inphase deposition modulated single phase five level ... · negative phase legs‟ switching...

INTERNATIONAL JOURNAL OF APPLIED SCIENCE ENGINEERING & MANAGEMENT, VOL 4, ISSUE 02

ISSN: 2454-9940

https://ijasem.org DOI: 02.03.2018-1519969975 Page | 1

Inphase Deposition Modulated Single Phase Five

Level Cascaded H- Bridge Multilevel Inverter

Mr. A.S. Mane

Ph.D. Student, Department of EE, Sant Gadge Baba Amravati University, Amravati, India

Dr. V. S. Bandal

Principal, Government Polytechnic, Karad, India

Keywords: Multilevel Inverter, Diode Clamped, Cascaded H-Bridge Multi level Inverter, Flying Capacitor Multi level Inverter, H-bridge ,Total

Harmonic Distortion (THD), SPWM.

I. Introduction

Power electronic converters, especially dc/ac PWM inverters have been extending their range of use in industry because they

provide reduced energy consumption, better system efficiency, improved quality of product, good maintenance, and so on. For a medium

voltage grid, it is troublesome to connect only one power semiconductor switches directly [1, 2, 3]. As a result, a multilevel power

converter structure has been introduced as an alternative in high power and medium voltage situations such as laminators, mills,

conveyors, pumps, fans, blowers, compressors, and so on. As a cost effective solution, multilevel converter not only achieves high power

ratings, but also enables the use of low power application in renewable energy sources such as photovoltaic, wind, and fuel cells which

can be easily interfaced to a multilevel converter system for a high power application. The most common initial application of multilevel

converters has been in high-voltage motor drive [3], traction both in locomotives and track-side static converters [4]. More recent

applications have been for power system converters for VAR compensation and stability enhancement [5], active filtering [6], high-

voltage dc transmission [7], and most recently for medium voltage induction motor variable speed drives [8]. Many multilevel converter

applications focus on industrial medium-voltage motor drives [3, 9], utility interface for renewable energy systems [10], flexible AC

transmission system (FACTS) [11], and traction drive systems [12]. The inverters in such application areas as stated above should be able

to handle high voltage and large power. For this reason, two-level high-voltage and large-power inverters have been designed with series

connection of switching power devices such as gate-turn-off thyristors (GTOs), integrated gate commutated transistors (IGCTs), and

integrated gate bipolar transistors (IGBTs), because the series connection allows reaching much higher voltages. However, the series

connection of switching power devices has big problems [13], namely, non-equal distribution of applied device voltage across series-

connected devices that may make the applied voltage of individual devices much higher than blocking voltage of the devices during

transient and steady-state switching operation of devices.

Abstract

Large electric drives and utility applications require advanced power electronics converter to meet the high power demands. As

a result, multilevel power converter structure has been introduced as an alternative in high power and medium voltage situations. A

multilevel converter not only achieves high power ratings, but also improves the performance of the whole system in terms of harmonics,

dv/dt stresses, and stresses in the bearings of a motor. Cascaded multilevel inverter is considered to be suitable for medium & high power

applications. Sine-triangle carrier modulation is identified as the most promising technique to reduce harmonics. The paper examines the

inphase deposition modulated single phase five level cascaded h- bridge multilevel inverter. The single phase five level cascaded

multilevel inverter is considered for study. The complete simulation of inphase modulation for five multilevel cascaded inverter i s

performed. The simulation is done in MATLAB-SIMULNIK and in-depth results are shown along with its total harmonic distortion value.

The results confirm effectiveness of proposed strategy.

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As alternatives to effectively solve the above-mentioned problems, several circuit topologies of multilevel inverter and

converter have been researched and utilized. The output voltage of the multilevel inverter has many levels synthesized from several DC

voltage sources. The quality of the output voltage is improved as the number of voltage levels increases, so the quantity of output filters

can be decreased. Multilevel inverter was first proposed in 1975. Separate DC-sourced full-bridge cells are placed in series to synthesize

a staircase AC output voltage. The term multilevel began with the three-level converter [14],[15]. Subsequently, several multilevel

converter topologies have been developed [16]. In 1981, diode-clamped multilevel inverter also called the Neutral-Point Clamped (NPC)

inverter schemes were proposed [17]. In 1992, capacitor-clamped (or flying capacitor) multilevel inverters, [18] and in 1996, cascaded

multilevel inverters were proposed [1], [19]. Although the cascade multilevel inverter was invented earlier, its application did not prevail

until the mid-1990s. The advantages of cascade multilevel inverters were prominent for motor drives and utility applications. The cascade

inverter has drawn great interest due to the great demand of medium-voltage high-power inverters. The cascade inverter is also used in

regenerative-type motor drive applications [20, 21]. Recently, some new topologies of multilevel inverters have emerged. This includes

generalized multilevel inverters [22], mixed multilevel inverter [23], hybrid multilevel inverters [24, 25] and soft-switched multilevel

inverters [26]. These multilevel inverters can extend rated inverter voltage and power by increasing the number of voltage levels. They

can also increase equivalent switching frequency without the increase of actual switching frequency, thus reducing ripple component of

inverter output voltage and electromagnetic interference effects. A multilevel converter can be implemented in many different ways. The

simplest techniques involve the parallel or series connection of conventional converters to form the multilevel waveforms [27]. More

complex structures effectively insert converters within converters [28]. The voltage or current rating of the multilevel converter becomes

a multiple of the individual switches, and so the power rating of the converter can exceed the limit imposed by the individual switching

devices.

The elementary concept of a multilevel converter to achieve higher power is to use a series of power semiconductor switches

with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform. Capacitors,

batteries, and renewable energy voltage sources can be used as the multiple dc voltage sources. The commutation of the power switches

aggregate these multiple dc sources in order to achieve high voltage at the output; however, the rated voltage of the power semiconductor

switches depends only upon the rating of the dc voltage sources to which they are connected. Abundant modulation techniques and

control paradigms have been developed for multilevel converters such as sinusoidal pulse width modulation (SPWM), selective harmonic

elimination (SHE-PWM), space vector modulation (SVM), and others. In this paper inphase deposition sinusoidal pulse width modulated

single phase five level cascaded h- bridge multilevel inverter is used.

II. Single Phase Five Level Cascaded Multilevel Inverter: (CMLI)

The concept of this inverter is based on connecting H-bridge inverters in series to get a sinusoidal voltage output. The output

voltage is the sum of the voltages that are generated by each cell. The number of output voltage levels are (2n+1), where n is the number

of cells. The switching angles can be chosen in such a way that total harmonics distortion is minimized. One of the advantages of this

type of multilevel inverter is that it needs less number of components in comparison to the Diode clamped or the flying capacitor, which

results in reduction of weight as well as cost. [30], [31], [32]. Cascade inverters are ideal for an induction motor that has many separate

dc sources (batteries) available for the individual H-bridges, these inverters are not an option for series hybrid induction motors because

cascade inverters cannot be easily connected back-to-back. For series-configured induction motors where an onboard combustion engine

generates ac power via an alternator or generator, a multilevel back-to-back diode clamped converter drive can best interface with the

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ISSN: 2454-9940


source of ac power and yet still easily meet the high power and/or high voltage requirements of the induction motor.[33], [34].

The converter topology is based on the series connection of single-phase inverters with separate dc sources. Fig.2 shows the

power circuit for one phase leg of five level cascaded inverter. The resulting phase voltage is synthesized by the addition of the voltages

generated by the different cells. In a 3-level cascaded inverter each single-phase full-bridge inverter generates three voltages at the

output: +Vdc, 0, -Vdc (zero, positive dc voltage, and negative dc voltage). This is made possible by connecting the capacitors

sequentially to the ac side via the power switches. The resulting output ac voltage swings from -Vdc to +Vdc with three levels, -2Vdc to

+2Vdc with five-level. The staircase wave form is nearly sinusoidal, even without filtering. Fig.1shows single phase five-level cascaded

multilevel inverter.

Fig.1. Circuit Diagram of single phase five level Cascaded H-Bridge Multilevel Inverter.

• For an output voltage level Vo = Vdc, S11, S41 and S12, S42 are turned ON

• For an output voltage level Vo = Vdc/2, S11, S41 are turned ON

• For an output voltage level Vo = 0, all switches are turn OFF

• For an output voltage level Vo = -Vdc, S21, S31 and S22, S32 are turned ON

• For an output voltage level Vo = -Vdc/2, S21, S31are turned OFF.

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Table-1 Switching State of the Five-Level Cascaded H-Bridge Multilevel Inverter.

Voltage

Vo

Switching sequence

S11 S21 S31 S41 S12 S22 S32 S42

Vao 1 0 0 1 1 0 0 1

Vdc 0 0 1 0 0 0 0 0

Vdc/2 0 0 0 0 0 0 0 0

o 0 0 0 0 0 0 0 0

-Vdc 0 1 1 0 0 0 0 0

-Vdc/2 0 1 1 0 0 1 1 0

Note- 1- means ON State, 0 - means OFF State

Cascaded H-Bride (CHB) configuration has recently become very popular in high power AC supplies and adjustable-speed

drive applications. Each H-bridge unit has its own dc source, which for an induction motor would be a battery unit, fuel cell or solar cell.

Each SDC (separate D.C. source) is associated with a single phase full-bridge inverter. The ac terminal voltages of different level

inverters are connected in series. Through different combinations of the four switches, S1-S4, each converter level can generate three

different voltage outputs, +Vdc, -Vdc and zero. The AC outputs of different full bridge converters in the same phase are connected in

series such that the synthesized voltage waveform is the sum of the individual converter outputs. Note that the number of output-phase

voltage levels is defined in a different way from those of the two converters (i.e. diode Clamped and flying capacitor). In this topology,

the number of output-phase voltage levels is defined by m=2N+1, where N is the number of DC sources. A five-level cascaded converter,

for example, consists of two DC sources and two full bridge converters. Minimum harmonic distortion can be obtained by controlling the

conducting angles at different converter levels. Each H- bridge unit generates a quasi-square waveform by phase shifting its positive and

negative phase legs‟ switching timings. Each switching device always conducts for 180° (or half cycle) regardless of the pulse width of

the quasi-square wave. This switching method makes all of the switching devices current stress equal. In the motoring mode, power flows

from the batteries through the cascade inverters to the motor. In the charging mode, the cascade converters act as rectifiers, and power

flows from the charger (ac source) to the batteries. The cascade converters can also act as rectifiers to help recover the kinetic energy of

the vehicle if regenerative braking is used. The cascade inverter can also be used in parallel HEV configurations. This new converter can

avoid extra clamping diodes or voltage balancing capacitors. The combination of the 180° conducting method and the pattern-swapping

scheme make the cascade inverters voltage and current stresses the same and battery voltage balanced. Identical H-bridge inverter units

can be utilized, thus improving modularity and manufacturability and greatly reducing production costs. Battery-fed cascade inverter

prototype driving an induction motor at 50% and 80% rated speed both the voltage and current are almost sinusoidal. Electromagnetic

interference (EMI) and common mode voltage are also much less than what would result from a PWM inverter because of the inherently

low dv/dt and sinusoidal voltage output.

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III. Modulation Topologies of Multi Level Inverters:

The multilevel topology involves several modulation techniques. Each technique involves different modulation methods. The

well-known modulation topologies for multilevel inverters as follows:

• Sinusoidal or “Sub harmonic” Natural Pulse Width Modulation (SPWM).

• Selective Harmonic Eliminated Pulse Width Modulation (SHE PWM) or

Programmed-Waveform Pulse Width Modulation (PWPWM).

• Optimized Harmonic Stepped-Waveform Technique (OHSW).

The advent of the transformer less multilevel inverter topology has brought forth various pulse width modulation (PWM)

schemes as a means to control the switching of the active devices in each of the multiple voltage levels in the inverter. The most efficient

method of controlling the output voltage is to incorporate pulse width modulation control (PWM control) within the inverters. In this

method, a fixed d.c. input voltage is supplied to the inverter and a controlled A.C. output voltage is obtained by adjusting the on and–off

periods of the inverter devices. Voltage-type PWM inverters have been applied widely to such fields as power supplies and motor drivers.

This is because such inverters are well adapted to high-speed self-turn-off switching devices that, as solid-state power converters, are

provided with recently developed advanced circuits; and they are operated stably and can be controlled well.

Fig. 2: Multilevel Modulation Techniques

From the above all mentioned PWM control methods, the Sinusoidal pulse width modulation (SPWM) is applied in the proposed inverter

since it has various advantages over other techniques. Sinusoidal PWM inverters provide an easy way to control amplitude, frequency

and harmonics contents of the output voltage. Sinusoidal pulse width modulation (SPWM) is one of the primitive techniques, which are

used to suppress harmonics presented in the quasi-square wave. In the modulation techniques, there are two important defined

parameters:

1) The ratio P = fc/fm known as frequency ratio, and

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2) The ratio Ma = Am/Ac known as modulation index, where fc is the reference frequency, fm is the carrier frequency, Am is

reference signal amplitude and Ac is carrier signal amplitude.

For NPC multilevel inverters, most carrier based modulation strategies derive from disposition techniques developed by Carrara

et al, where for an M level inverter, M-1 carriers of identical frequency and amplitude are arranged to occupy contiguous bands

between +Vdc and -Vdc.

These carriers can be arranged in:

• Alternative Phase Opposition Disposition (APOD), where each carrier is phase shifted by 1800 from its

adjacent carriers.

• Phase Opposition Disposition (POD) where the carriers above the reference zero point is out of phase with those

below the zero point by 1800 .

Phase Disposition (PD) where all carriers are in phase

IV. In Phase Disposition (IPD)

In this paper I have discuss using In Phase Disposition (IPD). The present work, in the carrier-based implementation

the phase disposition PWM scheme is used. Figure 3 demonstrates the sine-triangle method for a three-level inverter. Therein,

the a-phase modulation signal is compared with two (n-1 in general) triangle waveforms. The rules for the in phase disposition

method are

When the number of level N = 3,then N –1 = 3-1=2 carrier waveforms are arranged so that every carrier is in phase.

The converter is switched to +Vdc/ 2 when the reference is greater than both carrier waveforms.

The converter is switched to zero when the reference is greater than the lower carrier waveform but less than the upper

carrier waveform.

The converter is switched to - Vdc/ 2 when the reference is less than both carrier waveforms.

In the carrier-based implementation, at every instant of time the modulation signals are compared with the carrier and

depending on which is greater, the switching pulses are generated. As seen from Figure 3, the figure illustrates the switching

pattern produced by the carrier-based PWM scheme. In the PWM scheme there are two triangles, the upper triangle ranges from

1 to 0 and the lower triangle ranges from 0 to –1. In the similar way for an N –level inverter, the (N-1) triangles are used and

each has a peak-to-peak value of 2/ (N-1). Hence the upper most triangle magnitude varies from 1 to (1-2/ (N-1)), second carrier

waveform from (1-4/ (N-1)), and the bottom most triangle varies from (2-2/ (N-1)) to –1.

In Figure 4, simulation of carrier-based Modulation Techniques PWM scheme using the in phase disposition (IPD)

can be seen. The switching function for the devices is given by

Ha > Triangle -1 & Triangle -2; Ha3 =1, otherwise Ha3 =0.

Ha < Triangle -1 & Ha > Triangle -2; Ha2 =1, otherwise Ha2 =0.

Ha < Triangle -1 & Triangle -2; Ha1 =1, otherwise Ha1 =0.

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It is clear from the figure that during the positive cycle of the modulation signal, when the modulation is greater than

Triangle 1 and Triangle 2, then S1ap and S2ap are turned on and also during the positive cycle S2ap is completely turned on.

When S1ap and S2ap are turned on, the converter switches to the + Vdc / 2.When S1an and S2ap are on, the converter switches

to zero and hence during the positive cycle S2ap is completely turned on and S1ap and S1an will be turning on and off and

hence the converter switches from + Vdc / 2 to 0.During the negative half cycle of the modulation signal the converter switches

from 0 to - Vdc / 2.

Fig.3. Switching pattern produced using the IPD carrier-based PWM scheme: (a) two triangles and the modulation signal (b)

S1ap (c) S2ap (d) S1an (e) S2an

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Fig. 4. Simulation of carrier-based PWM scheme using the in phase disposition (IPD). (a). Modulation signal and in-phase carrier waveforms (b) Phase “a” output voltage.

For Cascaded Inverters, the common modulation strategy is to use continuous three levels PWM within each

individual inverter, with phase shifted carriers between the cascaded inverters of each phase leg to achieve optimum harmonic

cancellation within the phase leg. Recent work has shown that this modulation strategy achieves the same harmonic

performance as the APOD technique for NPC inverters when the switching frequencies are normalized so as to achieve the

same overall number of switching transitions per fundamental cycle. From this understanding, an improved modulation strategy

for Cascaded inverters has been developed using a discontinuous three level PWM strategy with 1800 phase shifted carriers

within each full bridge inverter, which achieves the same harmonic performance on a line- to-line basis as does PD modulation

for a NPC inverter. Since the Hybrid inverter topology is derived from the Cascaded structure it is reasonable to expect that a

similar situation exists for the Hybrid inverter.

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V. Simulation of Single Phase five level Cascaded Multilevel Inverter

Model Parameters:

Vdc1 = 120V;

Vdc2 = 120V;

Motor – single phase 1hp CSCR motor;

Simulation Tool: Matlab/Simulink 2017a

PID Parameters:

Kp = 0.0015688

Ki = 0.022212

Kd = 0.00001

Controller type : Discrete Parallel form PID

Sampling Time : 5x10-5 s

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Fig.5. Simulink diagram of cascaded H-bridge five level inverter connected to single phase 1-HP motor

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Fig.6. PWM generation using in-phase disposition and PID controller for speed control.

Fig.7 Generated PWM pulses to the switches in the inverter

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Fig.8. Triangular waves and sine wave signals used for IPD SPWM generation method. Here 4 triangle generators are used for 4

level (zero level not considered). Switches corresponding to the level are triggered when sine amplitude is greater than triangle.

Fig.9. PID controller graphs. (i) represents the output control signal generated by the PID controller in order to reach set point.

(ii) Is the error signal given to the PID input, which is difference between sepoint and actual speed. (iii) Graph of the actual motor

speed in RPM, here RPM is varied in two steps. First at t=0 setpoint = 800 and then at t = 4 setpoint is 1400, hence the reference

tracking can be seen with step change in setpoint

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Fig.10. Motor data from measurement bus of motor block. (i) Graph of the current taken by stator winding of the motor in

Amperes (ii)Rotor speed of the motor in RPM (iii) Electromagnetic torque generated on the rotor in Nm

Fig.11. Voltage waveform of the five level inverter at the input of LC filter. The waveform is distorted from is original five level

shape.

Fig.12. Voltage waveform of the five level inverter at the output of LC filter. Next two figures show expanded view of the

waveforms for different RPM’s of motor

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Fig.13. Expanded view of the motor voltage at 800RPM

Fig.14. Expanded view of the motor voltage at 1400RPM As seen from the above figures, motor voltage distortion reduces as the

motor RPM reaches to its maximum level as motor gets every input as per its rated values. Same effect is observed in next

simulation conditions where motor speed is varied in three steps 800RPM, 1000RPM and 1200RPM.

Fig.15. RPM Voltage of the five level inverter at the output of LC filter.

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Fig.16. PID controller graphs. (i) represents the output control signal generated by the PID controller in order to reach set point.

(ii) Is the error signal given to the PID input, which is difference between sepoint and actual speed. (iii) Graph of the actual motor

speed in RPM, here RPM is varied in two steps. First at t=0 setpoint = 800 and then at t = 4 setpoint is 1000, and at t= 6, setoint is

1200

Fig.17. Motor data from measurement bus of motor block. (i) Graph of the current taken by stator winding of the motor in

Amperes (ii)Rotor speed of the motor in RPM (iii) Electromagnetic torque generated on the rotor in Nm

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Fig.18. Voltage waveform of the five level inverter at the output of LC filter. Next two figures show expanded view of the

waveforms for different RPM’s of motor (1000RPM and 1200RPM)



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VI. Conclusion

Multi-level converters can achieve an effective increase in overall switch frequency through the cancellation of the lowest order

switch frequency terms. In phase deposition modulated single phase five level cascaded h- bridge multilevel inverter is studied and

simulated. PWM methods are advantageous in controlling the output voltage and reducing the harmonics. The PWM output spectra were

calculated from basic operation as explained above in-phase disposition method and simulated using MATLAB (SIMULINK).The in-

depth analysis of results confirms the advantages explained and effectiveness of proposed strategy.

Acknowledgment

I would like to thanks Principal, Head of Electrical Engineering Department of Sant. Gajanan Maharaj College of Engineering, Shegaon for providing

me a laboratory for my research work.

References:

[1] J. S. Lai and F. Z. Peng, “Multilevel converters – A new breed of power converters,” IEEE Trans. Ind. Application., vol. 32, pp. 1098–1107,

May/June 1996.

[2] J. Rodriguez, J.-S. Lai, and F. Z. Peng, "Multilevel inverters: a survey of topologies, controls, and applications," IEEE Trans. Ind. Electron., vol.

49, pp. 724-738, 2002.

[3] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, "Multilevel converters for large electric drives," IEEE Trans. Ind . Applicat., vol. 35, pp. 36-44,

1999.

[4] H. Stemmler. Power electronics in electric traction applications. IEEE conference of Industrial Electronics, Control and Inst rumentation,

IECON’93, 2:7 07 – 713, 1993.

[5] H. Fujita, S. Tominaga, and H. Akagi. Analysis and design of an advanced static VAR compensator using quad-series voltage-source inverters.

IEEE Industry Apps Meeting, 3:2565–2572, 1995.

[6] Y. Yoshioka, S. Konishi, N. Eguchi, M. Yamamoto, K. Endo, K. Maruyama, and K. Hino. Self-commutated static flicker compensator for arc

furnaces. In IEEE Applied Power Electronics Conference, volume 2, pages 891–897, 1996.

[7] L. Gyugyi, "Power electronics in electric utilities: static var compensators.," Proc. IEEE, vol. 76, pp. 3, 1987.

[8] Peter W. Hammond. A new approach to enhance power quality for medium voltage AC drives. IEEE Trans. Industry Applications, 33(1):202–

208, January 1997.

[9] M. F. Escalante, J. C. Vannier, and A. Arzande “Flying Capacitor Multilevel Inverters and DTC Motor Drive Applications,” IEEE Transactions on

Industry Electronics, vol. 49, no. 4, Aug. 2002, pp. 809-815.

[10] L. M. Tolbert, F. Z. Peng, “Multilevel Converters as a Utility Interface for Renewable Energy Systems,” in Proceedings of 2000 IEEE Power

Engineering Society Summer Meeting, pp. 1271-1274.

[11] L. M. Tolbert, F. Z. Peng, T. G. Habetler, “A Multilevel Converter-Based Universal Power Conditioner,” IEEE Transactions on Industry

Applications, vol. 36, no. 2, Mar./Apr. 2000 pp.596-603.

[12] L. M. Tolbert, F. Z. Peng, T. G. Habetler, “Multilevel Inverters for Electric Vehicle Applications,” IEEE Workshop on Power Electronics in

Transportation, Oct 22-23, 1998, Dearborn, Michigan, pp. 1424-1431. 89

[13] In-Dong Kim, Eui-Cheol Nho, , Heung-Geun Kim, , and Jong Sun Ko,. ‘A Generalized Undeland Snubber for Flying Capacitor Multilevel

Inverter and Converter‟.IEEE transactions on industrial electronics, vol. 51, no. 6, December 2004.

[14] R. H. Baker and L. H. Bannister, “Electric Power Converter,” U.S. Patent 3 867 643, Feb. 1975.

[15] A. Nabae, I. Takahashi, and H. Akagi, “A New Neutral-point Clamped PWM inverter,” IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518-523,

Sept./Oct. 1981.

[16] F. Z. Peng and J. S. Lai, “Multilevel Cascade Voltage-source Inverter with Separate DC source,” U.S. Patent 5 642 275, June 24, 1997 .

[17] N. S. Choi, J. G. Cho, and G. H. Cho, “A general circuit topology of multilevel inverter,” in Proc. IEEE PESC’91, 1991, pp. 96–103.

[18] T. A. Meynard and H. Foch, “Multilevel conversion: High voltage choppers and voltage source inverters,” in Proc. IEEE PESC’92, 1992, pp.

397–403.

[19] F. Z. Peng, J.-S. Lai, J. Mckeever, and J. VanCoevering, “A multilevel voltage-source inverter with separate DC source for static var generation,”

in Conf. Rec. IEEE-IAS Annu. Meeting, 1995, pp. 2541–2548.

[20] P. W. Hammond, "Four-quadrant AC-AC drive and method," U.S. Patent 6 166 513, Dec. 2000.

[21] M. F. Aiello, P. W. Hammond, and M. Rastogi, "Modular multi-level adjustable supply with series connected active inputs," U.S. Patent 6 236

580, May 2001.

[22] F. Z. Peng, "A generalized multilevel inverter topology with self voltage balancing," IEEE Trans. Ind. Applicat., vol. 37, pp. 611-618, 2001.

[23] W. A. Hill and C. D. Harbourt, "Performance of medium voltage multi-level inverters," Conf. Rec. IEEE-IAS Annu. Meeting, 1999, pp. 1186-92.

[24] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, "Hybrid multilevel power conversion system: a competitive solution for high-power

applications," IEEE Trans. Ind. Applicat., vol. 36, pp. 834- 841, 2000.

[25] Y.-S. Lai and F.-S. Shyu, "Topology for hybrid multilevel inverter," IEE Proc. Electr. Power Applicat., vol. 149, pp. 449-458, 2002.

[26] B.-M. Song, J. Kim, J.-S. Lai, K.-C. Seong, H.-J. Kim, and S.-S. Park, "A multilevel soft switching inverter with inductor coupling," IEEE Trans.

Ind. Applicat., vol. 37, pp. 628-36, 2001. 90

[27] E. Cengelci, S. U. Sulistijo, B. O. Woom, P. Enjeti, R. Teodorescu, and F. Blaabjerg, “A New Medium Voltage PWM Inverter Topo logy for

Adjustable Speed Drives,” in Conf. Rec. IEEE-IAS Annu. Meeting, St. Louis, MO, Oct. 1998, pp. 1416-1423.

[28] P. Jahn, and H. Leichtfried: „Traction equipment of the class 1822 dual-system locomotive‟, ABB Rev., 1992, (4), pp. 15-22.

[29] A. Nabae, I. Takahashi, and H. Akagi, „A new neutral point clamped PWM inverter‟, ZEEE Trans., 1981, 1A-17, (5), pp.518-523.

https://ijasem.org/


ISSN: 2454-9940


[30] Mohammad Farhadi Kangarlu, Student Member, IEEE, and Ebrahim Babaei, Member, IEEE A Generalized Cascaded Multilevel Inverter Using

Series Connection of Sub multilevel Inverters IEEE transactions on power electronics, vol. 28, no. 2, February 2013 pp: 625-636.

[31] Farid Khoucha, Soumia Mouna Lagoun, Khoudir Marouani, Abdelaziz Kheloui, and Mohamed El Hachemi Benbouzid, Senior Member, IEEE

Hybrid Cascaded H-Bridge Multilevel-Inverter Induction-Motor-Drive Direct Torque Control for Automotive Applications IEEE transactions on

energy conversion, vol. 28, no.3, September 2013 pp: 43-651.

[32] Effrey Ewanchuk, John Salmon, and Behzad Vafakhah, “A Five-/Nine-Level Twelve- Switch Neutral-Point-Clamped Inverter for High-Speed

Electric Drives”, IEEE Trans On Industry Applications, Vol. 47, No. 5, pp. 2145-2153, Sept/Oct 2011.

[33] Mariusz Malinowski, K. Gopakumar, Jose Rodriguez and Marcelo A. Perez “A Survey on Cascade Multilevel inverters”, IEEE Trans. Ind.

Electron. , vol. 57, no. 7, July 2010.’

[34] Mohamed S. A. Dahidah,Georgios Konstantinou, and Vassilios G. Agelidis, “SHE-PWM and Optimized DC Voltage Levels for Cascaded

Multilevel Inverters Control”, IEEE Symposium On Industrial Electronics And Applications(ISIEA 2010), pp. 143 -148,Oct 2010.

[35] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats,and M. A. Perez, “Multilevel converters: An enabling

technology for high-power applications,” Proc. IEEE , vol. 97, no. 11, pp. 1786–1817, Nov. 2009.

[36] Surin Khomfoi and Leon M. Tolbert, “Chapter 17 Multilevel power converter” Power electronic Handbook, Elsevier Publications.

[37] F. Z. Peng and J. S. Lai, “Multilevel Cascade Voltage-source Inverter with Separate DC source,” U.S. Patent 5 642 275, June 24, 1997.

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