ingrid: the integration of a grid onto a pixel anode by means of wafer post processing technology
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InGrid: the integration of a grid onto a pixel anode by means of Wafer Post Processing technology. 16 April 2008 Victor M. Blanco Carballo. Overview. Our wafer post processing requirements Concept and materials requirements Fabrication process Advanced processing Conclusions. - PowerPoint PPT PresentationTRANSCRIPT
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InGrid: the integration of a grid onto a pixel anode by means of Wafer Post Processing
technology 16 April 2008
Victor M. Blanco Carballo
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Overview
• Our wafer post processing requirements
• Concept and materials requirements
• Fabrication process
• Advanced processing
• Conclusions
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Wafer post processing
• Use microelectronics to add functionalities
• Chip still functional after process
-Temperature budget
-Plasma damage
-Stress
• Wafer level and chip level post-processing
• Suitable for Medipix, Timepix, Gosssipo, PSI-46…(general purpose process)
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Integrated Micromegas
Pixel padSupporting pillar
Grid
Cathode
•Use the chip as electronics•Perfect alignment holes to pixels•No dead areas•Geometry freedom•No manual manufacturing
CMOS chip
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Materials for the structures
• SU-8 negative photoresist for insulating pillars– Easy to define structures by lithography
– Low temperature process (below 95 °C)
– Suitable thickness range (2μm to 1mm)
– Insulating as Kapton foil (3MV/cm)
– Some radiation hardness data available
• Aluminum for conductive grid– Commonly used in microelectronics
– Easy to deposit
– Easy to pattern
– Low residual stress
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InGrid: Integrated Grid
1)Pre-process chip 2)Spin SU-8
3)UV exposure 4)Deposit metal
5)Pattern metal 6)Develop resist
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1) Pixel enlargement•Increase sensitive area for better charge collection•Pixel enlargement done by lift-off
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2) a-Si deposition (Neuchatel)
30μm a-Si3μm a-Si
•For later steps a-Si topography seems not to limit lithography performance
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3) SU-8 supporting structures
•Pillars tipically ~50μm tall and 30μm diameter
•Sparsed according to the pitch of the chip
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4)The integrated device
-Chip+a-Si+grid supported by insullating pillars
-Pillars in the middle of four pixels
-Perfect alignment hole to pixel
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Grid profile~1μm variation in grid roughness
Low gain fluctuations due to mechanical imperfections
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And the system is robust
- A scratch occurred during fabrication but system works
-Several months working in Helium/Isobutane
-Several months working in Argon/Isobutane
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An homogeneous response
No Moire effect
Scratch in the grid
Nut image after 55Fe irradiation
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Single electron counting possible•Charge spread over chip area
•55Fe spectrum reconstructed from single electron counting and TOT mode
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Electroplated grid
•Thicker and more robust grid possible
•Copper instead of aluminum
•Other materials possible by plating
CMOS chip
Unexposed SU-8
Exposed SU-8
Seed metal layer
Molding resist
Plated metal
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TwinGrid
1)First InGrid 2)Deposit resist
3)UV exposure 4)Deposit metal
5)Pattern metal 6)Develop structure
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And it works• Voltage on top grid, middle grid floating• Next step integrate on a chip with voltage on both
electrodes
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Triple grid•Follow same fabrication scheme
•Lower electric field facing the chip in Twingrid and triple grid
-reduce spark risk? reduce a-Si thickness needed?
•Intentionally misaligned grids can reduce ion-back flow?
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Conclusions
• Medipix/Timepix/Gossipo+a-Si+InGrid working• Wafer and chip level processing possible• Lot of freedom in the fabrication process• GEM-like structures seem feasible
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Special thanks to you and
• SC group (Tom, Arjen, Bijoy, Jurriaan, Joost, Jiwu,Sander,Cora)
• Mesa+ lab (Dominique, Hans)• NIKHEF(Max,Martin,Yevgen,Jan,Joop,Harry,
Fred) • Philips (Eugene)• NXP (Rob)• STW
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SU-8 radiation hardness
Mylar fluence of 7.5 1018 n cm2 ~ dose 106–107 Gy
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And they look great in 3D
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2D tracks projections
Cosmic rays Strontium
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