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industrial computing module

Ver. 0.6 – 18. 03 2020

DataSheet

byteENGINE AM437x

2 Datasheet_byteENGINE_AM437x ©bytes at work

Datasheet industrial computing module byteENGINE AM437x

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3Datasheet_byteENGINE_AM437x ©bytes at work


Table of Contents

1. Hardware Revisions 42. Revisions history 42.1 Hardware revision 0.2 4

3. Overview 43.1 General Information 43.2 Technical Data 53.3 AM437x block diagram 63.4 Overview of AM437x Processors 73.5 Decision guidance byteENGINE AM437x 73.6 Dimensions of AM437x 83.7 AM437x connectors layout 83.8 Connectors - Neltron 2001S-100G and 2001S-60G 93.9 byteENGINE AM437x Connectors Overview 93.10 PinMux Tool - configuring the AM437x Processor 10

4. Pinouts 114.1 Carrier board connectors X1 114.2 Carrier board connectors X2 134.3 Carrier board connectors X3 164.4 Power Domains 184.5 Power supply 194.6 Boot Modes byteENGINE AM437x 19

5. Ordering Info 216. References 217. Contact information 22



2.1 Hardware revision 0.2

2. Revisions history

> 0.2 is the first version available on sales.

1. Hardware Revisions

Hardware Revision Marking on PCB Release Date

0.2 m3 Rev.02 2016

3. Overview

The byteENGINE AM437x is a high per-formance industrial oriented computing module. It allows a short time-to-market, while reducing development costs and substantial design risks.

The system on module (SOM) uses the Texas Instruments AM437x industri-

al applications processor family. The AM437x features a PowerVRTM SGX Graphics Accelerator Subsystem for 3D graphics acceleration.

The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) allows independent opera-

tion from the ARM processor. PRU-ICSS enables real-time protocols such as Eth-erCAT, PROFINET, EtherNet/IP, PROFIB-US, Ethernet Powerlink and Sercos.

3.1 General Information

Scalable platform

> The AM437x Processor Family consists of 5 PIN-compatible devices.

> Integrated Quad-core PRU-ICSS deliver support for Ethercat-, Profibus and other Fieldbus-Protocols.

> The module byteENGINE AM437x is the perfect basis for innovative developments.

Expandable design

> The module provides a matching Linux-Kernel. As a result, the byteENGINE offers flexibility for almost any requirement.

> The free available open-source code allows reliable functionality and maximum extensibility.



Feature DetailsCPU Architecture ARM® Cortex™ -A9

CPU Texas Instruments - see Chart for CPU-Models: „3.4 Overview of AM437x Processors“

Frequency (max.) 1000 MHz

Floating Point YES (NEON™, SIMD & VFPv3)

PRU Up to 4 PRUs (200 MHz)

Memory SDRAM 256 MB - 1.024 MB DDR3

Flash 8 GB up to 64 GB eMMC

Nor-Flash 4 MB (Bootloader)

EEPROM 32 KB (containing HW configuration)

Ethernet Speed 2x 10/100/1.000 (Mbit/s)

Multimedia Video Parallel RGB 24bit

2D/3D Graphics Power VR™ SGX530 (AM4379, AM4378 only)

Touchscreen Supported

Audio Yes

Expansion SD/MMC/SDIO 3

Serial McASP 2

SPI 5

I2C 3

UART 6

CAN 2

USB OTG 2 HS (2.0)

Miscellaneous Watchdog Timers 1

GPMC Yes (Full Pinout)

JTAG Yes

Serial Console 1

GPIO 4x 32 GPIOS

PWM / ECAP / QEP 3

HRPWM 6

Boot Mode Selectable with Strapping Pins on Baseboard

Mechanical Information

Input Voltage 3 - 5 V

Power Consumption ~2 W

Dimensions 40 x 40 x 5 mm

Operational Temperature -40 to +85 °C

Connector 2 x 100 pin + 1x60 pin

Operating System Linux (yocto) Yesmeta-bytesatwork available on github: follow LINK

5

3.2 Technical Data

LINK: meta-bytesatwork on github

https://github.com/bytesatwork/meta-bytesatwork




Key Features of AM437x

> ARM Cortex-A9 processor, scalable from 300MHz – 1GHz

> Advanced 3D graphics acceleration

> Quad core PRU-ICSS for industrial Ethernet protocols and position feedback control

> Robust hardware enablement for differentiated peripherals: Gigabit Ethernet, Display connectivity, USB 2.0, Flexible communications interfaces

> The scalable memory (up to 1GB) can be operated from -40˚ up to +85˚ Celsuis

3.3 AM437x block diagramTI’s Sitara™ AM437x Processor is based on scalable ARM Cortex-A9 core which is a high-perfor-mance processor designed around the high efficiency dual-issue superscalar. It delivers exceptional levels of performance and power efficiency with the functionality required for leading edge products across the broad range of consumer, networking, enterprise and mobile applications. The AM437x microprocessor contains the subsystems shown in the Functional Block Diagram:



3.4 Overview of AM437x Processors

3.5 Decision guidance byteENGINE AM437xThe following three steps help identifying the suitable TI Sitara™ AM437x Processor for the specific customer application.

AM437x Processors AM4372 AM4376 AM4377 AM4378 AM4379ARM Cortex-A8 MHz 600/800 300/ 800/

1000800/ 1000 800/ 1000 800/ 1000

3D Graphics acceleration U U U R RPRU-ICSS for industrial communication¹

U Quad-Core PRU-ICSS for Industrial pro-tocols

Quad-Core PRU-ICSS for Industrial protocols includ-ing EtherCAT and POWERLINK

Quad-Core PRU-ICSS for Industrial pro-tocols

Quad-Core PRU-ICSS for Industrial protocols includ-ing EtherCAT and POWERLINK

Cryptographic accelerators R R R R RSecure boot Available on AM437x Secure Boot devices onlySoftware Software and pin-for-pin compatible across devices

1 PRU-ICSS is a programmable real-time subsystem for industrial communication protocols.

> Step 2: The choice of needed eMMC capacity.

> Min: 8 GB (eMMC)

> Max: 64 GB (eMMC)

> Step 3: The choice of needed RAM capacity.

> Min: 256 MB (SDRAM)

> Max: 1.024 MB (SDRAM)

> CPU-Speed: 300 up to 1.000 MHz for details see „3.4 Overview of AM437x Processors“

> Step 1: The choice of needed CPU-Speed.

LINK Overview AM437x Processors: Texas Instruments Sitara™ AM437x Processors

LINK Datasheet PDF: AM437x Sitara™ Processors Datasheet

http://www.ti.com/processors/sitara-arm/am4x-cortex-a9/overview.html#

http://www.ti.com/lit/ds/symlink/am4372.pdf



3.6 Dimensions of AM437xThe following illustration shows all important dimensions for mounting andinstallation of the industrial computing module byteENGINE AM437x.

> All dimensions are indicated in millimetres (mm).

3.7 AM437x connectors layoutThe AM437x is connected to the carrier board with 260 pins on three module connectors (X1, X2 and X3). The following picture shows the location of the connec-tors on the bottom side of the byteENGINE.

NOTICEThe module is held in the connectors with a considerable retention force. To avoid damaging the connectors while removing the mod-ule, the use of an extraction tool is highly recommended.

LINK: Schematic of the connectors X1, X2 and X3

https://download.bytesatwork.io/documentation/byteENGINE/ressources/m3-connector.pdf



3.9 byteENGINE AM437x Connectors Overview

3.8 Connectors - Neltron 2001S-100G and 2001S-60G

The following illustration shows the „Default-Configuration“ of the byteENGINE AM437x. The function of the components shown in blue squares cannot be changed. The yellow squares show the module connectors X1, X2 and X3. The functions of X1, X2 and X3 can be adapted and each connector module serves multiple functions. The detailed pinout-functions are shown in chapter „4. Pinouts“

The byteENGINE uses three Neltron 0,5mm Board to Board Plug connectors.For more specific information about the connectors used, please visit:

LINK: Datasheet of Neltron 0,5mm Connectors

LINK: „3.5 Decision guidance byteENGINE AM437x“

https://download.bytesatwork.io/documentation/byteENGINE/ressources/Neltron_2000P.pdf



3.10 PinMux Tool - configuring the AM437x Processor

LINK: Pinmux Tool

NOTICEFollow the Link to PinMux Tool. You need to LOG-IN first. Then choose the AM437x Processor. See illustration for details.

The PinMux Utility is a software tool which provides a Graphical User Inter-face for configuring pin multiplexing set-tings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.

Results are output as C header/code files that can be imported into software development kits (SDKs) or used to configure customer‘s custom software.

LINK: Prepared Pinmux File

https://dev.ti.com/pinmux/app.html

https://download.bytesatwork.io/documentation/byteENGINE/ressources/byteEngineM3-20161027.pinmux



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X1 1 GND

X1 2 GND

X1 3 nc

X1 4 Reserved

X1 5 nc

X1 6 Reserved

X1 7 nc

X1 8 ADC0_VREFP ADC0_VREFP

X1 9 nc

X1 10 ADC0_VREFN ADC0_VREFN

X1 11 nc

X1 12 ADC1_VREFP ADC1_VREFP

X1 13 nc

X1 14 ADC1_VREFN ADC1_VREFN

X1 15 nc

X1 16 PWRONRSTn porz

X1 17 EMU1 EMU1 gpio3[8]

X1 18 nTRST nTRST

X1 19 EMU0 EMU0 gpio3[7]

X1 20 TMS TMS

X1 21 TDI TDI

X1 22 TCK TCK

X1 23 GND

X1 24 TDO TDO

X1 25 Reserved

X1 26 GND

X1 27 Reserved

X1 28 Reserved

X1 29 Reserved

X1 30 Reserved

X1 31 Reserved

X1 32 Reserved

X1 33 Reserved

X1 34 Reserved

X1 35

X1 36 Reserved

X1 37 Reserved

X1 38 Reserved

4.1 Carrier board connectors X1

4. PinoutsThe multiple pin configurations must be taken note when using processor signals.The pins of the module connectors are described in detail in the following tables.



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X1 39 AGND

X1 40 GND

X1 41 ADC0_AIN7 ADC0_AIN7
















X1 57 GNDX1 58 GNDX1 59 cam0_field cam0_field dss_

data21cam0_data10

spi2_sclk cam1_data10

EMU4 gpio4[2]

X1 60 cam1_field cam1_field xdma_event_intr7

ext_hw_trigger

cam0_data10

spi2_cs1 cam1_data10

ehrpwm1B gpio4[12] ehrpwm3A

X1 61 cam0_wen cam0_wen dss_data20

cam0_data11

spi2_d0 cam1_data11

EMU5 gpio4[3]

X1 62 cam1_wen cam1_wen xdma_event_intr8

pr1_edio_sof

cam0_data11

spi2_d1 cam1_data11

EMU11 gpio4[13] ehrpwm3B

X1 63 cam0_data9 cam0_data9 dss_data17

pr0_pru0_gpo[16]

spi2_cs3 pr0_pru0_gpi[16]

EMU8 gpio4[6]


pr0_pru0_gpo[17]


EMU9 gpio4[7] uart0_ctsn


pr0_pru0_gpo[15]


EMU7 gpio4[5] I2C2_SCL

X1 66 cam1_data8 cam1_data8 xdma_event_intr3

spi0_cs2 pr0_pru1_gpo[0]

spi2_d0 pr0_pru1_gpi[0]

EMU10 gpio4[8] uart0_rtsn

X1 67 cam0_data7 cam0_data7 mmc1_dat3

qspi_d3 ehrpwm1B gpio4[29]

X1 68 cam1_data7 cam1_data7 uart1_dtrn uart2_rtsn mmc2_dat3

pr0_pru1_gpo[15]

pr0_pru1_gpi[15]

pr1_edio_data_in1

gpio4[21]


qspi_d2 ehrpwm1A gpio4[28]

X1 70 cam1_data6 cam1_data6 uart1_dcdn uart2_ctsn mmc2_dat2

pr0_pru1_gpo[14]

pr0_pru1_gpi[14]

pr1_edio_data_in0

gpio4[20]


qspi_d1 ehrpwm3B gpio4[27]

X1 72 cam1_data5 cam1_data5 uart1_dsrn uart2_txd mmc2_dat1

pr0_pru1_gpo[13]

pr0_pru1_gpi[13]

pr1_edio_latch_in

gpio4[19]


cam1_wen qspi_d0 ehrpwm3A gpio4[26]

X1 74 cam1_data4 cam1_data4 uart1_rin uart2_rxd mmc2_dat0

pr0_pru1_gpo[12]

pr0_pru1_gpi[12]

pr1_edc_latch1_in

gpio4[18] uart0_dcdn

X1 75 cam0_data3 cam0_data3 mmc1_cmd

cam1_data11

qspi_csn gpio4[25]

X1 76 cam1_data3 cam1_data3 uart1_rtsn spi3_sclk mmc2_cmd

pr0_pru1_gpo[11]

pr0_pru1_gpi[11]

pr1_edc_latch0_in

gpio4[17]

X1 77 cam0_data2 cam0_data2 mmc1_clk cam1_data10

qspi_clk gpio4[24]

X1 78 cam1_data2 cam1_data2 uart1_ctsn spi3_cs0 mmc2_clk pr0_pru1_gpo[10]

pr0_pru1_gpi[10]

ehrpwm1_tripzone_input

gpio4[16]

X1 79 cam0_data1 cam0_data1 cam1_data8

I2C1_SCL pr0_pru1_gpo[17]

pr0_pru1_gpi[17]

ehrpwm3_synco

gpio5[20]

X1 80 cam1_data1 cam1_data1 uart1_txd spi3_d1 I2C2_SCL ehrpwm0_synci

gpio4[15]

X1 81 cam0_data0 cam0_data0 cam1_data9

I2C1_SDA pr0_pru1_gpo[16]

pr0_pru1_gpi[16]

ehrpwm0_synco

gpio5[19]

Follow link for explanation „4.3.1 Yellow and Pink Marked X2- and X3-Connectors“



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X1 82 cam1_data0 cam1_data0 uart1_rxd spi3_d0 I2C2_SDA ehrpwm0_

tripzone_input

gpio4[14]

X1 83 cam0_hd cam0_hd dss_data23

pr1_edio_sof

spi2_cs1 EMU10 EMU2 gpio4[0]

X1 84 cam1_hd cam1_hd xdma_event_intr4



ehrpwm0A gpio4[9]

X1 85 cam0_vd cam0_vd dss_data22

pr1_edio_outvalid

spi2_d1 EMU11 EMU3 gpio4[1]

X1 86 cam1_vd cam1_vd xdma_event_intr5



ehrpwm0B gpio4[10]

X1 87 cam0_pclk cam0_pclk dss_data19

pr0_pru0_gpo[14]


EMU6 gpio4[4] I2C2_SDA

X1 88 cam1_pclk cam1_pclk xdma_event_intr6


spi2_sclk pr0_pru1_gpi[3]

ehrpwm1A gpio4[11]

X1 89 GNDX1 90 GNDX1 91 USB1_ID USB1_ID

X1 92 USB0_ID USB0_ID

X1 93 USB1_VBUS USB1_VBUS

X1 94 USB0_VBUS USB0_VBUS

X1 95 USB1_DP USB1_DP

X1 96 USB0_DP USB0_DP

X1 97 USB1_DM USB1_DM

X1 98 USB0_DM USB0_DM

X1 99 USB1_DRVVBUS USB1_DRV-VBUS

gpio3[13] gpio0[25]

X1 100 USB0_DRVVBUS USB0_DRV-VBUS

gpio0[18] gpio5[27]



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X2 1 VinX2 2 VinX2 3 VinX2 4 VinX2 5 VinX2 6 VinX2 7 VinX2 8 VinX2 9 VinX2 10 VinX2 11 GNDX2 12 GNDX2 13 GNDX2 14 GNDX2 15 GNDX2 16 GNDX2 17 GNDX2 18 GNDX2 19 GNDX2 20 GND



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X2 21 GNDX2 22 +3.3V(VMMC)X2 23 VbackupX2 24 +3.3V(VMMC)X2 25 PB_Reset

(PMIC)X2 26 mmc0_clk mmc0_clk gpmc_a24 uart3_ctsn uart2_rxd dcan1_tx pr0_pru0_

gpo[12]pr0_pru0_gpi[12]

gpio2[30]

X2 27 GNDX2 28 mmc0_cmd mmc0_cmd gpmc_a25 uart3_rtsn uart2_txd dcan1_rx pr0_pru0_


gpio2[31]

X2 29 WARMRSTn nRESE-TIN_OUT

X2 30 mmc0_dat0 mmc0_dat0 gpmc_a23 uart5_rtsn uart3_txd uart1_rin pr0_pru0_gpo[11]

pr0_pru0_gpi[11]

gpio2[29]

X2 31 SYS_nRESETX2 32 mmc0_dat1 mmc0_dat1 gpmc_a22 uart5_ctsn uart3_rxd uart1_dtrn pr0_pru0_


gpio2[28]

X2 33 eCAP0_in_PWM0_out

eCAP0_in_PWM0_out

uart3_txd spi1_cs1 pr1_ecap0_ecap_cap-in_apwm_o

spi1_sclk mmc0_sdwp

xdma_event_intr2

gpio0[7] ehrpwm2B timer1

X2 34 mmc0_dat2 mmc0_dat2 gpmc_a21 uart4_rtsn timer6 uart1_dsrn pr0_pru0_gpo[9]

pr0_pru0_gpi[9]

gpio2[27]

X2 35 xdma_event_intr1

xdma_event_intr1

spi0_cs2 tclkin clkout2 timer7 pr1_pru0_gpi[16]

EMU3 gpio0[20] pr1_mdio_mdclk

gpio5[29]

X2 36 mmc0_dat3 mmc0_dat3 gpmc_a20 uart4_ctsn timer5 uart1_dcdn pr0_pru0_gpo[8]

pr0_pru0_gpi[8]

gpio2[26]

X2 37 mdio_clk mdio_clk timer5 uart5_txd uart3_rtsn mmc0_sdwp

mmc1_clk mmc2_clk gpio0[1] pr1_mdio_mdclk

X2 38 gpmc_clk gpmc_clk gpmc_wait1

mmc2_clk pr1_mii1_crs

pr1_mdio_mdclk

mcasp0_fsr

gpio2[1] gpio0[4]

X2 39 mdio_data mdio_data timer6 uart5_rxd uart3_ctsn mmc0_sdcd

mmc1_cmd

mmc2_cmd

gpio0[0] pr1_mdio_data

X2 40 gpmc_wait0 gpmc_wait0 gmii2_crs gpmc_csn4

rmii2_crs_dv

mmc1_sdcd

pr1_mii1_crs

uart4_rxd gpio0[30] gpio5[30]

X2 41 GNDX2 42 gpmc_be0n_cle gpmc_

be0n_clespi1_cs3 timer5 qspi_d3 pr1_mii1_

rxlinkgpmc_a5 spi3_cs1 gpio2[5]

X2 43 gpmc_ad8 gpmc_ad8 dss_data23

mmc1_dat0

mmc2_dat4

ehrpwm2A pr1_mii_mt0_clk

spi3_sclk gpio0[22] spi3_cs1 gpio5[26]

X2 44 gpmc_be1n gpmc_be1n gmii2_col gpmc_csn6

mmc2_dat3

gpmc_dir pr1_mii1_col

mcasp0_aclkr

gpio1[28]


mmc1_dat1

mmc2_dat5

ehrpwm2B pr1_mii0_col

spi3_d0 gpio0[23] gpio5[25]

X2 46 gpmc_wpn gpmc_wpn gmii2_rxer gpmc_csn5

rmii2_rxer mmc2_sdcd

pr1_mii1_rxer

uart4_txd gpio0[31] gpio5[31]


mmc1_dat2

mmc2_dat6


pr1_mii0_txen

spi3_d1 gpio0[26] gpio5[24]

X2 48 gpmc_ad0 gpmc_ad0 mmc1_dat0

gpio1[0] eMMC


mmc1_dat3

mmc2_dat7

ehrpwm0_synco

pr1_mii0_txd3

spi3_cs0 gpio0[27] gpio5[23]


gpio1[1] eMMC


mmc1_dat4

mmc2_dat0

eQEP2A_in pr1_mii0_txd2

pr1_pru0_gpi[10]

gpio1[12] mcasp0_aclkx

pr1_pru0_gpo[10]


gpio1[2] eMMC


mmc1_dat5

mmc2_dat1

eQEP2B_in pr1_mii0_txd1

pr1_pru0_gpi[11]

gpio1[13] mcasp0_fsx

pr1_pru0_gpo[11]


gpio1[3] eMMC


mmc1_dat6

mmc2_dat2

eQEP2_in-dex

pr1_mii0_txd0

pr1_pru0_gpi[16]

gpio1[14] mcasp0_axr0


gpio1[4] eMMC




Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X2 57 gpmc_ad15 gpmc_ad15 dss_

data16mmc1_dat7

mmc2_dat3

eQEP2_strobe

pr1_ecap0_ecap_cap-in_apwm_o

gpio1[15] mcasp0_axr1

spi3_cs1


gpio1[5] eMMC

X2 59 dss_data15 dss_data15 gpmc_a19 eQEP1_strobe

mcasp0_ahclkx

mcasp0_axr3

pr1_mii0_rxdv

uart5_rtsn gpio0[11] spi3_cs0


gpio1[6] eMMC

X2 61 dss_data14 dss_data14 gpmc_a18 eQEP1_in-dex

mcasp0_axr1

uart5_rxd pr1_mii_mr0_clk

uart5_ctsn gpio0[10] spi3_d1


gpio1[7] eMMC

X2 63 dss_data13 dss_data13 gpmc_a17 eQEP1B_in mcasp0_fsr

mcasp0_axr3

pr1_mii0_rxer

uart4_rtsn gpio0[9] spi3_d0

X2 64 gpmc_csn0 gpmc_csn0 qspi_csn gpio1[29]

X2 65 dss_data12 dss_data12 gpmc_a16 eQEP1A_in mcasp0_aclkr

mcasp0_axr2

pr1_mii0_rxlink

uart4_ctsn gpio0[8] spi3_sclk

X2 66 gpmc_csn1 gpmc_csn1 gpmc_clk mmc1_clk pr1_edio_data_in6

pr1_edio_data_out6

pr1_pru0_gpo[8]

pr1_pru0_gpi[8]

gpio1[30] eMMC

X2 67 dss_data11 dss_data11 gpmc_a15 ehrpwm1B mcasp0_ahclkr

mcasp0_axr2

pr1_mii0_rxd0

uart3_rtsn gpio2[17] spi3_cs1

X2 68 gpmc_csn2 gpmc_csn2 gpmc_be1n

mmc1_cmd

pr1_edio_data_in7

pr1_edio_data_out7

pr1_pru0_gpo[9]

pr1_pru0_gpi[9]

gpio1[31] gmii2_crs rmii2_crs_dv

eMMC

X2 69 dss_data10 dss_data10 gpmc_a14 ehrpwm1A mcasp0_axr0

pr1_mii0_rxd1

uart3_ctsn gpio2[16]

X2 70 gpmc_csn3 gpmc_csn3 gpmc_wait0

qspi_clk mmc2_cmd

pr1_mii0_crs

pr1_mdio_data

EMU4 gpio2[0] gmii2_crs rmii2_crs_dv

X2 71 dss_data9 dss_data9 gpmc_a13 ehrpwm0_synco

mcasp0_fsx

uart5_rxd pr1_mii0_rxd2

uart2_rtsn gpio2[15]

X2 72 gpmc_wen gpmc_wen spi1_cs2 timer6 qspi_d2 gpio2[4]

X2 73 dss_data8 dss_data8 gpmc_a12 ehrpwm1_tripzone_input

mcasp0_aclkx

uart5_txd pr1_mii0_rxd3

uart2_ctsn gpio2[14]

X2 74 gpmc_oen_ren gpmc_oen_ren

spi0_cs2 timer7 qspi_d1 gpio2[3]

X2 75 dss_data7 dss_data7 gpmc_a7 pr1_edio_data_in7

eQEP2_strobe

pr1_edio_data_out7

pr1_pru0_gpo[7]

pr1_pru0_gpi[7]

gpio2[13]

X2 76 gpmc_advn_ale gpmc_advn_ale

spi0_cs3 timer4 qspi_d0 gpio2[2]

X2 77 dss_data6 dss_data6 gpmc_a6 pr1_edio_data_in6

eQEP2_in-dex

pr1_edio_data_out6

pr1_pru0_gpo[6]

pr1_pru0_gpi[6]

gpio2[12]

X2 78 gpmc_a0 gpmc_a0 gmii2_txen rgmii2_tctl rmii2_txen gpmc_a16 pr1_mii1_txen


gpio1[16]

X2 79 dss_data5 dss_data5 gpmc_a5 pr1_mii0_txd0

eQEP2B_in pr1_pru0_gpo[5]

pr1_pru0_gpi[5]

gpio2[11]

X2 80 gpmc_a1 gpmc_a1 gmii2_rxdv rgmii2_rctl mmc2_dat0

gpmc_a17 pr1_mii1_rxdv

ehrpwm0_synco

gpio1[17]


eQEP2A_in pr1_pru0_gpo[4]

pr1_pru0_gpi[4]

gpio2[10]

X2 82 gpmc_a10 gpmc_a10 gmii2_rxd1 rgmii2_rd1 rmii2_rxd1 gpmc_a26 pr1_mii1_rxd1

mcasp0_axr0

gpio1[26]


ehrpwm0_synco

pr1_pru0_gpo[3]

pr1_pru0_gpi[3]

gpio2[9]

X2 84 gpmc_a11 gpmc_a11 gmii2_rxd0 rgmii2_rd0 rmii2_rxd0 gpmc_a27 pr1_mii1_rxd0

mcasp0_axr1

gpio1[27]



pr1_pru0_gpo[2]

pr1_pru0_gpi[2]

gpio2[8]

X2 86 gpmc_a2 gpmc_a2 gmii2_txd3 rgmii2_td3 mmc2_dat1

gpmc_a18 pr1_mii1_txd3

ehrpwm1A gpio1[18]

X2 87 dss_data1 dss_data1 gpmc_a1 pr1_mii0_txen

ehrpwm2B pr1_pru0_gpo[1]

pr1_pru0_gpi[1]

gpio2[7]


Follow link for explanation „4.3.1 Yellow and Pink Marked X2- and X3-Connectors“



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X2 88 gpmc_a3 gpmc_a3 gmii2_txd2 rgmii2_td2 mmc2_

dat2gpmc_a19 pr1_mii1_

txd2ehrpwm1B gpio1[19]

X2 89 dss_data0 dss_data0 gpmc_a0 pr1_mii_mt0_clk

ehrpwm2A pr1_pru0_gpo[0]

pr1_pru0_gpi[0]

gpio2[6]

X2 90 gpmc_a4 gpmc_a4 gmii2_txd1 rgmii2_td1 rmii2_txd1 gpmc_a20 pr1_mii1_txd1

eQEP1A_in gpio1[20]

X2 91 dss_pclk dss_pclk gpmc_a10 gpmc_a3 pr1_edio_data_in4

pr1_edio_data_out4

pr0_pru1_gpo[8]

pr0_pru1_gpi[8]

gpio2[24]

X2 92 gpmc_a5 gpmc_a5 gmii2_txd0 rgmii2_td0 rmii2_txd0 gpmc_a21 pr1_mii1_txd0

eQEP1B_in gpio1[21]

X2 93 dss_ac_bias_en dss_ac_bias_en

gpmc_a11 gpmc_a4 pr1_edio_data_in5

pr1_edio_data_out5

pr0_pru1_gpo[9]

pr0_pru1_gpi[9]

gpio2[25]

X2 94 gpmc_a6 gpmc_a6 gmii2_txclk rgmii2_tclk mmc2_dat4

gpmc_a22 pr1_mii_mt1_clk

eQEP1_in-dex

gpio1[22]

X2 95 dss_vsync dss_vsync gpmc_a8 gpmc_a1 pr1_edio_data_in2

pr1_edio_data_out2

pr0_pru1_gpo[6]

pr0_pru1_gpi[6]

gpio2[22]

X2 96 gpmc_a7 gpmc_a7 gmii2_rxclk rgmii2_rclk mmc2_dat5

gpmc_a23 pr1_mii_mr1_clk

eQEP1_strobe

gpio1[23]

X2 97 dss_hsync dss_hsync gpmc_a9 gpmc_a2 pr1_edio_data_in3

pr1_edio_data_out3

pr0_pru1_gpo[7]

pr0_pru1_gpi[7]

gpio2[23]

X2 98 gpmc_a8 gpmc_a8 gmii2_rxd3 rgmii2_rd3 mmc2_dat6

gpmc_a24 pr1_mii1_rxd3

mcasp0_aclkx

gpio1[24]

X2 99 GNDX2 100 gpmc_a9 gpmc_a9 gmii2_rxd2 rgmii2_rd2 mmc2_

dat7gpmc_a25 pr1_mii1_

rxd2mcasp0_fsx

gpio1[25] rmii2_crs_dv



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X3 1 gmii1_tx_clk gmii1_txclk uart2_rxd rgmii1_tclk mmc0_

dat7mmc1_dat0

uart1_dcdn mcasp0_aclkx

gpio3[9] gpio0[8]

X3 2 gmii1_rx_clk gmii1_rxclk uart2_txd rgmii1_rclk mmc0_dat6

mmc1_dat1

uart1_dsrn mcasp0_fsx

gpio3[10] gpio0[9]

X3 3 gmii1_tx_en gmii1_txen rmii1_txen rgmii1_tctl timer4 mcasp1_axr0

eQEP0_in-dex

mmc2_cmd

gpio3[3]

X3 4 gmii1_rx_dv gmii1_rxdv rgmii1_rctl uart5_txd mcasp1_aclkx

mmc2_dat0

mcasp0_aclkr

gpio3[4] gpio0[1]

X3 5 gmii1_txd3 gmii1_txd3 dcan0_tx rgmii1_td3 uart4_rxd mcasp1_fsx

mmc2_dat1

mcasp0_fsr

gpio0[16] gpio3[11]

X3 6 gmii1_rxd3 gmii1_rxd3 uart3_rxd rgmii1_rd3 mmc0_dat5

mmc1_dat2

uart1_dtrn mcasp0_axr0

gpio2[18] gpio0[10]

X3 7 gmii1_txd2 gmii1_txd2 dcan0_rx rgmii1_td2 uart4_txd mcasp1_axr0

mmc2_dat2

mcasp0_ahclkx

gpio0[17] gpio3[12]

X3 8 gmii1_rxd2 gmii1_rxd2 uart3_txd rgmii1_rd2 mmc0_dat4

mmc1_dat3

uart1_rin mcasp0_axr1

gpio2[19] gpio0[11]

X3 9 gmii1_txd1 gmii1_txd1 rmii1_txd1 rgmii1_td1 mcasp1_fsr

mcasp1_axr1

eQEP0A_in mmc1_cmd

gpio0[21]

X3 10 gmii1_rxd1 gmii1_rxd1 rmii1_rxd1 rgmii1_rd1 mcasp1_axr3

mcasp1_fsr

eQEP0_strobe

mmc2_clk gpio2[20]

X3 11 gmii1_txd0 gmii1_txd0 rmii1_txd0 rgmii1_td0 mcasp1_axr2

mcasp1_aclkr

eQEP0B_in mmc1_clk gpio0[28]

X3 12 gmii1_rxd0 gmii1_rxd0 rmii1_rxd0 rgmii1_rd0 mcasp1_ahclkx

mcasp1_ahclkr

mcasp1_aclkr

mcasp0_axr3

gpio2[21]

X3 13 GNDX3 14 GNDX3 15 gpio5_8 pr1_mii0_

colgpio5[8]

X3 16 gpio5_12 I2C1_SDA pr1_mii0_rxlink

gpio5[12]



Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X3 17 gpio5_9 pr1_mii1_

colgpio5[9]

X3 18 gpio5_13 pr1_mii1_rx-link

gpio5[13]

X3 19 gpio5_10 I2C1_SCL pr1_mii0_crs

gpio5[10]

X3 20 spi4_sclk spi4_sclk ehrpwm0_synci

gpio5[4]

X3 21 gpio5_11 pr1_mii1_crs

gpio5[11]

X3 22 spi4_d0 spi4_d0, synci

ehrpwm3_ gpio5[5]

X3 23 mii1_crs gmii1_crs rmii1_crs_dv

spi1_d0 I2C1_SDA mcasp1_aclkx

uart5_ctsn uart2_rxd gpio3[1]

X3 24 spi4_d1 spi4_d1 ehrpwm0_tripzone_input

gpio5[6]

X3 25 mii1_rx_er gmii1_rxer rmii1_rxer spi1_d1 I2C1_SCL mcasp1_fsx

uart5_rtsn uart2_txd gpio3[2]

X3 26 uart3_txd uart3_txd pr0_pru0_gpo[19]

pr0_pru0_gpi[19]

ehrpwm4B gpio5[3]

X3 27 mii1_col gmii1_col rmii2_ref-clk

spi1_sclk uart5_rxd mcasp1_axr2

mmc2_dat3

mcasp0_axr2

gpio3[0] gpio0[0]

X3 28 uart3_rxd uart3_rxd pr0_pru0_gpo[18]

pr0_pru0_gpi[18]

ehrpwm4A gpio5[2]

X3 29 rmii1_ref_clk rmii1_refclk xdma_event_intr2

spi1_cs0 uart5_txd mcasp1_axr3

mmc0_pow

mcasp1_ahclkx

gpio0[29]

X3 30 uart3_rtsn uart3_rtsn hdq_sio pr0_pru1_gpo[19]

pr0_pru1_gpi[19]

ehrpwm5B gpio5[1]

X3 31 xdma_event_intr0

xdma_event_intr0

ext_hw_trigger

timer4 clkout1 spi1_cs1 pr1_pru0_gpi[16]

EMU2 gpio0[19] pr1_mdio_data

gpio5[28]

X3 32 uart3_ctsn uart3_ctsn spi4_cs1 pr0_pru1_gpo[18]

pr0_pru1_gpi[18]

ehrpwm5A gpio5[0]

X3 33 mcasp0_aclkx mcasp0_aclkx

ehrpwm0A spi0_cs3 spi1_sclk mmc0_sdcd

pr0_pru0_gpo[0]

pr0_pru0_gpi[0]

gpio3[14]

X3 34 GNDX3 35 mcasp0_ahclkx mcasp0_ah-

clkxeQEP0_strobe

mcasp0_axr3

mcasp1_axr1

EMU4 pr0_pru0_gpo[7]

pr0_pru0_gpi[7]

gpio3[21] gpio0[3]

X3 36 uart1_txd uart1_txd mmc2_sdwp

dcan1_rx I2C1_SCL pr1_uart0_txd

pr1_pru0_gpi[16]

gpio0[15]

X3 37 mcasp0_aclkr mcasp0_aclkr

eQEP0A_in mcasp0_axr2

mcasp1_aclkx

mmc0_sdwp

pr0_pru0_gpo[4]

pr0_pru0_gpi[4]

gpio3[18] gpio0[18]

X3 38 uart1_rxd uart1_rxd mmc1_sdwp

dcan1_tx I2C1_SDA pr1_uart0_rxd

pr1_pru0_gpi[16]

gpio0[14]

X3 39 mcasp0_ahclkr mcasp0_ah-clkr

ehrpwm0_synci

mcasp0_axr2

spi1_cs0 eCAP2_in_PWM2_out

pr0_pru0_gpo[3]

pr0_pru0_gpi[3]

gpio3[17]

X3 40 uart1_ctsn uart1_ctsn timer6 dcan0_tx I2C2_SDA spi1_cs0 pr1_uart0_cts_n

pr1_edc_latch0_in

gpio0[12]

X3 41 mcasp0_fsx mcasp0_fsx ehrpwm0B spi1_cs2 spi1_d0 mmc1_sdcd

pr0_pru0_gpo[1]

pr0_pru0_gpi[1]

gpio3[15]

X3 42 uart1_rtsn uart1_rtsn timer5 dcan0_rx I2C2_SCL spi1_cs1 pr1_uart0_rts_n

pr1_edc_latch1_in

gpio0[13]

X3 43 mcasp0_fsr mcasp0_fsr eQEP0B_in mcasp0_axr3

mcasp1_fsx


pr0_pru0_gpi[5]

gpio3[19] gpio0[19]

X3 44 uart0_txd uart0_txd spi1_cs1 dcan0_rx I2C2_SCL eCAP1_in_PWM1_out

pr0_pru1_gpo[5]

pr0_pru1_gpi[5]

gpio1[11]

X3 45 mcasp0_axr0 mcasp0_axr0


spi1_cs3 spi1_d1 mmc2_sdcd

pr0_pru0_gpo[2]

pr0_pru0_gpi[2]

gpio3[16]

X3 46 uart0_rxd uart0_rxd spi1_cs0 dcan0_tx I2C2_SDA eCAP2_in_PWM2_out

pr0_pru1_gpo[4]

pr0_pru1_gpi[4]

gpio1[10]

X3 47 mcasp0_axr1 mcasp0_axr1

eQEP0_in-dex

mcasp1_axr0


pr0_pru0_gpi[6]

gpio3[20] gpio0[2]

X3 48 uart0_ctsn uart0_ctsn uart4_rxd dcan1_tx I2C1_SDA spi1_d0 timer7 pr1_edc_sync0_out

gpio1[8]

X3 49 GNDX3 50 uart0_rtsn uart0_rtsn uart4_txd dcan1_rx I2C1_SCL spi1_d1 spi1_cs0 pr1_edc_

sync1_outgpio1[9]

X3 51 spi0_cs0 spi0_cs0 mmc2_sdwp

I2C1_SCL ehrpwm0_synci

pr1_uart0_txd

pr0_uart0_txd

pr1_edio_data_out1

gpio0[5] ehrpwm1B SPI Bootflash

X3 52 GND




4.3.1 Yellow and Pink Marked X2- and X3-ConnectorsGPMC Pins available on X2 and X3 are shared with onboard eMMC Flash and SPI Bootflash. The yellow marked pins on X2 cannot be used freely, when eMMC is populated and used.The pink marked pin „SPI0_CS0“ on X3 is used for SPI Bootflash and not available if SPI-Boot is used.

For collision avoidance it is highly recommended to use the TI Pinmux tool to check your connectivity. A prepared pinmux file for byteENGINE M3 can be downloaded - follow links on the right side.

Please consult the „Power“ column in Table 4-10 of the AM437x Datasheet.

LINK: Prepared Pinmux File

Con Pin Signal Name Available Modes on Pin Note0 1 2 3 4 5 6 7 8 9X3 53 spi0_cs1 spi0_cs1 uart3_rxd eCAP1_in_

PWM1_outmmc0_pow

xdma_event_intr2

mmc0_sdcd

EMU4 gpio0[6] ehrpwm2A timer0

X3 54 spi2_cs0 spi2_cs0 I2C1_SDA ehrpwm2_tripzone_input

gpio3[25] gpio0[23]

X3 55 spi0_sclk spi0_sclk uart2_rxd I2C2_SDA ehrpwm0A pr1_uart0_cts_n

pr0_uart0_cts_n

EMU2 gpio0[2]

X3 56 spi2_sclk spi2_sclk I2C1_SCL ehrpwm4_tripzone_input

gpio3[24] gpio0[22]

X3 57 spi0_d0 spi0_d0 uart2_txd I2C2_SCL ehrpwm0B pr1_uart0_rts_n

pr0_uart0_rts_n

EMU3 gpio0[3]


gpio3[22] gpio0[20]

X3 59 spi0_d1 spi0_d1 mmc1_sdwp

I2C1_SDA ehrpwm0_tripzone_input

pr1_uart0_rxd

pr0_uart0_rxd

pr1_edio_data_out0

gpio0[4] ehrpwm1A


gpio3[23] gpio0[21]


4.4 Power Domains

ATTENTIONNot all pins are on the same voltage level. The pink marked „Power Domains“ in the Voltage-Chart require 1.8V. Ensure that these „Power Domains“ are provided in the design with the correct voltage. Furthermore: The potential use of level shifters is recommended.

LINK: AM437x Sitara™ Processors DatasheetTable 4.10 Pin Diagrams.

Power Domains VoltageVDDA_MC_ADC 1.8V

VDDA_TS_ADC 1.8V

VDDA3P3V_USB0 3.3V

VDDA3P3V_USB1 3.3V

VDDS_DDR VLS1

VDDS_OSC 1.8V

VDDSHV1 3.3V

VDDSHV2 3.3V

VDDSHV3 3.3V

VDDSHV5 3.3V

VDDSHV6 3.3V

VDDSHV7 3.3V

VDDSHV8 3.3V

VDDSHV9 1.8V

VDDSHV10 3.3V

VDDSHV11 1.8V

LINK: Pinmux Tool

https://download.bytesatwork.io/documentation/byteENGINE/ressources/PinmuxConfigSummary-byteEngineM3-20161027.xlsx





4.5 Power supply > The byteENGINE can be powered with 2.7V to 5.5V.

> The recommended power supply is 5V.

LINK: TPS65910x Integrated Power-Management Unit

4.6 Boot Modes byteENGINE AM437x4.6.1 Booting procedureFirst a booting device list is created. The list consists of all devices which will be searched for a booting image. The list is filled in based on the SYSBOOT. Once the booting device list is set up, the booting routine examines the devices enumerated in the list sequentially and either executes the memory booting or peripheral booting proce-dure depending on the booting device type.

The following illustration showsthe booting procedure:

> The memory booting procedure is executed when the booting device is a memory type like NOR, NAND, MMC or SPI-EEPROM. If a valid booting image is found and successfully read from the external memory device, the code be-gins to execute.

> The peripheral booting is executed when the booting device type is Ethernet, USB or UART. The Data is downloaded from a host to the device by Ethernet, USB or UART links. This booting method is mostly used for program-ming flash memories connected to the device (for example, in the case of initial flashing, or for firmware updates or servicing). Follow LINK for details concerning this booting pro-cedure: AM437x Technical Reference Manual, Section 5.2.7.2 (Page 229)

LINK: AM437x Technical Reference Manual

http://www.ti.com/lit/ds/symlink/tps65910.pdf

http://www.ti.com/lit/ug/spruhl7h/spruhl7h.pdf





4.6.2 byteENGINE AM437x Boot Modes

The default Boot Mode setting of the byteENGINE AM437x is:

> SYSBOOT[4:0] 00010b (SPI / USB1 / MMC0 / USB0)


NOTICEWhen choosing a user defined boot mode, bytes at work AG advices a stronger pull resistor for the user board.

4.6.3 byteENGINE AM437x Default Boot Mode

The ROM Code creates the device list based on information gathered from the SYSBOOT configuration pins sensed in the control module. The pins are used to index the device table from which the list of devices is extracted. „Table 5-10“ (Follow LINK: „Chapter 5.10 SYSBOOT Configuration Pins, Page 186“.) contains the SYSBOOT configuration pins, which correspond to LCD_DATA[0:15].


NOTICEBe careful, when integrating the SYSBOOT configuration pins to your system. Pulling those Pins high or low with your circuit can result in changed Bootmode. A changed Bootmode will select the wrong Boot Media. This leads to a boot failure.

Experience showed that some LCDs, also operated in reset state, can drive those Pins to an undefined Level. This leads to a boot failure.

To avoid the change of the Bootmode, bytes at work AG highly recommends the use of a buffer with an enable pin for the SYSBOOT configuration pins.






5. Ordering Info

> Prepared Pinmux file for byteENGINE M3

> Texas Instruments Pinmux tool: https://dev.ti.com/pinmux/app.html

> Detailed pinout for byteENGINE M3

> Datasheet Connectors Neltron 2001S-100G-270-020

> Schematic of the connectors X1, X2 and X3

> meta-bytesatwork on github

> Texas Instruments Sitara™ AM437x Processors

> AM437x Processors Data Sheet

> AM437x Technical Reference Manual

> TPS65910x Integrated Power-Management Unit

LINKS:

Chapter: 3.10, 4.3.1

Chapter: 3.10

Chapter: 4.1, 4.2, 4.3

Chapter: 3.8

Chapter: 3.7

Chapter: 3.2

Chapter: 3.4

Chapter: 3.4

Chapter: 4.6.1, 4.6.2, 4.6.3

Chapter: 4.5

6. References

[SOM]-AM437[x]_[SPEED]_R[xxx MB]_[E GB]_[C, I][SOM]: SOM type bE: byteENGINE

AM437[x]: CPU type 2: AM4372, 6: AM4376, 7: AM4377, 8: AM4378, 9: AM4379

[SPEED MHz]: Clock speed 300, 600, 800, 1000

R[xxx MB]: RAM size 256, 512, 1024 MB

[E GB]: FLASH type/size eMMC: 8, 16, 32, 64 GB

[C, I]: Temperature range [C] Customer 0° to +70° Celsius, [I] Industrial -40° to +85° Celsius

The Ordering Code allows the customer to recognize easily the detailed specification of the ordered SOM. Please refer to chapter „3.4 Overview of AM437x Processors“ auf Seite 7 for possible CPU type and clock speed combinations.




https://download.bytesatwork.io/documentation/byteENGINE/ressources/Neltron_2000P.pdf

https://download.bytesatwork.io/documentation/byteENGINE/ressources/m3-connector.pdf


http://www.ti.com/processors/sitara-arm/am4x-cortex-a9/overview.html



http://www.ti.com/lit/ds/symlink/tps65910.pdf

Johannes Böhm�


Datasheet industrial computing module byteENGINE AM437xDatasheet industrial computing module byteENGINE AM437x

> bytes at work AG Technoparkstrasse 7 CH-8406 Winterthur Switzerland

> Phone: +41 52 213 79 79 Fax: +41 52 203 27 13

> eMail: [email protected]

> Product Information: www.bytesatwork.io

> Help: www.bytesatwork.io/support

7. Contact information

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