ARM architecture 1

ARM architecture

Logo

ARM

Designer ARM Holdings

Bits 32-bit & 64-bit implementations

Introduced 1983

Version ARMv8[1]

Design RISC

Type Register-Register

Encoding Fixed

Branching Condition code

Endianness Bi (Little as default)

Extensions NEON, Thumb, Jazelle, VFP, A64

Registers

16/31[1]

ARM is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings.It was named the Advanced RISC Machine and, before that, the Acorn RISC Machine. The ARM architecture is themost widely used 32-bit instruction set architecture in numbers produced.[2][3] Originally conceived by AcornComputers for use in its personal computers, the first ARM-based products were the co-processor modules for theBBC Micro series of computers.

ARM architecture 2

Features and applicationsRISC processors (like ARM) have lower power consumption than complex instruction set computer (CISC)processors (like x86), which leads to RISC-based devices having greater battery life (or smaller battery size) andrequiring less cooling. Thus, RISC-based devices can be smaller and weigh less[4].In 2005 about 98% of the more than one billion mobile phones sold each year used at least one ARM processor.[5]

As of 2009 ARM processors accounted for approximately 90% of all embedded 32-bit RISC processors[6] and wereused extensively in consumer electronics, including personal digital assistants (PDAs), tablets, mobile phones, digitalmedia and music players, hand-held game consoles, calculators and computer peripherals such as hard drives androuters.

LicenseesThe ARM architecture is licensable. Companies that are current or former ARM licensees include Advanced MicroDevices, Inc.[7], Alcatel-Lucent, Apple Inc., AppliedMicro, Atmel, Broadcom, Cirrus Logic, CSR_plc, DigitalEquipment Corporation, Ember, Energy Micro, Freescale, Intel (through DEC), LG, Marvell Technology Group,Microsemi, Microsoft, NEC, Nintendo, Nuvoton, Nvidia, Sony, NXP (formerly Philips Semiconductor), Oki, ONSemiconductor, Psion, Qualcomm, Renesas, Samsung, Sharp, Silicon Labs, STMicroelectronics, Symbios Logic,Texas Instruments, VLSI Technology, Yamaha, Fuzhou Rockchip, and ZiiLABS.In addition to the abstract architecture, ARM offers several microprocessor core designs, including the ARM7,ARM9, ARM11, Cortex-A8, Cortex-A9, and Cortex-A15. Companies often license these designs from ARM tomanufacture and integrate into their own system on a chip (SoC) with other components like RAM, GPUs, or radiobasebands (for mobile phones).System-on-chip packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR_plc'sQuatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAPproducts, Samsung's Hummingbird and Exynos products, Apple's A4, A5, and A5X chips, and Freescale's i.MX.Companies can also obtain an ARM architectural license for designing their own, different CPU cores using theARM instruction set. Distinct ARM architecture implementations by licensees include AppliedMicro's X-Gene,Qualcomm's Snapdragon and Krait, DEC's StrongARM, Marvell (formerly Intel) XScale, and Nvidia's plannedProject Denver.

HistoryAfter achieving success with the BBC Micro computer, Acorn Computers Ltd considered how to move on from therelatively simple MOS Technology 6502 processor to address business markets like the one that would soon bedominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan required a number ofsecond processors to be made to work with the BBC Micro platform, but processors such as the Motorola 68000 andNational Semiconductor 32016 were unsuitable, and the 6502 was not powerful enough for a graphics based userinterface.Acorn would need a new architecture, having tested all of the available processors and found them wanting. Acornthen seriously considered designing its own processor, and their engineers came across papers on the Berkeley RISCproject. They felt it showed that if a class of graduate students could create a competitive 32-bit processor, thenAcorn would have no problem. A trip to the Western Design Center in Phoenix, where the 6502 was being updatedby what was effectively a single-person company, showed Acorn engineers Steve Furber[8] and Sophie Wilson thatthey did not need massive resources and state-of-the-art R&D facilities.Wilson set about developing the instruction set, writing a simulation of the processor in BBC Basic that ran on a BBC Micro with a second 6502 processor. It convinced the Acorn engineers that they were on the right track. Before they could go any further, however, they would need more resources. It was time for Wilson to approach Acorn's

ARM architecture 3

CEO, Hermann Hauser, and explain what was afoot. Once the go-ahead had been given, a small team was puttogether to implement Wilson's model in hardware.

A Conexant ARM processor used mainly inrouters

Acorn RISC Machine: ARM2

The official Acorn RISC Machine project started in October 1983.VLSI Technology, Inc was chosen as silicon partner, since it alreadysupplied Acorn with ROMs and some custom chips. The design wasled by Wilson and Furber, and was consciously designed with a similarefficiency ethos as the 6502.[9] It had a key design goal of achievinglow-latency input/output (interrupt) handling like the 6502. The 6502'smemory access architecture had allowed developers to produce fastmachines without the use of costly direct memory access hardware.VLSI produced the first ARM silicon on 26 April 1985 – it worked thefirst time and came to be termed ARM1 by April 1985.[10] The first "real" production systems named ARM2 wereavailable the following year.

The ARM1 second processor for the BBC Micro

Its first practical application was as a second processor to the BBCMicro, where it was used to develop the simulation software to finishwork on the support chips (VIDC, IOC, MEMC) and to speed up theoperation of the CAD software used in developing ARM2. Wilsonsubsequently rewrote BBC Basic in ARM assembly language, and thein-depth knowledge obtained from designing the instruction setallowed the code to be very dense, making ARM BBC Basic anextremely good test for any ARM emulator. The original aim of aprincipally ARM-based computer was achieved in 1987 with therelease of the Acorn Archimedes.

In 1992 Acorn once more won the Queen's Award for Technology for the ARM.The ARM2 featured a 32-bit data bus, a 26-bit address space and twenty-seven 32-bit registers. Program code had tolie within the first 64 Mbyte of the memory, as the program counter was limited to 24 bits because the top 6 andbottom 2 bits of the 32-bit register served as status flags. The ARM2 had a transistor count of just 30,000, comparedto Motorola's six-year older 68000 model with 68,000. Much of this simplicity comes from not having microcode(which represents about one-quarter to one-third of the 68000) and, like most CPUs of the day, not including anycache. This simplicity led to its low power usage, while performing better than the Intel 80286.[11] A successor,ARM3, was produced with a 4 KB cache, which further improved performance.

Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScaleIn the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of the ARMcore. The work was so important that Acorn spun off the design team in 1990 into a new company called AdvancedRISC Machines Ltd. Advanced RISC Machines became ARM Ltd when its parent company, ARM Holdings plc,floated on the London Stock Exchange and NASDAQ in 1998.[12]

The new Apple-ARM work would eventually turn into the ARM6, first released in early 1992. Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM 610 as the main central processing unit (CPU) in their Risc PC computers. DEC licensed the ARM6 architecture and produced the StrongARM. At 233 MHz this CPU drew only one watt (more recent versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their ageing i960 line with the StrongARM. Intel later developed its own high performance implementation named XScale which it has

ARM architecture 4

since sold to Marvell.

LicensingThe ARM core has remained largely the same size throughout these changes. ARM2 had 30,000 transistors, whilethe ARM6 grew only to 35,000. ARM's business has always been to sell IP cores, which licensees use to createmicrocontrollers and CPUs based on this core. The original design manufacturer combines the ARM core with anumber of optional parts to produce a complete CPU, one that can be built on old semiconductor fabs and stilldeliver substantial performance at a low cost. The most successful implementation has been the ARM7TDMI withhundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system.ARM licensed about 1.6 billion cores in 2005. In 2005, about 1 billion ARM cores went into mobile phones.[13] ByJanuary 2008, over 10 billion ARM cores had been built, and in 2008 iSuppli predicted that by 2011, 5 billion ARMcores will be shipping per year.[14] As of January 2011, ARM stated that over 15 billion ARM processors haveshipped.[15]

The ARM architectures used in smartphones, personal digital assistants and other mobile devices range fromARMv5, in obsolete/low-end devices, to the ARM M-series, in current high-end devices. ARMv6 processorsrepresented a step up in performance from standard ARMv5 cores, and are used in some cases, but Cortex processors(ARMv7) now provide faster and more power-efficient options than all those prior generations. ARMv7 alsomandates a hardware floating point unit, which has ABI and performance impact.In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition withnetbooks based on Intel Atom.[16] According to analyst firm IHS iSuppli, by 2015, ARM ICs are estimated to be in23% of all laptops.[17]

In 2011, HiSilicon Technologies Co. Ltd. licensed a variety of ARM technology to be used in communications chipdesigns. These included 3G/4G basestations, networking infrastructure and mobile computing applications.[18]

ARM cores

Architecture Family

ARMv1 ARM1

ARMv2 ARM2, ARM3

ARMv3 ARM6, ARM7

ARMv4 StrongARM, ARM7TDMI, ARM9TDMI

ARMv5 ARM7EJ, ARM9E, ARM10E, XScale

ARMv6 ARM11, ARM Cortex-M

ARMv7 ARM Cortex-A, ARM Cortex-M, ARM Cortex-R

ARMv8 No cores available yet. Will support 64-bit data and addressing[19][20]

A summary of the numerous vendors who implement ARM cores in their design is provided by ARM.[21]

ARM architecture 5

Example applications of ARM coresARM cores are used in a number of products, particularly various PDAs and smartphones. Some computingexamples are the Acorn Archimedes, Apple iPad and ASUS Eee Pad Transformer. Some other uses are the AppleiPhone smartphone, iPod portable media player, Canon PowerShot A470 digital camera, Nintendo DS handheldgames console and TomTom automotive navigation system.Since 2005, ARM was also involved in Manchester University's computer, SpiNNaker, which used ARM cores tosimulate the human brain.[22]

An ARM chip is also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoard,... Single-board computers,because it is very small, very cheap and runs at a low temperature.

ArchitectureFrom 1995, the ARM Architecture Reference Manual [23] has been the primary source of documentation on the ARMprocessor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support(such as instruction semantics) from implementation details that may vary. The architecture has evolved over time,and starting with the Cortex series of cores, three "profiles" are defined:•• "Application" profile: Cortex-A series•• "Real-time" profile: Cortex-R series• "Microcontroller" profile: Cortex-M series.Profiles are allowed to subset the architecture. For example, the ARMv6-M profile (used by the Cortex-M0) is asubset of the ARMv7-M profile (it supports fewer instructions).

CPU modesThe ARM architecture specifies the following CPU modes. At any moment in time, the CPU can be in only onemode, but it can switch modes due to external events (interrupts) or programmatically.User mode

The only non-privileged mode.System mode

The only privileged mode that is not entered by an exception. It can only be entered by executing aninstruction that explicitly writes to the mode bits of the CPSR.

Supervisor (svc) modeA privileged mode entered whenever the CPU is reset or when a SWI instruction is executed.

Abort modeA privileged mode that is entered whenever a prefetch abort or data abort exception occurs.

Undefined modeA privileged mode that is entered whenever an undefined instruction exception occurs.

Interrupt modeA privileged mode that is entered whenever the processor accepts an IRQ interrupt.

Fast Interrupt modeA privileged mode that is entered whenever the processor accepts an FIQ interrupt.

Hyp modeA hypervisor mode introduced in armv-7a for cortex-A15 processor for providing hardware virtualizationsupport.

ARM architecture 6

Instruction setTo keep the design clean, simple and fast, the original ARM implementation was hardwired without microcode, likethe much simpler 8-bit 6502 processor used in prior Acorn microcomputers.The ARM architecture includes the following RISC features:•• Load/store architecture.•• No support for misaligned memory accesses (although now supported in ARMv6 cores, with some exceptions

related to load/store multiple word instructions).• Uniform 16 × 32-bit register file.• Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the

Thumb instruction set increased code density.•• Mostly single clock-cycle execution.To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola68020, some additional design features were used:• Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch

predictor.• Arithmetic instructions alter condition codes only when desired.• 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address

calculations.• Powerful indexed addressing modes.• A link register for fast leaf function calls.• Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.

Arithmetic instructions

The ARM supports add, subtract, and multiply instructions. The only ARM cores to include integer divideinstructions are those implementing the ARMv7-M and ARMv7-R architectures, such as the Cortex-M3 and M4.[24]

Registers

Registers R0-R7 are the same across all CPU modes; they are never banked.R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can beentered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and thereturn address from function calls, respectively.

Registers across CPU modes

usr sys svc abt und irq fiq

R0

R1

R2

R3

R4

R5

R6

R7

R8 R8_fiq

ARM architecture 7

R9 R9_fiq

R10 R10_fiq

R11 R11_fiq

R12 R12_fiq

R13 R13_svc R13_abt R13_und R13_irq R13_fiq

R14 R14_svc R14_abt R14_und R14_irq R14_fiq

R15

CPSR

SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

Aliases:R13 is also referred to as SP, the Stack Pointer.R14 is also referred to as LR, the Link Register.R15 is also referred to as PC, the Program Counter.

Conditional execution

The conditional execution feature (called predication) is implemented with a 4-bit condition code selector (thepredicate) on every instruction; one of the four-bit codes is reserved as an "escape code" to specify certainunconditional instructions, but nearly all common instructions are conditional. Most CPU architectures only havecondition codes on branch instructions.This cuts down significantly on the encoding bits available for displacements in memory access instructions, but onthe other hand it avoids branch instructions when generating code for small if statements. The standard example ofthis is the subtraction-based Euclidean algorithm: ARM address modeIn the C programming language, the loop is:

while(i != j) {

if (i > j)

i -= j;

else

j -= i;

}

In ARM assembly, the loop is:

loop CMP Ri, Rj ; set condition "NE" if (i != j),

; "GT" if (i > j),

; or "LT" if (i < j)

SUBGT Ri, Ri, Rj ; if "GT" (greater than), i = i-j;

SUBLT Rj, Rj, Ri ; if "LT" (less than), j = j-i;

BNE loop ; if "NE" (not equal), then loop

which avoids the branches around the then and else clauses. Note that if Ri and Rj are equal then neither ofthe SUB instructions will be executed, optimising out the need for a conditional branch to implement the whilecheck at the top of the loop, for example had SUBLE (less than or equal) been used.One of the ways that Thumb code provides a more dense encoding is to remove that four bit selector fromnon-branch instructions.

ARM architecture 8

Other features

Another feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic,logical, and register-register move) instructions, so that, for example, the C statement

a += (j << 2);

could be rendered as a single-word, single-cycle instruction on the ARM.

ADD Ra, Ra, Rj, LSL #2

This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipelineis used more efficiently.The ARM processor also has some features rarely seen in other RISC architectures, such as PC-relative addressing(indeed, on the 32-bit[1] ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes.Another item of note is that the instruction set increased over time. Some early ARM processors (beforeARM7TDMI), for example, have no instruction to store a two-byte quantity.

Pipelines and other implementation issues

The ARM7 and earlier implementations have a three stage pipeline; the stages being fetch, decode, and execute.Higher performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additionalimplementation changes for higher performance include a faster adder, and more extensive branch prediction logic.The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier (hence theadded "M").

Coprocessors

The ARM family of processors does not support or have any instructions similar to Intel x86's CPUID. There are,however, mechanisms for addressing coprocessors in the ARM architecture.The ARM architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which canbe addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logicallyinto 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical controlfunctions like managing the caches and MMU operation (on processors that have one).In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registersinto ARM memory space or into the coprocessor space or connecting to another device (a bus) which in turn attachesto the processor. Coprocessor accesses have lower latency so some peripherals (for example an XScale interruptcontroller) are designed to be accessible in both ways (through memory and through coprocessors).In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an imageprocessing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operationsto support a specific set of HDTV transcoding primitives.

DebuggingAll modern ARM processors include hardware debugging facilities; without them, software debuggers could notperform basic operations like halting, stepping, and breakpointing of code starting from reset. These facilities arebuilt using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. InARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an"EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de-factodebug standard, although it was not architecturally guaranteed.The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints,watchpoints, and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE.

ARM architecture 9

Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access thedebug facilities is not architecturally specified, but implementations generally include JTAG support.There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7processors.

DSP enhancement instructionsTo improve the ARM architecture for digital signal processing and multimedia applications, a few new instructionswere added to the set.[25] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures.E-variants also imply T,D,M and I.The new instructions are common in digital signal processor architectures. They are variations on signedmultiply–accumulate, saturated add and subtract, and count leading zeros.

JazelleJazelle is a technique that allows Java Bytecode to be executed directly in the ARM architecture as a third executionstate (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J"in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is requiredstarting in ARMv6 (except for the ARMv7-M profile), although newer cores only include a trivial implementationthat provides no hardware acceleration.

ThumbTo improve compiled code-density, processors since the ARM7TDMI (released in 1994[26]) have featured Thumbinstruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, theprocessor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set.[27]

Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes frommaking some of the instruction operands implicit and limiting the number of possibilities compared to the ARMinstructions executed in the ARM instruction set state.In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and manyopcodes are restricted to accessing only half of all of the CPU's general purpose registers. The shorter opcodes giveimproved code density overall, even though some operations require extra instructions. In situations where thememory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increasedperformance compared with 32-bit ARM code, as less program code may need to be loaded into the processor overthe constrained memory bandwidth.Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. In this situation, it usuallymakes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bitARM instructions, placing these wider instructions into the 32-bit bus accessible memory.The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, includingXScale, have included a Thumb instruction decoder.

ARM architecture 10

Thumb-2Thumb-2 technology made its debut in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bitinstruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing avariable-length instruction set. A stated aim for Thumb-2 is to achieve code density similar to Thumb withperformance similar to the ARM instruction set on 32-bit memory. In ARMv7 this goal can be said to have beenmet.Thumb-2 extends both the ARM and Thumb instruction set with yet more instructions, including bit-fieldmanipulation, table branches, and conditional execution. A new "Unified Assembly Language" (UAL) supportsgeneration of either Thumb-2 or ARM instructions from the same source code; versions of Thumb seen on ARMv7processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires abit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to executebased on a tested condition. When compiling into ARM code this is ignored, but when compiling into Thumb-2 itgenerates an actual instruction. For example:

; if (r0 == r1)

CMP r0, r1

ITE EQ ; ARM: no code ... Thumb: IT instruction

; then r0 = r2;

MOVEQ r0, r2 ; ARM: conditional; Thumb: condition via ITE 'T' (then)

; else r0 = r3;

MOVNE r0, r3 ; ARM: conditional; Thumb: condition via ITE 'E' (else)

; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE"

All ARMv7 chips support the Thumb-2 instruction set. Other chips in the Cortex and ARM11 series support both"ARM instruction set state" and "Thumb-2 instruction set state".[28][29][30]

Thumb Execution Environment (ThumbEE)ThumbEE, also termed Thumb-2EE, and marketed as Jazelle RCT [31] (Runtime Compilation Target), wasannounced in 2005, first appearing in the Cortex-A8 processor. ThumbEE is a fourth processor mode, making smallchanges to the Thumb-2 extended Thumb instruction set. These changes make the instruction set particularly suitedto code generated at runtime (e.g. by JIT compilation) in managed Execution Environments. ThumbEE is a target forlanguages such as Limbo, Java, C#, Perl and Python, and allows JIT compilers to output smaller compiled codewithout impacting performance.New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, aninstruction to perform an array bounds check, access to registers r8-r15 (where the Jazelle/DBX Java VM state isheld), and special instructions that call a handler.[32] Handlers are small sections of frequently called code,commonly used to implement a feature of a high level language, such as allocating memory for a new object. Thesechanges come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE mode.

Floating-point (VFP)VFP (Vector Floating Point) technology is an FPU coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true single instruction, multiple data (SIMD) vector

ARM architecture 11

parallelism. This vector mode was therefore removed shortly after its introduction,[33] to be replaced with the muchmore powerful NEON Advanced SIMD unit.Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module instead of a full VFP module, andrequire roughly ten times more clock cycles per float operation.[34] Other floating-point and/or SIMD coprocessorsfound in ARM-based processors include FPA, FPE, iwMMXt. They provide some of the same functionality as VFPbut are not opcode-compatible with it.

Advanced SIMD (NEON)The Advanced SIMD extension (aka NEON or "MPE" Media Processing Engine) is a combined 64- and 128-bitsingle instruction multiple data (SIMD) instruction set that provides standardised acceleration for media and signalprocessing applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9 devices.[35] NEONcan execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM adaptive multi-rate (AMR)speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files andindependent execution hardware.[36] NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit)floating-point data and operates in SIMD operations for handling audio and video processing as well as graphics andgaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware sharesthe same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support128-bit vectors but will execute with just 64 bits at a time,[34] whereas newer Cortex-A15 devices can execute 128bits at once.

Security Extensions (TrustZone)The Security Extensions, marketed as TrustZone Technology, is found in ARMv6KZ and later application profilearchitectures. It provides a low cost alternative to adding an additional dedicated security core to an SoC, byproviding two virtual processors backed by hardware based access control. This enables the application core toswitch between two states, referred to as worlds (to reduce confusion with other names for capability domains), inorder to prevent information from leaking from the more trusted world to the less trusted world. This world switch isgenerally orthogonal to all other capabilities of the processor, thus each world can operate independently of the otherwhile using the same core. Memory and peripherals are then made aware of the operating world of the core and mayuse this to provide access control to secrets and code on the device.Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, andsmaller security-specialized code in the more trusted world (named TrustZone Software, a TrustZone optimisedversion of the Trusted Foundations Software developed by Trusted Logic [37]), allowing much tighter digital rightsmanagement for controlling the use of media on ARM-based devices,[38] and preventing any unapproved use of thedevice. Open Virtualization [39] is an open source implementation of the trusted world architecture for TrustZone.In practice, since the specific implementation details of TrustZone are proprietary and have not been publiclydisclosed for review, it is unclear what level of assurance is provided for a given threat model.

No-execute page protectionAs of ARMv6, the ARM architecture supports no-execute page protection, which is referred to as XN, for eXecuteNever.[40]

ARMv8 and 64-bitReleased in late 2011, ARMv8 represents the first fundamental change to the ARM architecture. It adds a 64-bit architecture, dubbed 'AArch64', and a new 'A64' instruction set. Within the context of ARMv8, the 32-bit architecture and instruction set are referred to as 'AArch32' and 'A32', respectively. The Thumb instruction sets are referred to as 'T32' and have no 64-bit counterpart. ARMv8 allows 32-bit applications to be executed in a 64-bit OS,

ARM architecture 12

and for a 32-bit OS to be under the control of a 64-bit hypervisor.[1] As of March 2012, only the ARMv8-A("application") profile has been defined, and no implementations have been announced.To both AArch32 and AArch64, ARMv8 makes VFP and advanced SIMD (NEON) standard. It also addscryptography instructions supporting AES and SHA-1/SHA-256.AArch64 features:•• New instruction set, A64

•• 31 general-purpose 64-bit registers•• Instructions are still 32 bits long and mostly the same as A32•• Most instructions can take 32-bit or 64-bit arguments•• Addresses assumed to be 64-bit

•• A new exception system•• Fewer banked registers and modes

•• Memory translation from 48-bit virtual addresses based on the existing LPAE, which was designed to be easilyextended to 64-bit

ARM licenseesARM Ltd does not manufacture or sell CPU devices based on its own designs, but rather, licenses the processorarchitecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To alllicensees, ARM provides an integratable hardware description of the ARM core, as well as complete softwaredevelopment toolset (compiler, debugger, SDK), and the right to sell manufactured silicon containing the ARMCPU.Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested inacquiring a ready-to-manufacture verified IP core. For these customers, ARM delivers a gate netlist description ofthe chosen ARM core, along with an abstracted simulation model and test programs to aid design integration andverification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators,choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customerhas the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exoticdesign goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption,instruction set extensions, etc.). While ARM does not grant the licensee the right to resell the ARM architectureitself, licensees may freely sell manufactured product (chip devices, evaluation boards, complete systems, etc.).Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores,they generally hold the right to re-manufacture ARM cores for other customers.Like most IP vendors, ARM prices its IP based on perceived value. In architectural terms, lower performing ARMcores command lower license costs than higher performing cores. In implementation terms, a synthesizable corecosts more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry which holds an ARMlicense (such as Samsung and Fujitsu) can offer reduced licensing costs to its fab customers. In exchange foracquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminatepayment of ARM's upfront license fee. Compared to dedicated semiconductor foundries (such as TSMC and UMC)without in-house design services, Fujitsu/Samsung charge 2 to 3 times more per manufactured wafer. For low to midvolume applications, a design service foundry offers lower overall pricing (through subsidisation of the license fee).For high volume mass produced parts, the long term cost reduction achievable through lower wafer pricing reducesthe impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.Many semiconductor or IC design firms hold ARM licenses: Analog Devices, AppliedMicro, Atmel, Broadcom, Cirrus Logic, Energy Micro, Faraday Technology, Freescale, Fujitsu, Intel (through its settlement with Digital Equipment Corporation), IBM, Infineon Technologies, Marvell Technology Group, Nintendo, Nvidia,NXP

ARM architecture 13

Semiconductors, OKI, Qualcomm, Samsung, Sharp, STMicroelectronics, and Texas Instruments are some of themany companies who have licensed the ARM in one form or another.

Approximate licensing costsARM's 2006 annual report and accounts state that royalties totalling £88.7 million ($164.1 million) were the result oflicensees shipping 2.45 billion units.[41] This is equivalent to £0.036 ($0.067) per unit shipped. However, this isaveraged across all cores, including expensive new cores and inexpensive older cores.In the same year ARM's licensing revenues for processor cores were £65.2 million (US$119.5 million),[42] in a yearwhen 65 processor licenses were signed,[43] an average of £1 million ($1.84 million) per license. Again, this isaveraged across both new and old cores.Given that ARM's 2006 income from processor cores was approximately 60% from royalties and 40% from licenses,ARM makes the equivalent of £0.06 ($0.11) per unit shipped including both royalties and licenses. However, asone-off licenses are typically bought for new technologies, unit sales (and hence royalties) are dominated by moreestablished products. Hence, the figures above do not reflect the true costs of any single ARM product.

Operating systems

Android, a popular operating system running onthe ARM architecture

Acorn systems

The very first ARM-based Acorn Archimedes personal computers ranan interim operating system called Arthur, which evolved into RISCOS, used on later ARM-based systems from Acorn and other vendors.

Embedded operating systems

The ARM architecture is supported by a large number of embeddedand real-time operating systems, including Windows CE, Windows 8,.NET Micro Framework, Symbian, ChibiOS/RT, FreeRTOS, eCos,Integrity, Nucleus PLUS, MicroC/OS-II, QNX, RTEMS, CoOS,BRTOS, RTXC Quadros, ThreadX, Unison Operating System,uTasker, VxWorks, MQX and OSE.[44]

Unix-like

The ARM architecture is supported by Unix and Unix-like operatingsystems such as:

•• Android•• Bada•• FreeBSD•• iOS•• Linux•• NetBSD•• OpenBSD•• Plan 9 from Bell Labs

•• Inferno•• Solaris•• webOS

ARM architecture 14

Linux

The following Linux distributions support ARM processors:• APEXAR PDK[45]

• Android[46]

• Arch Linux Arm[47]

• Ångström[48]

• CRUX ARM[49]

•• BackTrack• Chrome OS[50]

•• DSLinux• Debian[51]

• ELinOS[52]

• Fedora[53]

• Gentoo[54]

• GoboLinux[55]

•• iPodLinux•• Maemo•• MeeGo• Mer[56]

• MontaVista[57]

• PuppyLinux[58]

• RedSleeve[59]

• Slackware[60]

• T2 SDE[61]

• TimeSys[62]

• Ubuntu[63][64]

•• webOS• Wind River Linux[65]

BSD

The following BSD derivatives support ARM processors:• RISC iX (Acorn ARM2/ARM3-based systems only)• FreeBSD[66]

• NetBSD[67]

• OpenBSD[68]

•• iOS

Solaris

• OpenSolaris[69]

WindowsMicrosoft announced on 5 January 2011 that the next major version of the Windows NT family (Windows 8) will include support for ARM processors. Microsoft demonstrated a preliminary version of Windows (version 6.2.7867) running on an ARM-based computer at the 2011 Consumer Electronics Show.[70] The ARM architecture is also supported by Microsoft's mobile operating systems, Windows Phone and Windows Mobile. ARM is also supported on Microsoft's Embedded OS, Windows Embedded CE which is now called Windows Embedded Compact. This

ARM architecture 15

latest version supports ARMv 5,6 and 7. Windows CE 5 is the underlying OS for Windows Mobile and WindowsEmbedded Compact 7 is the underlying OS for Windows Phone 7. The smaller Microsoft OS .NET Microframeworkuses ARM exclusively.In December 2011, Microsoft released a document about hardware certification of OEM products, WindowsHardware Certification Requirements which confirms that they intend to ban the possibility of installing alternativeoperating systems on ARM-based devices running Windows 8. The document insists that they will require x86 andx86-64 devices to have the Secure UEFI enabled. They allow for the possibility that a custom secure boot modecould be enabled providing to the user the ability to add signatures. However, they intend that going to customsecure boot mode or disabling secure boot mode on ARM devices will not be compatible with running Windows.

References[1] Grisenthwaite, Richard (2011). "ARMv8 Technology Preview" (http:/ / www. arm. com/ files/ downloads/ ARMv8_Architecture. pdf). .

Retrieved 31 October 2011.[2] "ARM Cores Climb Into 3G Territory" (http:/ / www. extremetech. com/ extreme/ 52180-arm-cores-climb-into-3g-territory) by Mark

Hachman, 2002.[3] "The Two Percent Solution" (http:/ / www. embedded. com/ shared/ printableArticle. jhtml?articleID=9900861) by Jim Turley 2002.[4] http:/ / www. quora. com/ iPad/ Why-would-someone-want-to-produce-an-ARM-based-tablet-over-an-x86-tablet iPad: Why would someone

want to produce an ARM based tablet over an x86 tablet?, Quora.com[5] "ARMed for the living room" (http:/ / news. cnet. com/ ARMed-for-the-living-room/ 2100-1006_3-6056729. html).[6] Fitzpatrick, J. (2011). "An interview with Steve Furber" (http:/ / cacm. acm. org/ magazines/ 2011/ 5/ 107684-an-interview-with-steve-furber/

fulltext). Communications of the ACM 54 (5): 34. doi:10.1145/1941487.1941501. .[7] "AMD Strengthens Security Solutions through Technology Partnership with ARM " (http:/ / www. amd. com/ us/ press-releases/ Pages/

amd-strengthens-security-2012jun13. aspx).[8] Furber, Stephen B. (2000). ARM system-on-chip architecture. Boston: Addison-Wesley. ISBN 0-201-67519-6.[9] Goodwins, Rupert (4 December 2010). "Intel's victims: Eight would-be giant killers" (http:/ / www. zdnet. co. uk/ news/ infrastructure/ 2010/

12/ 04/ intels-victims-eight-would-be-giant-killers-40091045/ 6/ ). ZDNet. . Retrieved 7 March 2012.[10] "Some facts about the Acorn RISC Machine" (http:/ / groups. google. com/ group/ comp. arch/ msg/ 269fe7defd51f29e) Roger Wilson

posting to comp.arch, 2 Nov 1988. Retrieved 25 May 2007.[11] Patterson, Jason. The Acorn Archimedes" (http:/ / www. pattosoft. com. au/ jason/ Articles/ HistoryOfComputers/ 1980s. html), The History

Of Computers During My Lifetime – The 1980s by (Retrieved 12 March 2008)].[12] "ARM Corporate Backgrounder" (http:/ / www. arm. com/ miscPDFs/ 3822. pdf), ARM Technology.[13] "ARMed for the living room" (http:/ / news. cnet. com/ ARMed-for-the-living-room/ 2100-1006_3-6056729. html) by Tom Krazit 2006.[14] "ARM Achieves 10 Billion Processor Milestone" (http:/ / www. arm. com/ news/ 19720. html), ARM Technology, 22 January 2008.[15] "Company Profile – ARM" (http:/ / www. arm. com/ about/ company-profile/ ), ARM Company Profile, 11 January 2011.[16] "ARM netbook ships with detachable tablet" (http:/ / www. linuxfordevices. com/ c/ a/ News/ Always-Innovating-Touch-Book/ ) by Eric

Brown 2009[17] Dylan McGrath, EE Times. " IHS: ARM ICs to be in 23% of laptops in 2015 (http:/ / eetimes. com/ electronics-news/ 4217951/

IHS--ARM-ICs-to-be-in-23--of-laptops-in-2015)." 18 July 2011. Retrieved 20 July 2011.[18] Peter Clarke, EE Times. " HiSilicon extends ARM licenses for 3G/4G (http:/ / eetimes. com/ electronics-news/ 4218416/

HiSilicon-licenses-ARM-3G-4G-communications)." 2 August 2011. Retrieved 2 August 2011.[19] "ARM Discloses Technical Details of the Next Version of the ARM Architecture" (http:/ / arm. com/ about/ newsroom/

arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture. php). 2011. . Retrieved 31 October 2011.[20] Michael J. Miller, PC Magazine. " Moving On Up: ARM's Next-Gen Cores Ascend to 64-Bit (http:/ / forwardthinking. pcmag. com/ chips/

289987-moving-on-up-arm-s-next-gen-cores-ascend-to-64-bit#fbid=aXy3o2Z2ZgE)." 1 November 2011. Retrieved 7 November 2011.[21] "Line Card" (http:/ / www. arm. com/ support/ 0141_5LineCard. pdf) (PDF). 2003. . Retrieved 6 January 2011.[22] Parrish, Kevin (14 July 2011). "One Million ARM Cores Linked to Simulate Brain" (http:/ / www. eetimes. com/ electronics-news/

4217840/ Million-ARM-cores-brain-simulator). EE Times. . Retrieved 2 August 2011.[23] http:/ / infocenter. arm. com/ help/ index. jsp[24] Lebeaupin, Pierre (19 July 2010). "A few things iOS developers ought to know about the ARM architecture" (http:/ / wanderingcoder. net/

2010/ 07/ 19/ ought-arm/ ). . Retrieved 4 April 2012.[25] "ARM DSP Instruction Set Extensions" (http:/ / www. arm. com/ products/ CPUs/ cpu-arch-DSP. html). Arm.com. Archived (http:/ / web.

archive. org/ web/ 20090414011837/ http:/ / www. arm. com/ products/ CPUs/ cpu-arch-DSP. html) from the original on 14 April 2009. .Retrieved 18 April 2009.

[26] ARM7TDMI Technical Reference Manual (http:/ / www. atmel. com/ Images/ DDI0029G_7TDMI_R3_trm. pdf) page ii[27] Jaggar, Dave (1996). ARM Architecture Reference Manual. Prentice Hall. pp. 6–1. ISBN 978-0-13-736299-8.

ARM architecture 16

[28] "ARM Processor Instruction Set Architecture" (http:/ / www. arm. com/ products/ CPUs/ architecture. html). Arm.com. Archived (http:/ /web. archive. org/ web/ 20090415171228/ http:/ / arm. com/ products/ CPUs/ architecture. html) from the original on 15 April 2009. .Retrieved 18 April 2009.

[29] "ARM aims son of Thumb at uCs, ASSPs, SoCs" (http:/ / www. linuxdevices. com/ news/ NS7814673959. html). Linuxdevices.com. .Retrieved 18 April 2009.

[30] "ARM Information Center" (http:/ / infocenter. arm. com/ help/ index. jsp?topic=/ com. arm. doc. ddi0290g/ I1005458. html).Infocenter.arm.com. . Retrieved 18 April 2009.

[31] http:/ / www. arm. com/ products/ multimedia/ java/ jazelle_architecture. html[32] "Arm strengthens Java compilers: New 16-Bit Thumb-2EE Instructions Conserve System Memory" (http:/ / www. arm. com/ miscPDFs/

10069. pdf) by Tom R. Halfhill 2005.[33] "VFP directives and vector notation" (http:/ / infocenter. arm. com/ help/ index. jsp?topic=/ com. arm. doc. dui0204j/ Chdehgeh. html).

Arm.com. . Retrieved 21 November 2011.[34] "Differences between ARM Cortex-A8 and Cortex-A9" (http:/ / www. shervinemami. info/ armAssembly. html#cortex-a9). Shervin Emami.

. Retrieved 21 November 2011.[35] "Cortex-A9 Processor" (http:/ / www. arm. com/ products/ processors/ cortex-a/ cortex-a9. php). Arm.com. . Retrieved 21 November 2011.[36] "About the Cortex-A9 NEON MPE" (http:/ / infocenter. arm. com/ help/ index. jsp?topic=/ com. arm. doc. ddi0409f/ Chdceejc. html).

Arm.com. . Retrieved 21 November 2011.[37] http:/ / www. trusted-logic. com[38] "ARM Announces Availability of Mobile Consumer DRM Software Solutions Based on ARM T" (http:/ / news. thomasnet. com/

companystory/ 476887). News.thomasnet.com. . Retrieved 18 April 2009.[39] http:/ / www. openvirtualization. org[40] "APX and XN (execute never) bits have been added in VMSAv6 [Virtual Memory System Architecture]", ARM Architecture Reference

Manual (http:/ / www. arm. com/ miscPDFs/ 14128. pdf). Retrieved 2009/12/01.[41] "Business review/Financial review/IFRS", p. 10, ARM annual report and accounts, 2006 (http:/ / media. corporate-ir. net/ media_files/ irol/

19/ 197211/ reports/ ar06. pdf). Retrieved 7 May 2007.[42] Based on total £110.6 million ($202.5 million) divided by "License revenues by product"; "Business review/Financial review/IFRS" and

"Key performance indicators" respectively, p. 10 / p. 3 ARM annual report and accounts, 2006 (http:/ / media. corporate-ir. net/ media_files/irol/ 19/ 197211/ reports/ ar06. pdf). Retrieved 7 May 2007.

[43] "Key performance indicators", p. 3, ARM annual report and accounts, 2006 (http:/ / media. corporate-ir. net/ media_files/ irol/ 19/ 197211/reports/ ar06. pdf). Retrieved 7 May 2007.

[44] "Software Enablement" (http:/ / www. arm. com/ community/ software-enablement/ index. php). arm.com. ARM Ltd.. Archived (http:/ /web. archive. org/ web/ 20101116164645/ http:/ / arm. com/ community/ software-enablement/ index. php) from the original on 16 November2010. . Retrieved 18 November 2010.

[45] "APEXAR PDK" (http:/ / www. apexar. com). . Retrieved 8 November 2011.[46] "Android Source Code" (http:/ / source. android. com/ source/ index. html). Archived (http:/ / web. archive. org/ web/ 20110707142839/

http:/ / source. android. com/ source/ index. html) from the original on 7 July 2011. . Retrieved 1 July 2011.[47] "Arch Linux Arm" (http:/ / archlinuxarm. org/ ). . Retrieved 12 November 2011.[48] http:/ / www. angstrom-distribution. org/[49] "CRUX Linux on ARM" (http:/ / crux-arm. nu/ ). . Retrieved 1 May 2011.[50] Womack, Brian (8 July 2009). "Google to Challenge Microsoft With Operating System" (http:/ / www. bloomberg. com/ apps/

news?pid=20601087& sid=aTd2k. YdQZ. Y). Bloomberg. . Retrieved 8 July 2009.[51] "Debian ARM Port" (http:/ / www. debian. org/ ports/ arm/ ). . Retrieved 1 June 2009.[52] "ELinOS supported boards" (http:/ / www. sysgo. com/ products/ board-support-packages/ elinos/ ). Archived (http:/ / web. archive. org/

web/ 20100418054654/ http:/ / www. sysgo. com/ products/ board-support-packages/ elinos/ ) from the original on 18 April 2010. . Retrieved22 April 2010.

[53] "Architectures/ARM" (http:/ / fedoraproject. org/ wiki/ Architectures/ ARM). . Retrieved 1 June 2009.[54] "Gentoo Linux ARM Development" (http:/ / www. gentoo. org/ proj/ en/ base/ arm/ index. xml). . Retrieved 1 June 2009.[55] "New release for ARM cpus" (http:/ / lists. gobolinux. org/ pipermail/ gobolinux-arm/ 2007-January/ 000019. html). 25 January 2007. .

Retrieved 17 September 2009.[56] "Mer ARM builds" (http:/ / releases. merproject. org/ releases/ 0. 20111020. 1/ builds/ ). . Retrieved 27 November 2011.[57] "Platform Support for MontaVista Linux" (http:/ / www. mvista. com/ boards. php). Archived (http:/ / web. archive. org/ web/

20100118113050/ http:/ / www. mvista. com/ boards. php?) from the original on 18 January 2010. . Retrieved 16 February 2010.[58] "PuppyLinux" (http:/ / bkhome. org/ blog/ ?viewDetailed=02808). . Retrieved 2 May 2012.[59] "RedSleeve" (http:/ / www. redsleeve. org/ ). . Retrieved 28 March 2012.[60] "Slackware Linux for ARM" (http:/ / www. armedslack. org/ ). Archived (http:/ / web. archive. org/ web/ 20090609151515/ http:/ /

armedslack. org/ ) from the original on 9 June 2009. . Retrieved 1 June 2009.[61] "T2 SDE" (http:/ / www. t2-project. org/ ). . Retrieved 12 March 2010.[62] "TimeSys" (http:/ / www. timesys. com/ ). . Retrieved 30 September 2011.

ARM architecture 17

[63] "Ubuntu on Arm" (http:/ / www. ubuntu. com/ products/ whatisubuntu/ arm). Canonical Ltd.. 2009. Archived (http:/ / web. archive. org/web/ 20090520032734/ http:/ / www. ubuntu. com/ products/ whatisubuntu/ arm) from the original on 20 May 2009. . Retrieved 15 June 2009.

[64] "ARM" (https:/ / wiki. ubuntu. com/ ARM). . Retrieved 1 June 2009.[65] "Wind River – Board Support Packages" (http:/ / windriver. com/ products/ bsp_web/ bsp_platform. html?platform=Wind+ River+ Linux+

3. 0. x). Archived (http:/ / web. archive. org/ web/ 20100205082314/ http:/ / windriver. com/ products/ bsp_web/ bsp_platform.html?platform=Wind+ River+ Linux+ 3. 0. x) from the original on 5 February 2010. . Retrieved 16 February 2010.

[66] "FreeBSD/ARM Project" (http:/ / www. freebsd. org/ platforms/ arm. html). Archived (http:/ / web. archive. org/ web/ 20090427205325/http:/ / www. freebsd. org/ platforms/ arm. html) from the original on 27 April 2009. . Retrieved 1 June 2009.

[67] "Hardware supported by NetBSD" (http:/ / www. netbsd. org/ ports/ #ports-by-cpu). Archived (http:/ / web. archive. org/ web/20090610211811/ http:/ / www. netbsd. org/ ports/ ) from the original on 10 June 2009. . Retrieved 1 June 2009.

[68] "OpenBSD/armish" (http:/ / www. openbsd. org/ armish. html). Archived (http:/ / web. archive. org/ web/ 20090609080919/ http:/ / www.openbsd. org/ armish. html) from the original on 9 June 2009. . Retrieved 1 June 2009.

[69] "OpenSolaris Project: ARM Platform Port" (http:/ / www. opensolaris. org/ os/ project/ osarm/ ). Sun Microsystems. .[70] Microsoft demonstrates early build of Windows 8 (http:/ / www. winrumors. com/ microsoft-demonstrates-early-build-of-windows-8/ )

Further reading• The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 479 pages; 2009; ISBN

978-1-85617-963-8. (Online Sample) (http:/ / books. google. com/ books?id=mb5d_xeINZEC&printsec=frontcover& dq=isbn:9781856179638)

• The Definitive Guide to the ARM Cortex-M0; 2nd Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN978-0-12-385477-3. (Online Sample) (http:/ / books. google. com/ books?id=5OZblBzjsJ0C&printsec=frontcover& dq=isbn:9780123854773)

External links• Official website (http:/ / www. arm. com), ARM Ltd.

Article Sources and Contributors 18

Article Sources and ContributorsARM architecture  Source: http://en.wikipedia.org/w/index.php?oldid=500036007  Contributors: (aeropagitica), 1exec1, 2620:0:1000:1B01:72CD:60FF:FEA9:5860, 2pac 2007, A876, Abaybas,Adam Zivner, Adamd1008, Ahunt, Akilaa, Alan Liefting, AlbanRampon, Alecv, Alexander.stohr, Alexandru Stanoi, AlexeySmirnov, Alexthepuffin, AlistairMcMillan, Alll, Alokprasad,AlphaPyro, Am088, Ambictus, Amh15, Amir.far, AmusedRepose, Anacrolix, AndrewBooker, Angrytoast, Animist, AnonMoos, Aquil Mirza, Armin76, Armux, Awesomexxkatie, AxelBoldt,Axlrosen, B Pete, BBar, Bachcell, Balazer, Balrog-kun, Beetstra, Bender235, Berelv, Berkut, Bhimaji, Bisy, Bisy77, Bjrice, Blakespot, Blow, Bobblewik, Brian R Hunter, Brianonn, Brianski,Briantist, Bryan Derksen, Brynmyrddinemrys, Bsborden, Butmine, Bwbuckley, CAkira, Cababunga, CalPaterson, Calltech, CanisRufus, Captain-n00dle, Cdshi, CesarB, Cesfahani, ChankeyPathak, Chaoszero6, Charliearcuri, Chchou7, Chebyshev, Chips700, Chjb, Chowbok, Chris Chittleborough, Chrisdew, Cjmumford, Ckielstra, Clapre, Classivertsen, Cmdrjameson, Cochonfou,ConanTheDiskFormatter, Corpsstudent20, Cpuwolf, Crazytales, Crotalus horridus, Crusadeonilliteracy, Csantifort, Ctrl alt delboot, Curriegrad2004, CyberSkull, Cybercobra, Cycotic, DHR,Da5id403, DaWaN, Damian Yerrick, Darkov, DataWraith, David Gerard, DavidBourguignon, DavidCary, Davinci56, Dayyan, Ddoomdoom, Dead Horsey, Delirium of disorder, Derek Ross,Destiny uk, Devil0150, Dfowler7437, Dfrg.msc, Dicklyon, Dimator, Direktorxxx, Djaus.20111, DmitryKo, Dmsar, DocendoDiscimus, Donnay, Doors5678, DopefishJustin, DrYak, Dratman,Drkamilz, Drpixie, Ds13, Dukeku, Duncan.Hull, Dwedit, Dysprosia, EEMIV, Eagleal, Easwarno1, Econtechie, Eeekster, Eegorr, Eggbertx, Egil, Electron9, EmanWilm, Ems2, EncMstr,Enchanter, Eneville, Enfcer, Enquire, Eraserhead1, Eridanos, Erl, Esebi95, Evice, Evil Genius, Eyreland, Faisal.akeel, Farry, Ferritecore, Flibble, Foobaz, Fourdee, Fourohfour, Frankie1969,Frap, Freewol, Frencheigh, Fresheneesz, Furrykef, Gabriel vincent, Galadh, Galoubet, Gasheadsteve, Gaul, Gegtik, Georgekk, GerbilSoft, Gerweck, Gf uip, Gh5046, Ghiraddje, Giftlite, Glenn,Gogo Dodo, Gonzad26, Gordan.bobic, Grahamwest, GregorB, Gri6507, Griffinofwales, Grossenhayn, Ground Zero, Gu1dry, Guy Harris, Hairy Dude, Haseo9999, He's a very naughty boy,HellDragon, HenkeB, Henriok, Holizz, HumphreyW, Ian201, IanOsgood, Ignorance is strength, Ijain, Imroy, Insertesla, Intersofia, Intgr, Islepchenkov, Ixfd64, JCDenton2052, JHunterJ,JLaTondre, Jack007, Jakew, Jakohn, Jantangring, Jason C.K., Jboonen, Jcarroll, Jencastelino, JerryJerry, Jerryobject, Jfmantis, Jgp, Jim10701, Jimmi Hugh, Johnnaylor, JonHarder, Jona, Jondel,Jonpatterns, Jose Icaza, Josemi, Joseph Egan, Jvatjusanttila, Jwarnier, KKong, Kaulike, Keksa, Kesla, Kevin B12, Kgaughan, Khalid hassani, Kinema, Komap, Komet, KonstZX, Koorogi,Kotepho, Kozuch, Kryvor, Kunkunuzzi, Kvprav, Lacp69, Lakshmin, Laudaka, Lbt, Leandrod, LeedsKing, Letdorf, Lezek, Lightmouse, Lloydd, Lmno, Lost.goblin, LouI, Lucifred, MER-C,MSTCrow, Madsy, Maghnus, Magnus.de, Mahjongg, Mailiaz, ManiacK, Mannermagmaneben, Manupap1, Marcelometal, Mark Grant, MarkMLl, Markuslaff, MarsRover, Martarius, Martin451,Martnym, Master Thief Garrett, Mathiastck, Matt Britt, Mauls, Maury Markowitz, Maximus Rex, Mazarin07, Mchliakh, Meewam, Meneth, Mercurytoxic, Mercy11, Metageek, Michael Slana,Michaeljamesmontgomery, Michalis Famelis, Mike Kao, Mike1024, Mikiemike, Mirosamek, Mirror Vax, Mithaca, Mjkaye, Mmm, Monochromec, MoonShadow, MoreNet, Mortense, Mr Beige,Mr.Do!, Mugunth Kumar, Mushroom, Mysterioususer, Mzabaluev, Narcelio, Nate Silva, Nealmcb, Neilc, Nemo20000, Nhays, Niceguyedc, Nikevich, Nixdorf, Now3d, Nposs, Nusk, Oborg,Ohconfucius, OlavN, Oleg Alexandrov, One half 3544, Oneiros, Oskilian, Ossianb, Owain, PGibbons, Panscient, Paranoidmage, Paranormal Skeptic, Peak, Peeyushagrawal, Pengkeu,Permacultura, Peter S., PeterJohnBishop, Pfagerburg, Phil Boswell, Phr, Pigpen, Pinchies, Pixel8, Pjrm, Pnm, Pol098, Polluks, Pouletic, Povlhp, Prari, Privatechef, Prolog, Ptoboley, Pttam,Qratman, Quebec99, Quibik, Quondum, RTC, RadioActive, Rajah, Randomwords2343, Raysonho, Rbhanti, Realdreamsplus, Reedy, Reilly, Rejectwater, Renegadeviking, Rhe br, Rilak,Rjwilmsi, Rkarlsba, Robert K S, Rodgling, Romanm, Runefrost, Rusmac, S4avnt, SF007, SGBailey, SHayter, Salix alba, Sarenne, Sbmeirow, SchuminWeb, Scientus, Seahcj, SeanCrossan,Secretlondon, Sfan00 IMG, Shadowriver, Shd, Shervinemami, Shirifan, Silas S. Brown, Sintau.tayua, Sladen, Slightsmile, SmackEater, Smmgeek, Smtrembl, Smyth, Sogliphy, Solipsist,Sonyack, SpuriousQ, Ssedov, Stan Shebs, Stephen, StephenHecht, Steveylin, Stewartadcock, Stmicro, StrengthOfNations, Stuarta, Sully, Supachikn, Suruena, Susanbednar, Swaaye, Sweepm,Swivelgames, Sysy, Tak'n, Tamias, Tarka, Taxman, Tazpa, Tcardone05, TechGeek70, Technopilgrim, TedPavlic, The Thing That Should Not Be, TheOtherJesse, Therumbler, ThomasHarte,Thumperward, Thunderbird2, Thv, Tigeron, Tim1357, Timbck2, Tkteun, ToastieIL, Tobias Bergemann, Toddintr, Tolstoy143, Tommy2010, Toradex, Torc2, Toussaint, Trasz, TreveX, Trevj,Tweisbach, Two9A, Uli, UmassThrower, Uzume, Vega Nexos, Verticalsearch, Vincent Lefèvre, Viridior, Viznut, Wackston, Wackymacs, Waffle, Walshga, Wangguoqin1001, WeirdBoyJim,Wereon, Wernhervonbraun, Why Not A Duck, WiJG?, Wikiborg, Wikophile, Will Beback Auto, WilliamSommerwerck, Wimvandorst, Winterspan, Wookey, WorkerBee, Wwoods, Xompanthy,Yannick56, Ybertrand, Ynhockey, Yoshm, Yungang, Yworo, ZeDestructor, Zoney, 955 anonymous edits

Image Sources, Licenses and ContributorsFile:ARM powered Badge.svg  Source: http://en.wikipedia.org/w/index.php?title=File:ARM_powered_Badge.svg  License: Public Domain  Contributors: Unbekannt (Transfered by Muffcabbage/Original uploaded by Afrank99)File:conexant arm.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Conexant_arm.jpg  License: GNU Free Documentation License  Contributors: Idrougge, Museo8bits,SuperzerocoolFile:Acorn-ARM-Evaluation-System.jpg  Source: http://en.wikipedia.org/w/index.php?title=File:Acorn-ARM-Evaluation-System.jpg  License: Creative Commons Attribution-Sharealike 3.0 Contributors: FlibbleFile:Android 4.0.png  Source: http://en.wikipedia.org/w/index.php?title=File:Android_4.0.png  License: unknown  Contributors: Android Open Source project

LicenseCreative Commons Attribution-Share Alike 3.0 Unported//creativecommons.org/licenses/by-sa/3.0/