International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064

Impact Factor (2012): 3.358

Volume 3 Issue 8, August 2014 www.ijsr.net

Licensed Under Creative Commons Attribution CC BY

Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design

Vivek Dadheech1, Ghanshyam Jangid2

1M.Tech student, Department of ECE, Gyan Vihar School of Engineering and Technology, SGVU, Jaipur, Rajasthan, India 2Assistant Professor, Department of ECE, Gyan Vihar School of Engineering and Technology, SGVU, Jaipur, Rajasthan, India

Abstract: This paper presents simultaneous use of clock gating and power gating in a sequential circuit, we have taken True Single Phase Clock (TSPC) FF. Clock gating is use to reduce the dynamic power whereas power gating technique is the best way to minimize the leakage current. If both the technique use in single circuit then we can minimize the power consumption and increase the performance of the circuit which also reduce the cost of the circuit, as also cost depends on the power consumption. Keywords: Clock gating, Power gating, TSPC FF, Sequential circuit.

1. Introduction As we know that VLSI is depend on the three major factors which is power, cost and speed. Power consumption is the vast issue in the present era and every new design is made to reduce the power. If power get reduce then the cost automatically get reduce and performance of the circuit increases. We are working on sequential circuits to minimize the power by applying clock gating and power gating technique in a single sequential circuit. Clock gating technique uses a gated clock pulse which is feed in the desire circuit. We use AND gate for gated clock signal. Instead of applying clock pulse we apply pulse to the AND gate with the enable signal, when both the inputs are “high” only then the out goes “high”. Hence the gated clock gives output high only in one condition and we can reduce the dynamic power using this technique. Power gating technique is use to reduce leakage current to some extent. In power gating we use sleep transistors, which is used to reduce the leakage current at pull down network. By applying fine-grain power gating approach, a “sleep” transistor is added to each and every cell, although the power of each cluster of cells is gated individually. Power gating is a modern technique that uses “sleep” transistors as high Vt devices to disconnect low Vt logic cells from the supply or ground to reduce the leakage in the sleep mode. In this paper we will discuss two sections, first we will discuss about the previous work clock gating and power gating technique in section 2, and then we will discuss the proposed work under section 3 in which we will use both the technique in a sequential TSPC FF. 2. Previous Work In previous work [1][2] we can notice that clock gating and power gating used in a single circuit, drawbacks and limitation of combining both the technique has been discussed, clock gating gives solution of circuit testability, formal verification and time closure. In power gating sleep transistor driven by the same sleep signal. This technique is best on large circuits, sleep transistors can control

clusters presents in gates. The three major problem clustering, size of ST and design of circuitry has been resolved to integrate both CG and PG in a single circuit.

Figure 1: Integration of CG and PG

Combining CG and PG [1] is convenient when the energy necessary to reactivate the circuit is smaller than the leakage energy consumed by the circuit in the idle state. CG is done via open database. Pulse applies directly to the design and also checks the simulation of the design with CG. This is the total technique which needed to setup the design and then if above steps would be done successfully then only add sleep transistor which is PG process. Low power design using CMOS based on T-SPICE simulator [3] in which enumerates low power. MTCMOS has been proposed which is based on DFF. As we discussed in the first paper that an extra NMOS is add in the TSPC FF which changes its functionality to low power design. As we are aware that in electronics devices Flip-Flops are the best source to stores the logical state of one or more than one data input signal. During the rise and fall signal data stored in a set of Flip-Flop present currently due to which we can feed it as an input to the other sequential circuit. Double edge triggered Flip Flops stores the data on both the edges. 3. Proposed Work 3.1) Sequential TSPC FF Low power design TSPC FF is modify version of D FF, the circuit consists of dual TSPC FF, we can say it is a sequential TSPC FF in which the output of first is the input of the second stage. Our aim is to reduce the power

Paper ID: 02015493 757

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