improving programming support for hardware accelerators...
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Improving Programming Support for Hardware Accelerators Through Automata Processing AbstractionsPhD Dissertation Proposal
Kevin [email protected]
18. December 2018
“ ”By 2020, it’s estimated that for every person on earth, 1.7MB of data will be created every second.
DOMO, “Data Never Sleeps 6.0”. 2018
18. December 2018 K. Angstadt – PhD Proposal 2
D E C E M B E R 2 0 1 5 15
The limits of existing semiconduc-tor microelectronic technology at the device level and their impact at the system level demand a successor tech-nology to the currently ubiquitous CMOS logic. There is not yet an obvious successor, but we see three basic paths to obtaining one, shown in Figure 1: create new devices, build new archi-tectures with or without new devices, and develop new computational par-adigms. We expect to see substantial exploration and innovation in each of these areas. New computation models will likely depart from digital comput-ing and expand into new areas, where former technology paradigms are less suitable. New architectures and pack-aging will resourcefully arrange exist-ing building blocks, improving perfor-mance irrespective of the underlying technology. Finally, new materials and transistors will enhance performance by creating more efficient underlying logic devices.
In the near term, emphasis will likely be on developing CMOS-based devices that extend into the third, or vertical, dimension and on improving materials technology. These efforts will likely coevolve with new archi-tectural approaches that better tailor computing capability to specific prob-lems, driven principally by large eco-nomic forces associated with the $4 trillion-per-year global IT market.
In the longer term, we expect a tran-sition toward new device classes and the emergence of practical systems based on novel computing approaches. To effectively meet societal needs and expectations in a broad con-text, these new devices and comput-ing paradigms must be economically manufacturable at scale and provide an exponential improvement path. Such requirements could necessitate
a substantial technological shift ana-logous to the transition from vacuum tubes to semiconductors.
This transition will require not years, but decades, of effort, so whether the semiconductor roadmap has 10 or 20 years of remaining vital-ity, researchers must begin now to lay a strategic foundation for change.
IS IT REALLY THE END?Far from a physical law, Moore’s obser-vation is an economic theory driven by technology scaling—constantly improving the photolithography pro-cesses that shrink on-chip compo-nent size. For the past 50 years (as of 2015), multiple assaults on conven-tional technology scaling for digital electronics have challenged Moore’s observations about performance improvement. As the sidebar “Moore’s Law Resilience” describes, despite the limitations of numerous under-lying physical mechanisms, new approaches have materialized to con-tinue Moore’s scaling. One researcher famously quipped, “I predict Moore’s law will never end—that way, I will only be wrong once!”
Why then should things be differ-ent this time?
Limits of 2D lithographyIf technology scaling is indeed the underlying driver of progress, 2D sili-con photolithography is central to that progress, and there is much concern that 2D scaling of photolithography will approach fundamental limits by the end of 2020. Moreover, there is no obvious successor technology. A sili-con atom is approximately half a nano-meter (nm) in diameter in semicon-ductor material. At the current rate of improvement, photolithography sys-tems will be able to use 5-nm technol-ogy to create transistor features on the scale of handfuls of atoms by 2022 to 2024.3
This feature size corresponds to a dozen or fewer silicon atoms across critical device features, which means that the technology will be a practical limit for controlling charge in a classi-cal sense. To go further would require engineering these devices in a regime in which quantum-mechanical effects will dominate, such as tunneling elec-trons through the gate oxide, which
PETs
New architectures and packaging
Generalpurpose
CMOS
TFETs
Carbonnanotubes
andgraphene
Spintronics
New models ofcomputaion
Neuromorphic
Adabiaticreversible
Dataflow
Approximatecomputing
Systemson chip NTV
3D stacking,adv. packaging
Superconducting
Reconfigurablecomputing
y
x
z
QuantumAnalog
New
dev
ices
and
mat
eria
ls
Darksilicon
FIGURE 1. Technology scaling options along three dimensions. The graph’s origin rep-resents current general-purpose CMOS technology, from which scaling must continue. All the dimensions, which are not mutually exclusive, aim to squeeze out more computing performance. PETs: piezo-electric transistors; TFETs: tunneling field-effect transistors; NTV: near-threshold voltage.
J. M. Shalf and R. Leland, “Computing Beyond Moore’s Law”. IEEE Computer, 2015.
Physical Limits Spark Creativity
Source: Dazeinfo
Source: MIT Technology Review
Hardware accelerators are seen as a viable path forward
for tackling increasing compute demands.
18. December 2018 K. Angstadt – PhD Proposal 3
A. Shimoni, “A gentle introduction to hardware accelerated data processing”. Medium, 2018
How Accelerators Help
18. December 2018 K. Angstadt – PhD Proposal 4
General Purpose Highly Specialized
CPU GPU AP TPU
Co-Processors FPGA
Adapted from: J. Poort, “Cloud 3.0: The Rise of Big Compute”. Rescale, 2017.
Significant Interest from Industry
18. December 2018 K. Angstadt – PhD Proposal 5
General Purpose Highly Specialized
CPU GPU AP TPU
Co-Processors FPGA
Adapted from: J. Poort, “Cloud 3.0: The Rise of Big Compute”. Rescale, 2017.
Significant Interest from Industry
18. December 2018 K. Angstadt – PhD Proposal 6
• Akin to “assembly-level” programming on CPU architectures• Are circuit design and digital logic concepts in CS curricula?
• Require low-level knowledge of architectural design to produce performant code• Difficult to debug and maintain: oscilloscopes and logic
analyzers• Many efforts to improve• OpenCL, Xilinx SDAccel, etc.• High-level language + annotations + decent performance• Non-intuitive impact of high-level implementation on
performance
Lack of [Good] Programming Models
18. December 2018 K. Angstadt – PhD Proposal 7
• Performance and Scalability: minimize overhead introduced by high-level programming models and tools. • Ease of Use: provide familiar abstractions and a shallow learning
curve. • Expressive Power: support the applications that developers wish to
accelerate with dedicated hardware. • Legacy Support: support the adaptation of existing software to
execute efficiently on hardware accelerators while placing a minimal burden on developers.
Successful Programming Models
18. December 2018 K. Angstadt – PhD Proposal 8
Finite automata provide a suitable abstraction for bridging the gap between high-level programming models and maintenance tools familiar to developers and the low-level representations that execute efficiently on hardware accelerators.Proposal Thesis
18. December 2018 K. Angstadt – PhD Proposal 9
Automata Processing in the Big Data World
Detecting Intrusion Attempts in Network
Packets
Learning Association Rules with an a priori
approach
Detecting incorrect POS tags in NLP
Looking for Virus Signatures in Binary
Data
Detecting Higgs Events in Particle
Collider Data
Aligning DNA Fragments to the Human Genome
18. December 2018 K. Angstadt – PhD Proposal 10
Finite Automata: 10,000ft View
G A C C A T A C G GG C T
Incoming Data
CGGCATT
ATCGAT
T
T
T
T
… …
Key
Active Searches
(Automata)= Target
Pattern⋮
Matching patterns trigger
reports
18. December 2018 K. Angstadt – PhD Proposal 11
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• Finite set of states with transitions operating over a finite alphabet• Input data processed by
repeatedly applying transition rules• Non-determinism: multiple
transitions on single input• Homogeneity: all incoming
transitions occur on the same input character
Homogeneous Finite Automata
18. December 2018 K. Angstadt – PhD Proposal
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• Finite set of states with transitions operating over a finite alphabet• Input data processed by
repeatedly applying transition rules• Non-determinism: multiple
transitions on single input• Homogeneity: all incoming
transitions occur on the same input character
Homogeneous Finite Automata
State Transition Element (STE): a state in a
homogeneous NFA
18. December 2018 K. Angstadt – PhD Proposal
c
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astart a
a
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Trad
ition
al N
FAH
omog
eneo
us N
FA13
Automata/RegEx Processing Platforms
Custom ASICExisting Architecture
Von
Neu
man
nSp
atia
l-Rec
onfig
urab
le
HyperScan
PCREBecchi, et al.
VASimCPU-Based
iNFAnt2DFAGE
GPU-Based
REAPR Micron AP
UAPHAREIBM PowerEN
PAPCache AutomatonFPGA-Based
18. December 2018 K. Angstadt – PhD Proposal 14
• Proposed Research Efforts• High-Level Programming Language: RAPID• High-Speed, Interactive Debugger for Hardware Accelerators• In-Cache Accelerator for Pushdown Automata• Adapting Legacy Code for Execution on Hardware Accelerators
• Candidate Schedule• Conclusion/Discussion
Proposal Overview
18. December 2018 K. Angstadt – PhD Proposal 15
High-Level Languages for Automata ProcessingResearch Effort 1
18. December 2018 K. Angstadt – PhD Proposal 16
Goal: establish the feasibility of compiling an imperative, high-level programming language to a set of finite automata for execution on hardware accelerators
Hypothesis: A high-level programming language will improve the conciseness of representing an algorithm while maintaining the performance of hand-crafted applications for hardware accelerators
Research Effort 1 RE1
18. December 2018 K. Angstadt – PhD Proposal 17
RAPID at a Glance
• Provides concise, maintainable, and efficient representations for pattern-identification algorithms • Conventional, C- or Java-style language with domain-
specific parallel control structures• Excels in applications where patterns are best represented
as a combination of text and computation• Compilation strategy supports execution on AP, FPGAs,
CPUs, and GPUs
RE1
18. December 2018 K. Angstadt – PhD Proposal 18
Domain-Specific Code Abstraction
G A C C A T A C G GG C T
Incoming Data
CGGCATT
ATCGAT
T
T
T
T
… …
Key
Active Searches
(Automata)= Target
Pattern⋮
Matching patterns trigger
reports
RE1
18. December 2018 K. Angstadt – PhD Proposal 19
Domain-Specific Code Abstraction
Network Macros
RE1
18. December 2018 K. Angstadt – PhD Proposal 20
Parallel Control Structures• Concise specification of multiple, simultaneous comparisons
against a single data stream• Support common pattern search paradigms• Static and dynamic thread spawning for massive parallelism
support• Explicit support for sliding window computations
@NITBDELGMVUDBQZZDWIEFHPTG@ZBGEXDGHXSVCMKADSKFJÖKLGJADSKGOWESIOHGADHYCBG0ASDGßAEGKQEYKPREBN…
Pattern
RE1
18. December 2018 K. Angstadt – PhD Proposal 21
Multi-Architecture System Overview
RAPID Program
AP Binary
CPU Engine
GPU Output
FPGA Engine
RAPID Compiler
Micron AP Compiler
VASim
REAPR
HyperscanCompiler
iNFAnt2
Xilinx PAR
Automata
Focus of this research effort
RE1
18. December 2018 K. Angstadt – PhD Proposal 22
Code Generation
network (…) {…
}
macro qux (…) {…
}
macro foo (…) { … }
macro baz (…) { … }
macro bar (…) { … }
RAPID Program
• Recursive transformation of RAPID program
• Similar to RegEx à NFA transformation
• Adapt strategy from Staged Computation– Imperative statements: evaluate at
compile time– Declarative interaction with input:
evaluate at runtime
RE1
18. December 2018 K. Angstadt – PhD Proposal 23
• Five benchmarks from real-world applications (expressiveness)• Success: Applications can be implemented in RAPID
• Compare LOC in RAPID and hand-crafted baseline automata (scalability)• Success: RAPID size remains constant or grows sublinearly with application
instance size
• Measure required hardware resources for AP and FPGA (performance)• Success: overheads within 15% of baseline
Experimental Methodology RE1
18. December 2018 K. Angstadt – PhD Proposal 24
RAPID Lines of Code
0 500 1000 1500 2000 2500
ARM
Brill
Exact
Gappy
MOTOMATA
Handcrafted RAPID
Lines of Code
RE1
18. December 2018 K. Angstadt – PhD Proposal 25
RAPID Hardware Utilization
Automata Processor
0
200
400
600
800
1000
1200
1400
1600
ARM Brill Exact Gappy MOTOMATA
Handcrafted STEsRAPID STEs
FPGA
0
200
400
600
800
1000
1200
1400
1600
ARM Brill Exact Gappy MOTOMATA
Handcrafted LUTsRAPID LUTsHandcrafted Reg.RAPID Reg.
RE1
18. December 2018 K. Angstadt – PhD Proposal 26
• Feasibility of compiling an imperative, high-level programming language to a set of finite automata for execution on hardware accelerators• RAPID extends C- or Java-like language with domain-specific
parallel control structures and code abstraction• Preliminary results demonstrate low overheads on AP and FPGA;
reduced program size
Research Effort 1 Summary RE1
18. December 2018 K. Angstadt – PhD Proposal 27
Interactive Debugging for High-Level Languages and AcceleratorsResearch Effort 2
18. December 2018 K. Angstadt – PhD Proposal 28
Houston, we have a problem!
18. December 2018 K. Angstadt – PhD Proposal
RE2G A C C A T A C G GG C T
Incoming Data
CGGCATT
ATCGAT
T
T
T
T
… …
Bug in corner case infrequently activated by input
Unexpected output deep in data processing
CPU too slow to debug full application, but may be difficult to extract subset of input
29
Goal: Design a high-speed interactive debugger for a high-level language (RAPID) executing on a hardware accelerator
Hypothesis: The automata abstraction reduces the program state that must be monitored at the signal level on hardware accelerators while still allowing for program semantics to be lifted to higher levels of abstraction and meaningfully supporting debugging
Research Effort 2 RE2
18. December 2018 K. Angstadt – PhD Proposal 30
“A [debugger is a] program designed to help detect, locate, and correct errors in another program. It allows the developer to step through the execution of the process and its threads, monitoring memory, variables, and other elements of process and thread context.”MSDN Windows Dev Center(https://msdn.microsoft.com/en-us/library/windows/desktop/ms679306(v=vs.85).aspx)
RE2
18. December 2018 K. Angstadt – PhD Proposal 31
1. First, we must halt execution and extract current program state from the processor
2. Then, we lift the extracted state to the semantics of the source language
Multi-Step Process
Insight: repurpose existing hardware/signal monitoring
Insight: generate mapping from expressions/statements to hardware elements during compilation
RE2
18. December 2018 K. Angstadt – PhD Proposal 32
• Breakpoints annotate expressions/statements to specify locations to pause execution for inspection• Traditional notion relies on instructions stream• Mechanism does not apply directly to architectures with no instructions
(e.g., FPGAs, AP)
• Key Insight: Automata computation driven by input• Set breakpoints on input data, not instructions• Supports use case of stopping computation at abnormal behavior• Can also provide abstraction of traditional breakpoints
Where do we stop? RE2
18. December 2018 K. Angstadt – PhD Proposal 33
• Process input data up to breakpoint• State of automata is compact • O(n) in the number of states of the NFA• State vector captures relevant execution
information• Repurpose existing hardware to capture• AP: State vector cache already stores active
states• FPGA: Integrated Logic Analyzers (ILAs) and
Virtual I/O pins (VIOs) allow for probing of activation bits
Capturing StateChallenge: Space
overhead on FPGAs
ILAs can be dynamically reconfigured to probe different signals, but
support additional features, causing bloat
VIOs are tied to the same clock as the design slow
down the design
RE2
18. December 2018 K. Angstadt – PhD Proposal 34
• Modify the RAPID compiler to generate debugging tables• Approach for the RAPID compiler is similar to traditional compilation• For every line, which NFA states does it map to?• For every line, what variables are in scope and what are their values (or
which hardware resources hold their values)?• At breakpoint, apply mappings in reverse • Now have:
• Expressions currently executing• Values of in-scope variables
Lifting Hardware State to Source-Level RE2
18. December 2018 K. Angstadt – PhD Proposal 35
Putting it all togetherStandard Program Execution
Debugging Execution
Accelerator processes data
Accelerator processes data
Abnormal behavior observed
NSystem-calculated breakpoint
User-defined breakpoint
Accelerator state vector
Simulator state vector
Simulator processes
data
Mapping
RE2
18. December 2018 K. Angstadt – PhD Proposal 36
• Measure performance and scalability of FPGA-based automata debugging• ANMLZoo benchmark Suite (14 real-world applications)• Measure additional resources used and relative clock frequency• Success: fit on commercial FPGA and exceed performance of baseline CPU
engine• Measure ease of use with a human study• Participants given fault localization task• Ten RAPID programs with indicative bugs• Collect implicated lines and measure time taken to answer• Success: statistically significant improvement in accuracy or time
Experimental Methodology RE2
18. December 2018 K. Angstadt – PhD Proposal 37
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0
10
20
30
40
50
60
Brill
ClamAV
Dotstar ER
Ferm
i
Hamming
Leve
nshte
in
PowerE
N
Protom
ata RFSno
rtSPM
BlockR
ings
Cloc
k Pe
rcen
tage
Ove
rhea
d
LUT Overhead FF Overhead Power Overhead Clock Percentage
Preliminary FPGA Results RE2
18. December 2018 K. Angstadt – PhD Proposal 38
• N=61 participants (predominantly UVA students)• Our debugging tool improves a user’s fault localization accuracy for
RAPID programs in a statistically significant manner (p = 0.013) • No statistically significant impact on the time needed to localize
faults in RAPID programs• Debugging information for RAPID programs helps novices and
experts alike (there is no interaction between developer experience and the ability to interpret debugging information)
Human Study Results RE2
18. December 2018 K. Angstadt – PhD Proposal 39
• Design a high-speed interactive debugger for RAPID on hardware accelerators• Repurpose existing hardware to extract runtime state from
accelerator and bridge semantic gap with high-level language• Preliminary FPGA results demonstrate viability• High overhead remain a challenge
• Human Study results demonstrate ease of use
Research Effort 2 Summary RE2
18. December 2018 K. Angstadt – PhD Proposal 40
Expressive Power of In-Memory Automata AcceleratorsResearch Effort 3
18. December 2018 K. Angstadt – PhD Proposal 41
Automata/RegEx Processing Platforms
Custom ASICExisting Architecture
Von
Neu
man
nSp
atia
l-Rec
onfig
urab
le
HyperScan
PCREBecchi, et al.
VASimCPU-Based
iNFAnt2DFAGE
GPU-Based
REAPR Micron AP
UAPHAREIBM PowerEN
PAPCache AutomatonFPGA-Based
RE3
18. December 2018 K. Angstadt – PhD Proposal 42
Automata/RegEx Processing Platforms
Custom ASICExisting Architecture
Von
Neu
man
nSp
atia
l-Rec
onfig
urab
le
HyperScan
PCREBecchi, et al.
VASimCPU-Based
iNFAnt2DFAGE
GPU-Based
REAPR Micron AP
UAPHAREIBM PowerEN
PAPCache AutomatonFPGA-Based
Finite automata are fundamentally limited in the kinds and complexity of analyses they support
RE3
18. December 2018 K. Angstadt – PhD Proposal 43
Automata/RegEx Processing Platforms
Custom ASICExisting Architecture
Von
Neu
man
nSp
atia
l-Rec
onfig
urab
le
HyperScan
PCREBecchi, et al.
VASimCPU-Based
iNFAnt2DFAGE
GPU-Based
REAPR Micron AP
UAPHAREIBM PowerEN
PAPCache AutomatonFPGA-Based
Finite automata are fundamentally limited in the kinds and complexity of analyses they support
RE3
18. December 2018 K. Angstadt – PhD Proposal 44
Goal: Extend the expressive power of automata-based accelerators to support more common data processing tasks, including the parsing of recursively-nested structures.
Hypothesis: An in-cache accelerator architecture supporting pushdown automata computation will support a rich class of applications, and allow for improved performance over state-of-the-art baselines.
Research Effort 3 RE3
18. December 2018 K. Angstadt – PhD Proposal 45
• Accelerated in-SRAM Pushdown ENgine• Scalable processing engine that uses LLC slices to accelerate
Pushdown Automata computation• Custom five-stage datapath using SRAM lookups can process up to
one byte per cycle• Optimizing compiler supports existing grammars, packs states
efficiently, and reduces the number processing stalls
ASPEN Will Support Richer Analyses RE3
18. December 2018 K. Angstadt – PhD Proposal 46
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
⊥STACK
Pushdown Automata Refresher
Input Symbol Match
Top of Stack Match
Stack Actions
Finite State Control
Stack Mem
ory
18. December 2018 K. Angstadt – PhD Proposal 47
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
⊥STACK
Pushdown Automata Refresher
Input Symbol Match
Top of Stack Match
Stack Actions
Finite State Control
Stack Mem
ory
Deterministic Pushdown Automata (DPDA) avoidstack divergence, but still support parsing of most
common languages
RE3
18. December 2018 K. Angstadt – PhD Proposal 48
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
⊥STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 49
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
⊥STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 50
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
0⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 51
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
10⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 52
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 53
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
1010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 54
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
01010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 55
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
01010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 56
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
01010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 57
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
1010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 58
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
010⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 59
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
10⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 60
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
0⊥
STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 61
01010c01010 ✓
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push 1
1Pop 1
No Push
00
Pop 1No Push ε
⊥Pop 0
No Push
⊥STACK
Recognizing Palindromes with a Middle Character
18. December 2018 K. Angstadt – PhD Proposal 62
• ASPEN supports homogeneous DPDA• All transitions to a state occur on the same input character, top of stack
comparison, and stack operation• Similar in nature to homogeneous NFAs
• Equal expressive power as standard DPDA• State increase is quadratic in the worst case with a fixed alphabet• Allows for efficient mapping to hardware resources• Transitions decoupled from input/stack matches
Mapping DPDA Efficiently to Hardware RE3
18. December 2018 K. Angstadt – PhD Proposal 63
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push
11
Pop 1No Push
00
Pop 1No Push
ε⊥
Pop 0No Push
⊥STACK
Five Steps of DPDA Execution Per Cycle RE3
18. December 2018 K. Angstadt – PhD Proposal 64
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push
11
Pop 1No Push
00
Pop 1No Push
ε⊥
Pop 0No Push
⊥STACK
1. Input Match"
2. Stack Match3. Action Lookup4. Stack Update5. State
Transition
Five Steps of DPDA Execution Per Cycle
1"
RE3
18. December 2018 K. Angstadt – PhD Proposal 65
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push
11
Pop 1No Push
00
Pop 1No Push
ε⊥
Pop 0No Push
⊥STACK
1. Input Match"
2. Stack Match3. Action Lookup4. Stack Update5. State
Transition
Five Steps of DPDA Execution Per Cycle
1"
2
RE3
18. December 2018 K. Angstadt – PhD Proposal 66
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push
11
Pop 1No Push
00
Pop 1No Push
ε⊥
Pop 0No Push
⊥STACK
1. Input Match"
2. Stack Match3. Action Lookup4. Stack Update5. State
Transition
Five Steps of DPDA Execution Per Cycle
1"
2
3
RE3
18. December 2018 K. Angstadt – PhD Proposal 67
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push
11
Pop 1No Push
00
Pop 1No Push
ε⊥
Pop 0No Push
⊥STACK
1. Input Match"
2. Stack Match3. Action Lookup4. Stack Update5. State
Transition
Five Steps of DPDA Execution Per Cycle
1"
2
43
RE3
18. December 2018 K. Angstadt – PhD Proposal 68
01010c01010
0*
Pop 0Push ‘0’
1*
Pop 0Push ‘1’
c*
Pop 0No Push
11
Pop 1No Push
00
Pop 1No Push
ε⊥
Pop 0No Push
⊥STACK
1. Input Match"
2. Stack Match3. Action Lookup4. Stack Update5. State
Transition
Five Steps of DPDA Execution Per Cycle
1"
2
435
RE3
18. December 2018 K. Angstadt – PhD Proposal 69
• ASPEN uses 2 arrays per bank• 240 states per
bank• Full connectivity
within bank• Global switch
and stack in CBOX for large DPDA
Where is ASPEN?
CBOX
Way 20 Way 2 Way 1
ASPEN G-switch ASPEN G-stackASPEN
RE3
18. December 2018 K. Angstadt – PhD Proposal 70
RE3ASPEN Datapath — 240 States in 2 SRAM Arrays
1. Input Match!
2. Stack Match3. Action Lookup4. Stack Update5. State
Transition240b
8-bit Input
Row
Dec
oder
255
0
EN
0 255
4:1 column mux
Row D
ecoder
255
00 255
4:1 column mux
Active State Vector
256b
256b
256 x 256 6-T SRAM L-Switch
256b
SM Vector240b
IM Vector
1. Input Matching
—One
Column per State
2. Stack Matching
—One
Column per State
3. Stack Actions —One Row
per State
Push Sym. Pop #
8b 8b
TOS
Local TOS
4. Local Stack —One Row
per Entry
8b8b
TOS +1
Stack Pointer
SRAM Array0 SRAM Array1
256b
5. Reconfigurable
Transition Matrix18. December 2018 K. Angstadt – PhD Proposal 71
• Average of 65% reduction in epsilon states
Optimizations
[A-Z]*
Pop 0No Push
ε*
Pop 1Push ‘a’
… …[A-Z]
*Pop 1
Push ‘a’
… …
ε*
Pop 1No Push
ε*
Pop 1No Push
ε*
Pop 1No Push
ε*
Pop 1No Push
… …
ε*
Pop 4No Push
… …
Epsilon Merging
Multipop
Goal: Reduce the number of stalls while processing
input
RE3
18. December 2018 K. Angstadt – PhD Proposal 72
• Compile existing grammars (expressive power and legacy support)• Cool, JSON, XML, Dot, etc.• Measure hardware utilization, including optimization improvement
• Real-world application case studies (performance and scalability)• Stress different aspects of architecture• Large DPDA with Global Stack (high connectivity)• Small DPDA with Local Stacks (sparse connectivity)• Compare runtime performance to state-of-the-art baselines
• Success: Outperform state-of-the-art for indicative applications while not exceeding power thresholds for modern CPUs
Experimental Methodology RE3
18. December 2018 K. Angstadt – PhD Proposal 73
• Benchmarks: Parabix, Ximpleware, UW XML• ASPEN is 13-18x
faster (on average) than popular CPUParsers• Performance did not
vary significantly with complexity of XML• Optimizations and
tokenization hide !-stalls
Application 1: XML Parsing
0
5
10
15
20
25
Low (< 0.3) Medium (0.3-0.7) High (>0.7) Average
Spee
dup
(nor
mal
ized
to X
erce
s)
Markup Density
Xerces Expat ASPEN ASPEN-MP
RE3
18. December 2018 K. Angstadt – PhD Proposal 74
• Identify abnormal program executions by monitoring memory access patterns• Hypothesis: normal executions will exhibit consistent, similar
memory access patterns• Cache is perfect!• Transparently snoop on memory access• Automata accelerators repurpose address lines for data input
• Revisits “a sense of self” work by Forrest et al. using system calls for signatures of normal behavior
Application 2: Anomaly Intrusion Detection RE3
18. December 2018 K. Angstadt – PhD Proposal 75
• Successful approaches (syscalls) use simple automata• Build dictionary of observed behavior• Sliding window of sequences to determine normal/abnormal
MemIDS Basic Approach: Sliding Windows
A B C D E
A
B
C
D
E
AABACCBBCTraining Memory
RE3
18. December 2018 K. Angstadt – PhD Proposal 76
• Successful approaches (syscalls) use simple automata• Build dictionary of observed behavior• Sliding window of sequences to determine normal/abnormal
MemIDS Basic Approach: Sliding Windows
A B C D E
A
B
C
D
E
AABACCBBCTraining Memory
AAECDTesting Memory
RE3
18. December 2018 K. Angstadt – PhD Proposal 77
• Can we successfully detect the execution of different programs?• How many bits of address are needed for a meaningful dictionary?• What classes of abnormal behavior can we detect?• Speculative execution-based attacks• Stealthy malware• Information leaks
• What do we do with this information?• Block access• Delay access• Return bogus values
MemIDS Research Questions RE3
18. December 2018 K. Angstadt – PhD Proposal 78
• Expand expressive power of automata accelerators with new in-cache architecture for DPDA• New homogeneous DPDA variant for efficient hardware
implementation• Optimizing compiler to support existing grammars• Preliminary results demonstrate improved performance for XML
parsing• Ongoing work to leverage accelerator for intrusion detection
applications
Research Effort 3 Summary RE3
18. December 2018 K. Angstadt – PhD Proposal 79
Adapting Legacy Code for Execution on Hardware AcceleratorsResearch Effort 4
18. December 2018 K. Angstadt – PhD Proposal 80
• Legacy code typically cannot be directly compiled for accelerators • Learning a new programming model is costly and slows rate of
adoption of new accelerators• May want to “try out” new hardware with existing software• No training on new hardware• Limited time or resources to allocate
Legacy Code in the Age of Hardware Accelerators
RE4
18. December 2018 K. Angstadt – PhD Proposal 81
Goal: Reduce the burden on developers tasked with porting legacy code to execute on hardware accelerators
Hypothesis: An algorithm that learns a set of finite automata from a legacy source code kernel, using a combination of automata learning and formal methods, can correctly synthesize a functionally-equivalent kernel computation, reduce the manual annotation and refactoring efforts of human developers, and efficiently represent real-world applications.
Research Effort 4 RE4
18. December 2018 K. Angstadt – PhD Proposal 82
• Input: function kernel : string -> bool
• Assumptions:• Function decides a regular language
• Source code for function is available
• Output: finite automaton with the same behavior on “all” inputs as kernel
Problem Statement RE4
18. December 2018 K. Angstadt – PhD Proposal 83
Angluin-Style Learning (L*)
Learner
Teacher
Oracle
s?2 L
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Membership Query
Yes/No Answer
Equivalence QueryL(A)
?= L
<latexit sha1_base64="ebjV/7Vo4GlXzDWPBU4ufDSDepE=">AAADHXicbVLNjtMwEHbD37L8deHIxaJCWqSoahASXFYscOGwh0Wiuyttq2riTlKrjh3Zk4UQ5cpr8AJc4Q24Ia6IB+A9cNIcti0j2fr0zdjf/MW5ko5Goz+94MrVa9dv7NzcvXX7zt17/b37J84UVuBYGGXsWQwOldQ4JkkKz3KLkMUKT+Plm8Z/eoHWSaPfU5njNINUy0QKIE/N+vxof5IBLQSo6lX9hE8cgVhaVNXLujqo+dGsPxgNR63xbRB1YMA6O57t9f5O5kYUGWoSCpw7j0Y5TSuwJIXCendSOMy9CKR47qGGDN20akup+WPPzHlirD+aeMteflFB5lyZxT6ySdtt+hryv74EtCgvbLym36luU2F7U6w20qXkxbSSOi8ItVhlmxSKk+FNc/lcWhSkSg9AWOkL5mIBFgT5EaypNKOVOnXr2gRxocCW66oZ2FTqg0jqaZWiyZA2IiqSy08rpkFKxtZ/UkFBxjcCQrDWfHDhHIWx7dxdmEgK+SViSPiRQreAHF2YGycb1icYNh8KaUUhyYWx10utKfTc1X4xos012AYnT4eRx++eDQ5fdyuywx6yR2yfRew5O2Rv2TEbM8E+s6/sG/sefAl+BD+DX6vQoNe9ecDWLPj9D5GTCEI=</latexit><latexit sha1_base64="ebjV/7Vo4GlXzDWPBU4ufDSDepE=">AAADHXicbVLNjtMwEHbD37L8deHIxaJCWqSoahASXFYscOGwh0Wiuyttq2riTlKrjh3Zk4UQ5cpr8AJc4Q24Ia6IB+A9cNIcti0j2fr0zdjf/MW5ko5Goz+94MrVa9dv7NzcvXX7zt17/b37J84UVuBYGGXsWQwOldQ4JkkKz3KLkMUKT+Plm8Z/eoHWSaPfU5njNINUy0QKIE/N+vxof5IBLQSo6lX9hE8cgVhaVNXLujqo+dGsPxgNR63xbRB1YMA6O57t9f5O5kYUGWoSCpw7j0Y5TSuwJIXCendSOMy9CKR47qGGDN20akup+WPPzHlirD+aeMteflFB5lyZxT6ySdtt+hryv74EtCgvbLym36luU2F7U6w20qXkxbSSOi8ItVhlmxSKk+FNc/lcWhSkSg9AWOkL5mIBFgT5EaypNKOVOnXr2gRxocCW66oZ2FTqg0jqaZWiyZA2IiqSy08rpkFKxtZ/UkFBxjcCQrDWfHDhHIWx7dxdmEgK+SViSPiRQreAHF2YGycb1icYNh8KaUUhyYWx10utKfTc1X4xos012AYnT4eRx++eDQ5fdyuywx6yR2yfRew5O2Rv2TEbM8E+s6/sG/sefAl+BD+DX6vQoNe9ecDWLPj9D5GTCEI=</latexit><latexit sha1_base64="ebjV/7Vo4GlXzDWPBU4ufDSDepE=">AAADHXicbVLNjtMwEHbD37L8deHIxaJCWqSoahASXFYscOGwh0Wiuyttq2riTlKrjh3Zk4UQ5cpr8AJc4Q24Ia6IB+A9cNIcti0j2fr0zdjf/MW5ko5Goz+94MrVa9dv7NzcvXX7zt17/b37J84UVuBYGGXsWQwOldQ4JkkKz3KLkMUKT+Plm8Z/eoHWSaPfU5njNINUy0QKIE/N+vxof5IBLQSo6lX9hE8cgVhaVNXLujqo+dGsPxgNR63xbRB1YMA6O57t9f5O5kYUGWoSCpw7j0Y5TSuwJIXCendSOMy9CKR47qGGDN20akup+WPPzHlirD+aeMteflFB5lyZxT6ySdtt+hryv74EtCgvbLym36luU2F7U6w20qXkxbSSOi8ItVhlmxSKk+FNc/lcWhSkSg9AWOkL5mIBFgT5EaypNKOVOnXr2gRxocCW66oZ2FTqg0jqaZWiyZA2IiqSy08rpkFKxtZ/UkFBxjcCQrDWfHDhHIWx7dxdmEgK+SViSPiRQreAHF2YGycb1icYNh8KaUUhyYWx10utKfTc1X4xos012AYnT4eRx++eDQ5fdyuywx6yR2yfRew5O2Rv2TEbM8E+s6/sG/sefAl+BD+DX6vQoNe9ecDWLPj9D5GTCEI=</latexit><latexit sha1_base64="ebjV/7Vo4GlXzDWPBU4ufDSDepE=">AAADHXicbVLNjtMwEHbD37L8deHIxaJCWqSoahASXFYscOGwh0Wiuyttq2riTlKrjh3Zk4UQ5cpr8AJc4Q24Ia6IB+A9cNIcti0j2fr0zdjf/MW5ko5Goz+94MrVa9dv7NzcvXX7zt17/b37J84UVuBYGGXsWQwOldQ4JkkKz3KLkMUKT+Plm8Z/eoHWSaPfU5njNINUy0QKIE/N+vxof5IBLQSo6lX9hE8cgVhaVNXLujqo+dGsPxgNR63xbRB1YMA6O57t9f5O5kYUGWoSCpw7j0Y5TSuwJIXCendSOMy9CKR47qGGDN20akup+WPPzHlirD+aeMteflFB5lyZxT6ySdtt+hryv74EtCgvbLym36luU2F7U6w20qXkxbSSOi8ItVhlmxSKk+FNc/lcWhSkSg9AWOkL5mIBFgT5EaypNKOVOnXr2gRxocCW66oZ2FTqg0jqaZWiyZA2IiqSy08rpkFKxtZ/UkFBxjcCQrDWfHDhHIWx7dxdmEgK+SViSPiRQreAHF2YGycb1icYNh8KaUUhyYWx10utKfTc1X4xos012AYnT4eRx++eDQ5fdyuywx6yR2yfRew5O2Rv2TEbM8E+s6/sG/sefAl+BD+DX6vQoNe9ecDWLPj9D5GTCEI=</latexit>
Yes or CounterexampleA<latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit>
Automaton
RE4
18. December 2018 K. Angstadt – PhD Proposal 84
Angluin-Style Learning (L*)
Learner
Teacher
Oracle
s?2 L
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Membership Query
Yes/No Answer
Equivalence QueryL(A)
?= L
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Yes or CounterexampleA<latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit>
Automaton
Kernel
RE4
18. December 2018 K. Angstadt – PhD Proposal 85
Angluin-Style Learning (L*)
Learner
Teacher
Oracle
s?2 L
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Membership Query
Yes/No Answer
Equivalence QueryL(A)
?= L
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Yes or CounterexampleA<latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit><latexit sha1_base64="qHhxLuveeh3J3eTbTY+fjB1qyhU=">AAADBnicbVLNjtMwEHbD37L87cKRS0SFxCGqGrQSXJAWuHBcJLq7Uhutxs4kterYkT1ZCFHvvABXeANuiCuvwQPwHjhpDpuWkWx9+mbs7/N4eKmko+n0zyi4dv3GzVt7t/fv3L13/8HB4cNTZyorcCaMMvacg0MlNc5IksLz0iIUXOEZX71t82eXaJ00+gPVJSYF5FpmUgB5ar4ogJYCVPN6fXEwnk6mXYS7IO7BmPVxcnE4+rtIjagK1CQUODePpyUlDViSQuF6f1E5LEGsIMe5hxoKdEnTeV6HTz2ThpmxfmkKO/bqiQYK5+qC+8rWo9vOteR/cxloUV9aPtDvVXepqNuJqy27lL1MGqnLilCLjdusUiGZsO1imEqLglTtAQgr/YNDsQQLgnyvByrtH0qdu6E2Aa8U2HqoWoDNpX4VS500OZoCaauiIbn6vGFapCS3/pIGKjK+ERCBteaji1IUxnYf7KJMUhReISaEnyhySyjRRaVxsmW9wai9UEgrKkku4l4vt6bSqWsHI94eg11w+nwSe/z+aHz8ph+RPfaYPWHPWMxesGP2jp2wGRPMsK/sG/sefAl+BD+DX5vSYNSfecQGEfz+B03y/+Y=</latexit>
Automaton
Kernel
Software Model Checker
RE4
18. December 2018 K. Angstadt – PhD Proposal 86
• Explores control flow graph looking for property violations• Success finding variety of bugs (e.g., double-free, locking violations, etc.)• Used in industry for driver verification
• Properties specified as automata• Research: How do we leverage this?• Adapt L*-learned candidate automata to specifications• Verify source kernel: violations are counterexamples
• Research: identify appropriate verification strategies
Equality Checking as Software Verification RE4
18. December 2018 K. Angstadt – PhD Proposal 87
• Restrict kernel functions• Decide regular languages• Streaming access to input data• Time permitting: relax these assumptions
• Allow for approximate solutions• Measure accuracy with respect to time• Reduce impact of error with examples
• User-provided annotations• Guide software verification• Note “transitions” in kernel
Mitigating Risk: Speculative Research RE4
18. December 2018 K. Angstadt – PhD Proposal 88
• Seek benchmark suite of existing kernel functions • Is it possible for our algorithm to adapt kernels? (legacy support)• Measure time needed to learn automata and their size in
states/hardware resources (scalability)• Success: Run over the weekend and fit on commercial FPGA
• Measure accuracy of approximate solutions• Use provided test suites and augment with test input generation• Success: use of example inputs improves accuracy
Experimental Methodology RE4
18. December 2018 K. Angstadt – PhD Proposal 89
• Design algorithm to adapt legacy kernels for execution on hardware accelerators• Adopt Angluin-style learning approach• Convert equivalence queries to software verification tasks• Speculative research• Limit kernels to decide regular languages• Annotations to guide software verification• Approximate solutions and guiding example inputs
Research Effort 4 Summary RE4
18. December 2018 K. Angstadt – PhD Proposal 90
• Proposed Research Efforts• High-Level Programming Language: RAPID• High-Speed, Interactive Debugger for Hardware Accelerators• In-Cache Accelerator for Pushdown Automata• Adapting Legacy Code for Execution on Hardware Accelerators
• Candidate Schedule• Conclusion/Discussion
Proposal Overview
18. December 2018 K. Angstadt – PhD Proposal 91
2014 2015 2016 2017 2018 2019 2020
RAPID Language [ASPLOS’16]
RAPID Multi-Architecture [TPDS’18]
Debugging System [ASPLOS’19]
ASPEN [MICRO’18]
ASPEN Security Application
Automata Learning
Primary Instructor
Undergraduate Mentorship
Today Graduation
Research Period
Publication Lag
Other
Figure 4: Proposed dissertation work schedule.
research [9,10]. We will extend this collection of tools with the new artifacts we develop as part ofthe research effort.
Mentorship and Diversity. To train the next generation of researchers and engineers, we will in-volve undergraduate students in the proposed research agenda. Mentorship is a first-order desirefor this dissertation. We are particularly interested in attracting and mentoring students from gen-ders and groups typically underrepresented in computer science. Such undergraduate researchershave contributed to the preliminary results, including Matthew Casias (UVA ’19), first author on apeer-reviewed publication detailing interactive debugging for automata processing and hardwareaccelerators [24]. We have mentored an additional five undergraduate students (including two fe-males as well as students with limited computing background) on projects related to autonomousvehicle resiliency [46], the use of automata processing in kinesiology, and modeling hard disk fail-ures. For work proposed in this dissertation, we will recruit students from the University’s Un-dergraduate Research Opportunity Program (UROP) and the Girls Encoded Explore ComputerScience Research program as well as targeted invitations to students in courses we have taught.These activities are synergistic with our recent efforts to organize a speaker series highlighting thediverse research, careers, and backgrounds within the computer science discipline. We success-fully proposed and received funding—with 50% matching departmental support—through theRackham Faculty Allies Diversity Grant program.
7 Schedule
Figure 4 outlines the research timeline for the proposed dissertation. We anticipate completingthe proposed research efforts in 1.5 years, with an expected graduation in May 2020. We havecompleted the research described in Section 3.1 to develop a high-level language for automataprocessing. The results of this effort have been published in [11, 12]. We have developed a work-ing prototype and conducted an initial human study for our research on interactive debugging(Section 3.2), and a manuscript detailing our findings has been accepted for publication [24]. Forthe expressive power of in-cache automata processors (Section 3.3), we have completed design ofa prototype compiler and architecture, which has been published in [8]. We are currently con-
15
Proposed Research Schedule
18. December 2018 K. Angstadt – PhD Proposal 92
Typical Venues
Computer Architecture• MICRO (March/April)• HPCA (July/August)• ASPLOS (August)• TPDS (Journal)
PL and Software Engineering• ASE (April)• POPL (July)• ICSE (August/September)
18. December 2018 K. Angstadt – PhD Proposal 93
1. Matthew Casias, Kevin Angstadt, Tommy Tracy II, Kevin Skadron, Westley Weimer. Debugging Support for Pattern-Matching Languages and Accelerators. In Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems, Providence, Rhode Island, 2019. ACM, to appear. (21% acceptance rate)
2. Kevin Angstadt, Jack Wadden, Westley Weimer, and Kevin Skadron. Portable Programming with RAPID. In Transactions on Parallel and Distributed Systems, to appear. IEEE. (4.181 journal impact factor)
3. Kevin Angstadt, Arun Subramaniyan, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, ReetuparnaDas. ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata. In Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, Fukuoka, Japan. 2018. IEEE. (21% acceptance rate)
4. Kevin Angstadt, Jack Wadden, Vinh Dang, Ted Xie, Dan Kramp, Westley Weimer, Mircea Stan, and Kevin Skadron. MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem. In Computer Architecture Letters, vol. 17, no. 1, pp. 84-87, Jan.-June 1 2018. IEEE. (~24% acceptance rate)
5. Jack Wadden, Kevin Angstadt, and Kevin Skadron. Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing Architectures. In Proceedings of the 24th IEEE International Symposium on High-Performance Computer Architecture, Vienna, Austria, 2018. IEEE. (21% acceptance rate)
6. Kevin Angstadt, Westley Weimer, and Kevin Skadron. RAPID Programming of Pattern-Recognition Processors. In Proceedings of the 21st International Conference on Architectural Support for programming Languages and Operating Systems, Atlanta, Georgia, 2016. ACM. (22% acceptance rate)
Publications Supporting Proposed Research
18. December 2018 K. Angstadt – PhD Proposal 94
7. Kevin Angstadt and Ed Harcourt. A Virtual Machine Model for Accelerating Relational Database Joins using a General Purpose GPU. In Proceedings of the High Performance Computing Symposium, Alexandria, VA, 2015. Society for Computer Simulation International
8. Sihang Liu, Kevin Angstadt, Mike Ferdman, Samira Khan. ARMOR: Towards Restricted Approximation with a Worst-Case Guarantee. In: Proceedings of the 2018 Workshop on Approximate Computing Across the Stack, Williamsburg, VA, 2018.
9. Kate Highnam, Kevin Angstadt, Kevin Leach, Westley Weimer, Aaron Paulos, and Patrick Hurley. An Uncrewed Aerial Vehicle Attack Scenario and Trustworthy Repair Architecture. In Proceedings of the 46th International Conference on Dependable Systems and Networks, Industrial Track, Toulouse, France, 2016. IEEE.
Invited Papers and Tech Reports
10. Ke Wang, Kevin Angstadt, Chunkun Bo, Nathan Brunelle, Elaheh Sadredini, Tommy Tracy, II, Jack Wadden, Mircea Stan, and Kevin Skadron. An overview of Micron’s Automata Processor. In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Pittsburgh, PA, 2016. ACM.
11. Kevin Angstadt, Jack Wadden, Westley Weimer, and Kevin Skadron. MNRL and MNCaRT: An Open-Source, Multi-Architecture State Machine Research and Execution Ecosystem. Technical Report CS-2017-01, Department of Computer Science, University of Virginia, May 2017.
Additional Publications
18. December 2018 K. Angstadt – PhD Proposal 95
• Hardware accelerators more commonplace—need for programming models and maintenance tools• Four components to improve programming support for hardware
accelerators using automata abstractions• High-level programming language (RAPID)• High-speed, interactive debugging for RAPID on AP and FPGA• In-cache accelerator for pushdown automata (ASPEN)• Adapt legacy kernels for execution on hardware accelerators
• Evaluation w.r.t. Performance & scalability, ease of use, expressive power, and legacy support
Proposal Summary
18. December 2018 K. Angstadt – PhD Proposal 96
• Space overheads for FPGA debugging probes• Dynamic probing or decoupling clock signals or some other approach?
• Memory-based intrusion detection evaluations and applications• What classes of abnormal behavior can we detect?• What do we do with this information?
• Automata synthesis approach and evaluation• Thoughts on representing equivalence queries?• What will computer architects want to know?
• Potential interest overlap and collaboration?• Integrating with pedagogy…undergraduate mentorship?
Discussion Cache
18. December 2018 K. Angstadt – PhD Proposal 97
Bonus Slides
18. December 2018 K. Angstadt – PhD Proposal 98
Programming Support
Hardware Abstraction Layer
Micro ArchitectureLogic
TransistorsGeometry
Operating SystemLow-Level (Assembly) Lang.
High-Level Language
Architectural modifications to support applications and features
Low-level representations to bridge the gap between software and hardware
Software systems to adapt/transform/improve existing (legacy) code
Har
dwar
eSo
ftw
are New programming languages better-suited for
specific application domains/hardware
18. December 2018 K. Angstadt – PhD Proposal 99
The AP at a High LevelRo
w A
ddre
ss(In
put S
ymbo
l)
Row Access results in 49,152 match & route operations
RoutingMatrix
Automata Processor
18. December 2018 K. Angstadt – PhD Proposal 100
Executing NFA in DRAM• Columns in DRAM store STE labels (Each STE is a single column)• Reconfigurable routing matrix connects the STEs
0 1 0 0 1 1 0 0 1Input:Drives a Row
1 1 0 0 0 0 0 1 1
Active States
Columns with “1”: STEs that accept input symbol
&=
Active States for Next Clock Cycle
18. December 2018 K. Angstadt – PhD Proposal 101
Program Structure• Macro• Basic unit of computation• Sequential control flow• Boolean expressions as statements for
terminating threads of computation• Network• High-level pattern matching• Parallel control flow• Parameters to set run-time values network (…) {
…}
macro qux (…) {…
}
macro foo (…) { … }
macro baz (…) { … }
macro bar (…) { … }
RE1
18. December 2018 K. Angstadt – PhD Proposal 102
Either/Orelse Statements1 either {2 hamming_distance(s,d); // hamming distance3 ’y’ == input(); // next input is ’y’4 report; // report candidate5 } orelse {6 while(’y’ != input ()); // consume until ’y’7 }
• Perform parallel exploration of input data• Static number of parallel operations
RE1
18. December 2018 K. Angstadt – PhD Proposal 103
Some Statements
• Parallel exploration may depend on candidate patterns• Iterates over items, dynamically spawn computation
1 macro hamming_distance (String s, int d) {2 Counter cnt;3 foreach (char c : s)4 if(c != input()) cnt.count ();5 cnt <= d;6 report;7 }8 network (String [] comparisons) {9 some(String s : comparisons)
10 hamming_distance(s,5);11 }
RE1
18. December 2018 K. Angstadt – PhD Proposal 104
Whenever Statements1 whenever( ALL_INPUT == input() ) {2 foreach(char c : "rapid")3 c == input ();4 report;5 }
• Body triggered whenever guard becomes true• ALL_INPUT: any symbol in the input stream
RE1
18. December 2018 K. Angstadt – PhD Proposal 105
Parallel Control Structures
Sequential Structure Parallel Structure
if…else either…orelse
foreach some
while whenever
RE1
18. December 2018 K. Angstadt – PhD Proposal 106
Example RAPID Program
Association Rule MiningIdentify items from a database that frequently
occur together
RE1
18. December 2018 K. Angstadt – PhD Proposal 107
Example RAPID Programmacro frequent (String set, Counter cnt) {
foreach(char c : set) {
while(input() != c);
}
cnt.count();
}
network (String[] set) {
some(String s : set) {
Counter cnt;
whenever(START_OF_INPUT == input())
frequent(s,cnt);
if (cnt > 128)
report;
}
}
Spawn parallel computation for each
item set
Sliding window search calls frequent on every
input
If all symbols in item set match, increment
counter
Trigger report if threshold reached
RE1
18. December 2018 K. Angstadt – PhD Proposal 108
• Accelerator applications often target large datasets• CPUs typically too slow to debug full applications• Abnormal behavior may not manifest itself in testing inputs
• Low quality/coverage test suites• Ex. ANMLZoo (automata processing benchmark suite) contains two inputs
per application and no gold standard output! • May be difficult to extract subset of input for debugging• Low-level debugging support exists—tedious to use and abstraction mismatch
Houston, we have a problem! RE2
18. December 2018 K. Angstadt – PhD Proposal 109
Traditional Breakpoints
18. December 2018 K. Angstadt – PhD Proposal
macro helloWorld() { whenever( ALL_INPUT == input() ) { foreach(char c : "Hello") { c == input(); } input() == ' '; foreach(char c : "world") { c == input(); } report; }}
network() { helloWorld(); }
RAPID Program
RAPIDCompiler
MachineA
MachineB
Accelerator processes data with Machine B
Accelerator processes data with Machine A
Reports occur whenline is executed
Input breakpointsinserted at reports
Figure 5: Transformation of a line breakpoint to an input breakpoint. Reports generated by STEs mapped to RAPID expressionsdetermine input breakpoints.
Table 1: ANMLZoo Benchmark Overview
Benchmark Family States Ave Node Degree
Brill Regex 42,658 1.03287ClamAV Regex 49,538 1.00396Dotstar Regex 96,438 0.97396PowerEN Regex 40,513 0.97601Protamata Regex 42,009 0.99110Snort Regex 69,029 1.08831
Hamming Mesh 11,346 1.69672Levenshtein Mesh 2,784 3.26724
Entity Resolution (ER) Widget 95,136 2.28372Fermi Widget 40,783 1.41176Random Forest (RF) Widget 33,220 1.00000SPM Widget 100,500 1.70000
BlockRings Synthetic 44,352 1.00000CoreRings Synthetic 48,002 1.00000
For each benchmark, we generate an FPGA configurationusing our modified version of REAPR [55], producing Verilogincluding both VIOs (for capturing state vector) and also Wad-den et al.’s reporting architecture [47] for efficient transfer ofreports to the host system. We also use REAPR to generate abaseline configuration that does not include the VIOs.
We synthesize and place-and-route each application foran Alphadata board rev 1.0 with a Xilinx Kintex-Ultrascalexcku060-ffva1156-2-e FPGA using Vivado 2017.2 on anUbuntu 14.04.5 LTS Linux server with a 3.70GHz 4-core IntelCore i7-4820K CPU and 32GB of RAM. For both the base-line and our version supporting debugging, we measure thehardware resources required, the maximum clock frequencyand the total power utilized. We present these results next.
5.2. FPGA Results
Performance results for FPGA-based debugging are presentedin Table 2. We were able to successfully place and routethirteen of the fourteen benchmarks—the Xilinx toolchain failswith a segmentation fault for one of the synthetic benchmarks.We limit our discussion to these thirteen benchmarks.
Three benchmarks—Entity Resolution, Snort, and SPM—require two VIOs due to the number of states in the automata.Nonetheless, all but Entity Resolution and SPM—our twolargest benchmarks—fit within the hardware constraints whensynthesized with our added debugging hardware. We supportthese two benchmarks by partitioning the automata. Most ap-plications in ANMLZoo, including these two, are collectionsof many small automata or rules. By splitting the applicationsinto two pieces, we still support debugging on an FPGA, butthroughput is halved if run serially on a single FPGA. Thenumbers presented in Table 2 include this overhead.
Our additional debugging hardware has average LUT andFF overheads of 2.707⇥ and 5.925⇥, respectively. The over-heads vary significantly between applications, and we suspectthat this is due to aggressive optimization during synthesis.The area overhead of state capture is unknown in the AP (areadetails for specific structures are not provided), but since it isprovided for context switching, using it for debugging incursno extra hardware cost. For FPGAs, the area overhead of ourapproach is 2–3⇥ for LUTs (except for Hamming) and 5–10⇥for FFs. This area overhead is high. For complex programs,the compiled automata may need to be partitioned (as in EntityResolution and SPM), which is straightforward and supportedby our infrastructure. However, partitioning requires eitherrunning multiple passes over the input (end-to-end latencyincreases as extra passes are added) or using multiple FPGAs(increasing hardware costs, but as of August 2018 cloud com-puting providers offer instances with access to up to eight
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Human Study Results
• ~60 participants (students and professional developers)
• Participants shown 10 RAPID programs with seeded defects• 5 have interactive debugger• 5 have no debugging information
• Asked to identify location of bug in source code and describe
• Recorded time needed to perform each task
RE2
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• ASPEN repurposes LLC slices for pushdown automata computation• Location in LLC supports tighter coupling with CPU operations than
dedicated accelerator• PDA often part of a larger workflow• ASPEN similar to auxiliary functional unit in CPU (similar to FPU or vector
unit)
• SRAM arrays in LLC already support necessary operations for DPDA execution
Implementing ASPEN in LLC RE3
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• Check all states against top of stack• One column of SRAM/state• Input TOS as row address• “1”: match; ”0”: no match
• Intersect with currently active states
Stack Match in SRAM
4:1 column mux
Row D
ecoder
255
00 255
Top of Stack (TOS)
Active State Vector Active States Matching Stack
S0*
S1*
S3*
S2541
S2550
S253⊥
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• Check all states against top of stack• One column of SRAM/state• Input TOS as row address• “1”: match; ”0”: no match
• Intersect with currently active states
Stack Match in SRAM
4:1 column mux
Row D
ecoder
255
00 255
Top of Stack (TOS)
Active State Vector Active States Matching Stack
S0*
S1*
S3*
S2541
S2550
S253⊥
111111111
111111111
111111111
100000000
010000000
000000001
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Component Max Frequency Operating Frequency
ASPEN 880 MHz 850 MHzCache Automaton 4 GHz 3.4 GHz
Preliminary Results: XML Parsing
• Baseline Evaluation• CPU: 2.6 GHz dual-socket Intel Xeon E5-2697-v3 (28 cores total)
• Performance and Power: PAPI, Intel RAPL• ASPEN Simulation:• METIS graph partitioning framework• VASim modified for cycle-accurate DPDA simulation
RE3
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Angluin-Style Learning
• Attempts to learn a finite automaton from a held-out model
• Requires set membership queries (Is string in language? Returns yes/no answer)• Run legacy code for answer
• Requires equivalence queries (Is the automaton equivalent to model? Returns yes/counterexample)• Software model checking to
find differences
a b bbTrue True True True
a True True False Falseaa True True False Falseb True False True Trueaaa True True False Falseba False False False Falseaaaa True True True Falseab False False False Falseaaaab True False False False
C Kernel
Membership Queries
1 2
3
45
6 7
State Machine
Transform
Software Model Checker
Coun
tere
xam
ple
Generate Observation Table
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