improving op amp performance
DESCRIPTION
Improving Op Amp performance. Improving gain cascoding cascading feedback feed forward push pull complementary input decreasing current using “analog friendly” CMOS processes using bipolar. Improving speed Increasing UGF, increase transient speed - PowerPoint PPT PresentationTRANSCRIPT
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Improving Op Amp performance
• Improving gain– cascoding– cascading– feedback– feed forward– push pull– complementary input– decreasing current– using “analog friendly” CMOS processes– using bipolar
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• Improving speed– Increasing UGF, increase transient speed
• Settling may not improve, which depends on PM and secondary poles
• Cannot simply increase W/L ratio optimal sizing for a given CL
• Two stage optimal design: can potentially achieve higher UGF than single stage
– Increasing PM at UGF, reduce ringing• Once PM large enough, no effect
– Taking care of secondary poles and zeros, reduce settling time to 1/A0 level
• Pole zero cancellation be accurate and at sufficiently high frequency
• Cascode or mirror poles sufficiently high frequency• Reduce parasitic capacitances
– Increasing current– Using better processes
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• Other specifications to improve– reduced power consumption– low voltage operation– low output impedance (to drive resistive load,
or deliver sufficient real power)– large output swing (large signal to noise ratio)– large input common mode range– large CMRR– large PSRR– small offset voltage– improved linearity– low noise operation– common mode stability
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Two-Stage Cascode Architecture• Why Cascode Op Amps?
– Control the frequency behavior– Increase PSRR– Simplifies design
• Where is the Cascode Technique Applied?– First stage -
• Good noise performance• May require level translation to second stage• Requires Miller compensation
– Second stage -• Increases the efficiency of the Miller compensation• Increases PSRR
– Folded cascode op amp• Reduce # transistors stacked between Vdd and Vss
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VDDVDD
Vbb
Vin-
CL
Vin+
CL
Vyy
Vxx
DifferentialTelescopic CascodingAmplifier
Needs CMFBOn either Vyy
Or VG9
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Single-ended telescopic cascoding
Analysis very similar to non-cascoded version:think of the cascode pair as a composite transistor.
M2-MC2 has gm=gm2go=gds2*gdsC2/gmC2
Ao=gm/gop1=-go/CoRight half plane zero: gm/Cgd2
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Output swing is much less
Vo1 max: VDD – Vsg3-I1*R + |VTP|Vo1 min: Vicm – Vgs1 – Vbias – VTN
> Vss + Vdssat5 – Vbias – VTN
Several additional pole-zero pairs
At node D2-SC2:Pole: g=gmC2+gmbC2+gds2+gdsC2
C=CgsC2+cgd2+cdb2p=-g/C ≈-gmC2/(CgsC2+cgd2+cdb2)
Zero: z≈-gmC2/CgsC2
Pole-zero cancellation at -2fT of MC2
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Two stage
Mb
M1 M1
M3 M3
Vi1 Vi2
M2 M2
M4 M4
bias1
bias3
CMFB
bias2
Depends on supply and first stage biasing, may need level shifting
Analysis very similar, except very small go1, more p/z
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Cascoding the second stage
Very similar analysis, very small goNot suitable for low voltage design
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A balanced version
Mirror gain M:gm6:gm4 =gm8:gm3 * gm11:gm10
Ao = gm1/go * M
Should have small current in theseBut parasitic poles should be high enough
SR=I6/CL
GB=gm1M/CL
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Layout of cascode transistorsWith double poly:
In a single poly process:
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Folded cascode
Balanced has better output swing and better gain than telescopic cascodeBoth single stageNeither require compensationBut balanced limits input common mode range due to diode connection
folding
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VDD
Vin+CL
VDD
Vin-
Vbb
folded cascode ampSame GBW as telescopic
Differential amp requires CMFB
Iss
Iss determines slew rate
1 2
3 4
56
10
8
11
9
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• I1=I2=Iss/2, I3=I4=Iss*1.2~1.5
• Ao=gm1/go; go=gds9*gds11/gm11 + (gds1+gds3)*gds5/gm5;
• p1=-go/CL; GB = gm1/CL
• Slew rate: Iss/CL
• Vomin = Vg11–VTN, Vomax=Vg5+|VTP|
• Vicmmin = vs+Vgs1, vicmmax=Vg3+VTN+|VTP|
• Power = (Vdd-Vss)*(I3+I4) + biasing power
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VDD
Vin+
CL
VDD
Vin-
Iss
1 2
3 4
5
11
9
15
13
VDD
Cc
Rz
Triode transistor
vo+vo1-
CMFBVb
Vb Vb
Vx
Vy
The left side cascode and second stage not shown
Appropriate Rz moves zero to cancel p2
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VDD
Vin+
CL
VDD
Vin-
Iss
1 2
3 4
5
11b
9
15
13
VDD
Cc
Triode transistor
vo+vo1-
CMFB
Vb
VbVb
vx
Vy
11a
NMOS11b serves as Rz
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CL
VDD
Vin-
Iss
2
4
5
11b
9
15
13
VDD
Ccvo+vo1-
CMFB
Vb
Vb
Vbx
Vby
11a
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High speed low voltage design• Assume VDD-VSS<VTN-VTP, assume a given
Itot• Use minimum length for high speed operation• Use appropriate Von13,15 to achieve balance
between high fT and high swing• Select Von4,5,9,11 so that vo1 has + – 10%
(VDD-VSS) swing• Set desired vocm at (VDD+VSS+Vdssat13-
Vsdsat15)/2• Size transistors so that Vgs13 = mid range of
vo1 swing
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• Show that the compensation scheme has very similar pole splitting effect as in 7 transistor op amp before
• Show that appropriate sizing of M11b can cause the zero to move over p2
• If CMFB is applied at G3,4, compensation can be connected to channel of M9
• Show that with an appropriate attenuator, the go at vo1 can be made zero by positive feedback from opposite side vo1+ to G5
• Show that with an appropriate gm5, the go at vo1 can be made zero by positive feedback from opposite side vD12 to G5
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PUSH-PULL Output Stage
v v
At low frequency, vg7 and vg8 nearly constant as vo swings
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PUSH-PULL Output Stage• Let AI be the current gain from M1 to M7
• Icc=sCcVg6, (Iss-Icc)/2–>I3, I7=AI*Icc/2
• KCL at D6: -Icc + Vg6*gm6 +I7=0,
Can choose AI so that z cancels p2 for high speed
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PUSH-PULL Output Stage
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VDD
Vin+CL
VDD
Vin-
Iss
1 2
3 4
5
6
VDD
True push pull
Problem: bias current in second stage unknown
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VDD
Vin+
CL
VDD
Vin-
Iss
1 2
3 4
5
6
VDD
If VDD-VSS is sufficient
VbpVbn
But gain of 1st stage
reduced!
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VDD
Vin+
CL
VDD
Vin-
Iss
1 2
3 4
5
6
VDD
To recover gain:
Vbp Vbn
VDD
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VDD
Vin+
CL
VDD
Vin-
Iss
1 2
3 4
5
6
VDD
Vbp Vbn
VDD
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Figure 7.11 in book: process variations can cause large change in M21/22 current, and mismatch in M21 vs M22 bias results in offset voltage
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Figure 7.1-2
Same comment applies to this one
Both can have very small quiescent current when vin≈0But provide large charging or discharging current
power efficiency
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Dynamically Biased (Switched) Amplifiers
• Switched amplifiers lead to smaller parasitic capacitors and therefore higher frequency response.– Switched amplifiers require a non-overlapping clock– Switched amplifiers only work during a portion of a
clock period– Bias conditions are setup on one clock phase and
then maintained by capacitance on the active phase– Switched amplifiers use switches and capacitors
resulting in feed-through problems– Simplified circuits on the active phase minimize the
parasitics
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Dynamically Biased Amplifiers• Two phase non-overlapping clocks
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Dynamically Biased InverterIn 2 offset and bias are sampledIn 1, COS provides offset cancellation plus bias for M1; CB provides the bias for M2.
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Dynamic, Push-pull, Cascode Op Amp
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vIN - VSS - VB1
VDD - VB2 - vIN
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A Dynamic Op Amp which Operates on Both Clock Phases
True push-pullSingle stage
Differential-inSingle-ended out
No tail currentOff-set cancelled
For large swing:Remove cascodes
S. Masuda, et. al.,1984
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LOW VOLTAGE OP AMPS• We will cover:
– Low voltage input stages– Low voltage bias circuits– Low voltage op amps– Examples
• Methodology:– Modify standard circuit blocks for reduced
power supply voltage– Explore new circuits suitable for low voltage
design
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ITRS Projection – near term
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ITRS Projection – longer term
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Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range• Nonlinearity will increase because the transistor is
working close to VDS(sat)
• Large values of λ because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
• Large values of currents and W/L ratios to get high transconductance
• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range• Switches will require charge pumps
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Input common mode range drop
VDD – VDS3sat + VT1 > vicm > VDS5sat + VT1 + VEB1
1.25 -0.25 + 0.75 > vicm > 0.25+0.75+0.25
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p-n complementary input pairs
n-channel: vicm > VDSN5sat + VTN1 + VEBN1
p-channel: vicm <VDD- VDSP5sat - VTP1 - VEBP1
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Non-constant input gm
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constant input gm solution
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Set VB1 = Vonn and VB2 = Vonp
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Rail-to-rail constant gm input
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Rail-to-rail constant gm input
Coban and Allen, 1995
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The composite transistor
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Bulk-Driven MOSFET
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Bulk-Driven, n-channel Differential Amplifier
I1=I2=I5/2As Vic varies, Vd5 changes
and gmb varies
Varied gain, slew rate,
gain bandwidth;
nonlinearity; and difficulty
in compensatio
n
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Bulk-driven current mirrors
Increased vin range and vout range
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Traditional techniques for wide input and output voltage swings
1
Io =Iin+Ib
Iin
Ib Ib
1 1
1
1/4
VT+Von
VT+2Von
VonVon
>2Von
+
–VT+Von
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Traditional techniques for wide input and output voltage swings
1
Io
Iin Ib Ib
1
1
1/4
VT+Von
VT+2Von
VonVon
>2Von
+
–Veb
Io =Iin
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A 1-Volt, Two-Stage Op Amp
Uses a bulk-driven differential input pair,wide swing current mirror load, and emitter follower level shifter
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Low voltage VBE and PTAT reference
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Vref=I3*R3=
)]ln(1
))ln(1
([1
0
1
2
013 T
TkT
qR
mT
T
VV
A
A
q
k
RR
VR o
o
GBEGo
Low voltage band-gap reference
Needs a low voltage op amp
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One example implementation
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Threshold Voltage Tuning for low power supply voltages operation
+-
+ -
dcntntn VVV '
dcptptp VVV '
dcnV tnV
dcpV tpV
virtualtransistors
standardtransistors
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Implementation of the voltage sources+-
+ -
1 12
21 1
2
Bias Voltage
21
C
2C
IN OUT
dcV
Bias Voltagedc
V
IN OUT1C
2C
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A low voltage Op Amp core
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Op Amp Implementation
Clock booster Bias voltage generator
VDD
OUT
VSS
RVDD
IN
OUTM1
M2
M3
M4
M5
C -+
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Clock booster (doubler)
CB1 >> CBL
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Experimental Results
Power supply 750mV
Slew Rate 3.1V/uS
GB 3.2MHz
DC gain 62dB
Input offset voltage 2.2mV
Input common mode range 0.1V-0.58V
Output swing for linear operation 0.31V-0.58V
PSRR at DC 82dB
CMRR at DC 56dB
Total power consumption 38.3uW
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Q2
VG2
VG3
Q1
Q5
Q3
Q8
Q6
Q4
Q7
Q11
Q2Q1 Vi-Vi+
Vb5
Regulated Cascode
Vb7
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Regulated Cascode: one realization
k
VD
VS
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Common mode feedback for low voltage
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1.5v op amp for 13bit 60 MHz ADC
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Output Stage and CMFB
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Folded cascode with AB output
Lotfi 2002
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Simulated performance• 0.25 um process
• 1.5 V power supply
• 82 dB DC gain
• 2 V p-p diff output swing
• 170 MHz UGF @ 10 pF load
• 77o PM with = 1/5
• 0.02% 1V step settling time: 8.5 ns
• Full output swing Op Amp power: 25 mW
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Differential difference input AB output
Alzaher 2002
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Nested Miller Cap Amplifier
Not much successes
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Low voltage amp
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Low voltage amp
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LOW POWER OP AMPS• Op Amp Power = (VDD-VSS)*Ibias
– Reduce supply voltage: effect is small• Many challenges in low voltage design same as
before
– Reduce bias: factor of hundred reduction• Weak inversion operation• Nano-amp to small micro-amp currents• Needs small current biasing circuits and small
current reference generators• Needs output stage to drive the load
– Design it so that it consume tiny quiescent power– But generate sufficient current for large signals
– Tradeoff speed for reduced power
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Sub-threshold OperationMost micro-power op amps use transistors in the sub-threshold region.
np~1.5; nn~2.5
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Two-Stage, Miller Op Amp in Weak Inversion
At VDD-VSS=3V, ID5=0.2uA, ID7=0.5uA, got A=92dB, GB=50KHz, P=2.1uW
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Push-Pull Output in Weak InversionFirst stage gain
Total gain
S=W/L
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Increasing gain
go
Gain=gm/go
What is VON?
L5=L12, W12=W5/2S13<<S4
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Increasing Iout with positive feedbackWhen vi1>vi2
i2>i1
i26=i2-i1>0i27=0
i28=A*i26
itail=i5+i28
=i1+i2
i2/i1=e(vi1-vi2)/nvt
=evin/nvti2=i1evin/nvt
i1=I5 /{A+1-(A-1)evin/nvt)}
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A=0 is normal case
A > 0 can greatly enhance available
output current for load driving
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A=0
A=1
A=2
A=3
i1
i2
i1=i2
i2=i1evin/nvt
as vin
I5
I5
i1+i2=I5
New i1+i2
i1+i2 much faster than i2-i1