implementing multicore system using openrisc
DESCRIPTION
Implementing multicore system using OpenRISC. Advisor: Mony Orbach By: Jehad Ghanayem Ahmad Kiswani. Content. Project Goals. Term A Goals. Quick Overview of Term A Goals. Term B Goals. Gantt Chart. Requests. Project Goal. - PowerPoint PPT PresentationTRANSCRIPT
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Implementing multicore system using OpenRISC
Advisor: Mony Orbach
By: Jehad Ghanayem Ahmad Kiswani
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ContentProject Goals.Term A Goals.Quick Overview of Term A Goals.Term B Goals.Gantt Chart.Requests.
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Project GoalUsing the open source single core OpenRISC 1200 CPU to implement a multicore system. The OpenRISC 1200 is a synthesizable CPU
core maintained by developers at OpenCores.
The OR1200 design is an open source (under LGPL GNU) implementation of the OpenRISC 1000 RISC architecture.
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Term APrimary Goal: building an OpenRISC based system on FPGA.
Configuring the CPU.Building a SoC.Simulation and SynthesisImplementationDebuggingBenchmarking for future reference.
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OR1200 Block Diagram
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OR1200 Based SoC
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Term ASecondary Goal: choosing a multicore
architecture.
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Background NeededLogic Design.Computer architecture.
OpenRISC architecture.Multicore architectures.
Wishbone bus. Verilog. FPGA tools. Linux toolchain (uClib,binutils, GCC, GDB).
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Project Layers
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ChallengesThe work is done on multiple levels, from a
hardware RTL design to a C software.We aren’t working just with OR1200, but an entire
SoC.Numerous units and different architectures go into
the design.Hardware and software together.The lack of proper documentation for several
components of the system.
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Term BPrimary Goal: building a SoC based on a multicore implementation of the OpenRISC.
Choosing multicore architecture.Choosing the number of cores (could it be
dynamic ?).Designing, implementing and debugging the
system.Benchmarking.
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Where Are We Now We finished most of the reading, Still need
to read about: Wishbone bus. Verilog (partial).
The real work starts nowWe should have synthesis of the system in the
next 4-6 weeks.
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Gantt chart
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RequestsVirtualBox: open source software under GNU GPL.
allows the guest OS to run on virtual environment within the host OS.
VirtualBox Extension pack: allows the guest OS access to the USB.
FPGA: Xilinx XUP5.Extra HD space: 15GB in total.
Virtualbox base image = 5GBVirtualbox image with development tools = 8GBSource code of the core = 3GB15% extra space
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Thank you.