implementation of zilog z-88 base realization …
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ARD-Ai146 359 IMPLEMENTATION OF A ZILOG Z-88 BASE REALIZATION LIBRARY 1/2FOR THE COMPUTER SYSTEMS DESIGN ENVIRONMENT(U) NAVALPOSTGRADUATE SCHOOL MONTEREY CA T J SMITH MAR 84
UNCLASSIFIED F/G 9/2 N
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NAVAL POSTGRADUATE SCHOOLMonterey, California
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THESIS-MPLEMENATION OF A ZILOG Z-80 BASEREALIZATION LIBRARY FOR THE COMPUTER
SYSTEMS DESIGN ENVIRONMENT
by
Theodore John Smith, Jr.0.March 1984
Thesis Advisor: Alan A. Ross
Approved for Public Release; Distribution Unlimited
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4. TITaEter'suThesis
Implementation of a Zilog Z-80 BaseMatrsTeiRealization Library for the Computer Mac,18
Systms Dsig Envronmnt1. PERFORMING ORG. REPORT NUMBER
T. A&TN@Re S. CONTRACT OR GRANT NUMBER(.)
Theodore John Smith, Jr.
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Naval Postgraduate SchoolMonterey, California 93943
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I&. SUPPLEMENTARY NOTES
19. KEV WORS (C.ethueon Maffe Side It 0@00080F dedg #~vfr 6F 68o6h RUnMW)
* Computer aided design, CSDL, Z-80, realization, primitivemonitor
So. ABSTRACT (Coww sw Mooreso it uoernp mE Idwully Av wOp Noa .)
This thesis develops a Zilog-80 based realization library foruse in the automated design of microprocessor based controlsystems. The library is designed around Standard Bus boards.This bus is supported by a number of manufacturers for use inbreadboard construction, through a number of standard cards.The library of primitives developed implement the construction
* used in Computer System Design Language (CSDL) for (Continued)
DD I W3 147 OITION OF I NOV 6 1 OSSOLETE
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he Z-80 cpu. CSDL is a high level language that allows the* pecifications of tasks and procedures, and their time constraints
se of the design system and this library can enable Z-80 based* prototype controllers to be quickly designed and built.
*L i
Tm~
SI 0-U-01-60
~.12OSC........................................
Approved for public release; distribution unlimited
Implementation of a Zilog Z-80 Bass Realization Library forthe Computer Systems Design Environment
by
Theodore John Smith Jr. yMajor,,. United States Army
9.5., Loyola University, 1970 ~
Submitted in partial fulfillment of therequirements for the degree of
MASTER OF SCIENCE IN INFORMATION SYSTEMS
from the
NAVAL POSTGRADUATE SCHOOLMarch 1984
12*
Author: _ _ _ _ _ _ _ _ _ _ _ _ _
Approved by:-
Second Reader
Chairman, Departmn miisraiy Science
Dean of Information and Po Icy Sciences
3
ABSTRACT
library 'for use in the automated design of microprocessor
based control systems. The library Is designed around
* Standard Bus boards. This bus I% supported by a number of
manufacturers for use in breadboard construction, through a
number of standard cards. The library of primitives
* developed implement the constructions used in Computer
System Design Language (CSDL) for the Z-80 cpu. CSDL is a
high level language that allows the specifications of tasks
anid proceduresp and their time constraints. Use of the
* design system and this library can unable Z-SO based
prototype controllers to be quickly designed and built.
4
: .... IL
TABLE OF CONTENTS
I. INTRODUCT I O"- 9
I I A ACKGROUND -13
III. DESIGN1 19
A. THE CURRENT DESIGN SYSTE------- 19
S. CURRENT PRO..EMS WITH THE INTEL 8060 LIBRARY- 21
C. METHODOLOGYO - -- -- 23
IV. IIMPLENENTAT ION-..... .. 25
A. MONITOR-.. . - 25
B. ARITHMETIC - 29
C. CONTROL STRUCTURES--.-....-- 31
D. INTERRUPTS- ---- - -33
E. INPUTf/OUTPUT DEVICES- 34
1. Onboard Cpu Three Channel Counter Timer
Chip , 37
2. 8 Bit Analog To Digital Conversion
Board- -38
3. 8 Bit Digital To Analog Conversion
Board- 39
4. 64 Part 8 Bit Standard Bus To Digital
1/o Bus -- 39 --.
5. Keyboard/Display Card-- - 40---".-4
6. Dual UART Board. 41
F. TESTIN - - 41.p
- .. L_ -. / : .~-~- . **~* ~~..**,. S.. ~ .. * . *.- S5 *~~~
6. FORMATT INS OF PRIMIT IV- 42
1. Pollock Fi x i t - 45
2. Ross's Nuwcudl 46
3. Walden' s Data Base In- 48
V. RESULTS AND CO NCLUS O NS- 49
APPENDIX A -PRIMITIVE TITLE IN- 51
APPENDIX 8 GLOBAL VARIABLE LISTING 57
APPENDIX C - Z ILOG-SO0 REAL IZAT ION LIST IN- 60
ILIST OF REFRENCES.- 104
INITIAL DISTRIBUTION LIST------------- 106
LLP
LIST OF FIGURES
1.* Cost Versus Productioan by Lan guage- 11
2. Current Ross Controller Deign Sys e- 20
3. Monitar for Z-80 Realization 27
7.
7o.
14.
I would like to thank my thesis advisor, Lieutenant
Colonel Alan Ross, and second readers Prof essor Daniel Dolk,
for their assistance and support in this thesis. I thank my
wife Celeste and Peter for their support and faith in so.b
li a?
During the past ton years there has been a
mi croel ectroni cs revolution in which ever Increasing numbers
of functions have been put on a single chip. This has
translated Into a shift In system costs from capital to
labor. Hardware Is no longer the dominant factor in the
*cost of a computer system. The rapid drop in the price of
general purpose computer chip% has also caused a shift in
their application. Because of their low cost many of these
chips are replacing specialized control hardware.
In the past hardware was extremely expensive., Even the
design of a simple controller required a large number of
components. Many of these simple logic components cost as
such as the single chip general purpose controller today.
Because hardware was so expensivey controll1ers were
developed to use the minimum amount of hardware possible, at
the expense of a great deal of labor. This took the form of
engineers trying to minimize the number of gates or logic
functions used to implement the controller. The
microelectronic industry has now managed to put a functional
computer on a chip for the same cost an a few gates ten
years agoo
?7
Two examples of control applications are speed control
of a powuer plant generator and starting control of a gas
turbine engine. Control of powr plant generators has been
done in the past by mechanical controllers. The first
-i example shows the displacement of the mechanical controllers
because of the high cost mechanical systems. Even though
the mechanical controller was expensive, the degree of
control was imprecise. Here the driving factor has been the
desire to increase the amount of control possible as well as
reduce the cost of the controller. The starting of gas
turbine engines has been for the most part manual, because
of the large number of malfunctions that can occur during
starting. Recently, mechanical and digital starting systems
*- have been developed to start gas turbine engines. The
second example shows a new application for a controller,
primarily based on the reduced cost of digital component.
Unfortunately the very low cost of the microprocessor
cpu is a small part of the total system cost. Currently a
microprocessor can cost less than four dollars CRef. 1:
" p.5U3 , but the cost of a programmer can exceed $12 per hour
CRof. 2: p.903. Unless the system being controlled is very
costly or the volume produced high, the cost of designing
the digital system is not affordable. This cost can also be
exacerbated by the choice of programming language. Figure I
illustrates the costs of programming in a high order
language versus assembly language. Note that implicit in
this graph is a belief that assembly code will be more
. .. ",t.o .* .... . .
r.
* efficient at run time. Current optimizing compilers are
becoming more efficient and are approaching the efficiency
of assembly code. This has the effect of decreasing the
slope of the higher order language total cost line and
moving the intersection of the two line to higher production
levels. The implication to that except for the most
demanding of high production applicationos the coding should
be done in a high level language.
The second factor affecting the cost of programming is I
the complexity of the system to be controlled. As the
complexity of the control program becomes larger than a
single individual can intellectually handle, the program I.
must be subdivided and designed by a team. Currently, ]
hardware is chosen early in the design process and the
software is then written for that hardware. Early design
errors can cause all subsequent programming to be redone as
well as the possibility of having to select different
hardware.High L W Language
T .:.
* 11
Los VruPrutinblAssel Languag
FiueI[*f =p42 I.1. ** . -
0rSo*
S.-
The final factor is the speed at which the control must
. be performed. Same control functions must be accomplished
within a critical length of time. This factor competes
* directly with the previous two factors, cost and complexity.
There are two methods to determine if a program is fast
enough: program the controller and time the response of the
system based on an input or calculate the basic execution
time of the instructions in the program. In the first case,
exhaustive testing must be used to establish the maximum
runtime of the program. The second method is more exact,
but is labor intensive. In both cases, the program must be
present before the timing can be determined. If the program
is too slow it must be rewritten or possibly the hardware
must be changed in order to sufficiently increase the system
speed.
These problems in design have caused the computer
community as well as the controller community to increase
the use of simulations and other tools to minimize the risk
of these errors. Some have stressed the hardware design,
others have stressed the software design, and others have
Increased the use of models. As costs have decreased, a
final group has attempted to design the whole systim
including both hardware and software. In this last case we
see increased use of prototype development in computer
design. In the past this was not done because of the cost
of developing the prototype. It is becoming more feasible
now because the size and complexity of the final system
12
.
,,. ', ' " . " .. " , " " • . -; -" • ." * .- .. ." . . .- .. * ." *.. . . * . .'. ... '. .. '*'..'..- .. . . ' ".. . .. . .. . . .* *".
makes errors in design too costly to be routinely repaired
after the systems are fielded.
This thesis will investigate and develop a library of .
realizations based on the Zilog Z-80 cpu to support the
design system developed by ROSS Ref. 4: pp.7-83. Since
Ross's original work only contained a single library, this
second library will provide the option of building a
realization with more than one library. It will be possible 4to test the design system's capabilities to choose a
realization library based on a problem statement. The Z-80
hardware will be provided by the Standard Bus system of
prototyping boards, to make it possible to quickly design
and reconfigure prototypes. With the completion of these
goals it will be possible to construct a working controller
using Ross's design system and finally verify the accuracy
of this design concept.
II. -.
Computer aided design has been an evolving process over
the past 20 years, Intended to reduce the labor required to
engineer a product. This process can be described by
tracing several different threads. The first thread to be
follnod will be the design of controller systems. This
implies a ready pool of predesigned hardware. The second
13
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area to be looked at will be the design of hardware.
Finally, the design of the complete system will be examined.
hatelan proposed that computer aided design be applied
to the design of real time controllers, by adding the use of
realization libraries of standard components. He presented
a methodology for defining the timing constraints driving a
real time controller. This consists of having pairs of
contingencies and their associated tasks. By dividing the
total problem into paired contingencies and tasks, the
individual pairs can be reordered to meet the overall timing
constraintsCRef. 5: pp.17-202
Rose implemented Patelan's ideas for timing analysis and
added the potential for background tasks CRef. 6:
pp.15-22]. The processor chosen for the realization library
was the INTEL 8060. This particular processor was chosen
because of its availability and low cost. In the course of
his thesis, Ross also corrected Matelan's example problem
CRef. 7: p. 7 7 3. This came about while trying to debug
Ross's timing analyzer. The timing analyzer was correct and
.ateln's example was wrong, because hatelan had scheduled a
potential second occurrence of a contingency task pair
within the time needed for the execution of the first
contingency pair. This highlights the need for some
automated means of assisting the designer in avoiding
similar errors. Ross provided sample executions of the
program with accompanying paper hardware realization,
however, no actual hardware was built or tested.
14
.... ...,-... ........ .. .. .... . .. , ..... ,.. :. ... .,. . .. .. .. . . . . . . .. . . . .. . ,: . -.
Pollock attempted to build an actual hardware
realization in the form of a fuel controller far a car.
Pollock never did attain this goal in the course of writing
his thesis. He did add a variety of additional hardware to
the INTEL 8060 realization library to include a floating
point chip for floating point operations and transcendental
functions. He criticized Ross's FORTRAN implementation of
the timing analyzer and functional mapper. He suggested
that all of the present programs be scrapped and work begin
anew retaining Matelan's theoretical foundations. Much of
this criticism appears to be the result of the difficulty in
adding additional primitives. This is caused in large part
by the column reads performed by the FORTRAN functional
mapper on the primitive listing. The structure of the
primitive listing itself has pointers that refer to parts of
the listing by a relative line displacement that makes
changing the primitives tedious. CRef. 8: p.343
Manwaring argues for a similar system, independent of
Ross and Matelan. His ideas on libraries of implementations
for different processors are equivalent to Ross's, but he
does not include the selection of the processor by the
design system. As in Ross's system he argues for a design
system that chooses hardware and the software to run the
system, by means of a high level language to state the
problem. He also does not consider the analysis of timing "
in his design system. But he does concede that the compiled
code may run too slowly and portions of the .software may
15
have to be manually optimized to met tim constraints.
Additionally, his proposed design system does not manipulate
the timing problem and realizations to the extent that
Ross's does. He proposes generating a compiler error if the
desired primitive doesn't exist in a particular processor's
library, rather than trying a different hardware
realization. He does argue that the rapid generation of
programs can make digital controllers available for more
applications. CRf. 9: pp.431-435]
Diehl# also independent of others, presents the system
LOSE-MIIR to design controllers using microprocessors. The
input is in the form of a state table and flow diagram.
LOBE-MIR process the state table and flow diagram to obtain
an intermediate language. The intermediate language is then
manipulated to optimize the following: the sequence in which
the condition variables are tested, the assignment of
conditional inputsy the control of outputs to ports and the
number of jump instructions. This system is in contrast to
Ross's in that there are no time constraints, the system
merely attempts to make the controller as fast as possible.
The ultimate machine code is just a direct translation of _
the intermediate code to the target controller code, with no
guarantee of a specific response. [Ref. 10: pp.328-33,
Finally, Sherlock studied the problem of making entries
of the problem into the Problem Statement Analyzer easier.
After a lengthy review of human factors engineering, a
program was written to make the input of a problem 177::
-. . . . . ..'-'
formulated in Computer System Design Language into Ross's
design system easier. CRef. 11: pp.15-16.
The second thread in the description of automated design
tools is the design of the hardware itself. Chu has been
working in the area of microcomputer design since 1965. H.
states that the following need to be described in the p
language: identification of the selected L81, M8I, and 881
chips, a plan for the Interconnection of these chips and a
description of the internal structures and sequences of
these chips. He also describes three level of increasing
detail in the design process: functional, ideal timing, and
real time levels. He proposes that, given a functional
description, a computer system could be designed and
simulated prior to the actual construction of the system.
The system would need a large data bass of chip
identifications and interconnections to function. He
proposes that manufacturers provide disk packs of their chip
descriptions in addition to the data books that they now
provide. CRef. 12: pp.45-51,
Heath, Carroll and Cwik descrilpe a modified version of
Chu's Computer Design Language that was running at Auburn
University. Two new declarations were added to allow the
easy implementation of buses and front panel lights. They
conclude that the following can be easily tested using
simulation: basic system organization, function of some
microcode, timing problems, limitations on inputl and
throughput rate. CRf. 13: pp.93-1062 .7
17
.-. ~ -~- - . .. . . - . . . . . ...... . .. - _L-
Hartenstein and Von Puttkamur describe the language KARL
and its associated graphical description MBL. KARL is a
Pascal-like language for allowing simulations of a processor
at the register transfer level. It is an improvement over
- CDL in it's original form in that it allows the integration
of a graphical description of the design through the use of
.. ARL , a block diagram language. Once inputed, the design
*.. can be simulated for correctness and finally the design
system can output detailed layout drawing and mask
specifications. rRf. 14: pp. 15-13O2
The third and final thread is the design of both the
hardware and the software. A feasibility study was
" conducted on the design of an integrated design facility by
: the US Air Force at the Rome Air Development Center. The
initial study was performed by Sperry Univac. The concept
included a design facility wmre total system design
. alternatives could be emulated for the purpose of providing
and evaluating designs prior to actual development. Two
.- important conclusions of the study were: the system could be
used for requirements formulation as well as hardware and
software design specifications and the present system was
i* inadequate for the analytic determination of operating
performance. Further, the study concluded that additional
tools should be added to assess operating performance, even
" though the tools would only provide approximate answers.
" CRef. 15: pp.19-20, 253-2503
718
Having reviewd the current progress in automated
controller design, further study on the problems associated
with the design system developed by Ross will be done. This
i done to limit the ucope of the problem to a manageable
size.
A. THE CJIENT DESKON SYSTEM
The area of study for this thesis is the design system
established by Ross. In this system the hardware is
selected from predesigned components. The major goal of the
system is the rapid design of prototype controllers. The
system is not intended to produce a final packaged
production design. It will produce a breadboard controller
capable of verifying the feasibility of the controller, its
desired characteristics, and timing.
The current design system is shoan graphically in figure
2. The library of primitives currently contains only an
Intel 8080 realization. The implications of this are that
if the controller cannot be designed using an Intel 8060
processor, then the system will indicate that the controller
is not possible.
19"'
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. . . . . . . . . ... . . . . . . . . . ....--. "..
.. 4 ~ ~ S . . . . * . ~ . -. * ~ ~ . ** * . -' °*5. 4..~**5..-~.- 5........... ~ u~u~ r2 * 5.5 ~ . . 5.5. 5.~5 . '. -. -
~ ~ ~P r II -L
The purpose of this research is to add a Zilog Z-9O
based realization to that library. Construction of this
second library will give the design system an alternative
mnethod of realizing a controller. This will also enable
further testing to be done on the design system itself.
ICEd Ffc rTip I n/description
TransatorLibrary[Update
Priitve Timing ELibrary ofIea IzatiVolumes
dware Functional Botwar-e
Analyzer
Current Rtoss Controller Design System
Figure 2
Another reason for adding the Z-80 realization library is to
allow the actual construction of a test controller from the
design system. A thesis currently being conducted by Riley
will use the design system and the primitives developed in
this thesis to construct a generic gas turbine starting
controller CRf. 163. Since an actual controller will be
constructed using the primitives in this theoss provisions
have been added to the primitives to allowv ease of debugging
and testing@
20 '5
So far there has been no complete exercise of the design-
systems Pollock attempted to build a fuel controller far a
I car but no hardware was built. Hilstedt studied the
* problem of using the design system to construct digital
* filters, but also did not build any hardware. Mlany of his
I problems related to converting the program to run on a VAX
* 11/780. A prime purpose of this thesis is to get a working
system that can be used far a complete design test in future
I projects. With this as a goalp the Standard Prolog
breadboard system was chosen as a source of hardware. This
particular system Is available far testing and offers
potential for quick prototype assembly*
* 9. CURENT PRODLM48 UM~ THE INTE D060 LIBRARY
The current realization library, basod on an Intel 8060,
has Its origin in Ross's original thesis In 1973. As
mentioned before, the library has been modified and expanded
by Pollock and Heilstedt, woith specific projects in mind.
In the six years since the library's Inception the cost of
hardware has continued to decrease, and its power increase
The change In orientation can be seen In the types of
primitives put In the realization. Pollock added a great
deal of hardware, including a floating point processoir, to
the 8060 library. The Zilog Z-60 was chosen as, a neer chipr
* that could add a higher performance library to the design
system. It was also chosen because of its popularity and
L similarity to the Intel 6060.
21
The floating point processor added to the Intel 8080
library confuses some of the design issues in using the
design system. By adding the floating point chip the cost
of the system Is greatly increased. Because of their -..
infrequent uses floating point chips do not have a
production volume that has all-wed the general purpose
processing chips to decrease in price. The use of the
floating point chip will be eliminated in the Z-90 library.
An alternative to this in a hierarchy of processors is a
high performance library being designed around the Intel
8089 by Cietal Ref. 173. Because of the hardware
instructions available, this chip may offer similar
performance wtth reduced cost.
The current Intel 8080 library does not treat negative
numbers correctly. The comparlson, multiply and division
primitives all were written only with positive integers in
mind. The Z-60 library will incorporate code that also
provides correct operations with 2's complement arithmetic.
The monitor was initially designed to be used without a
stack. Because of that the monitor, when calling a routine,
used an intermediate table to determine where the task was
located. Later Pollock added a stack to the primitive
listing, but the monitor structure was never completely
modified to take advantage of it.
Finally, there is no protection from the propagation of
errors. Should an underflow or overflow occur, the sign of
the result will be incorrect and no action is taken to
22 .-..*-
' minimize the effect. In terms of control, it is possible
that the item controlled will be directed to perform the
exact apposite action from what is required. As an example,
if a positive number opens a valve and a negative number
closes the valve, then an overflow will cause the valve to
be closed at a time when the control program is trying to
open the valve wider.
C. HEIHODOLOGSY
To capitalize on the effort that has gone into the Intel
8060 library, each of the primitives will be reviewed. If
the primitive is still required, then the initial draft of
the Z-60 primitive will be a direct translation of the 8080
code to Z-6O assembly code. Speed improvements will then be
attempted using the additional instructions available to the
Z-.O. If there is a tradeoff to be made in speed or code
*. size, then speed will be chosen. This will eliminate the
use of the jump relative instruction, since it is slower but
more compact than the jump absolute instruction.
All loop and control structures in each primitive will
initially be made with labels to facilitate writing the
* primitive. Then each primitive will be incrementally tested
. using a debugger. When the primitive works correctlys, the
labels will be replaced with relative assembly jumps to
insure portability in the actual use of the primitive. Each
primitive will then be tested again with a debugger to
insure that the primitive still functions correctly. In
23
* testing a primitive all paths through the code will be
exercised. To do this numbers from a representative class
will be chosen and entered through the debugger.
The floating point processor used in the Intel 8080
*library will not be used In the Z830 library. The floating
point arithmetic operations will be implemented In software.
- To insure compatibility with other computers, the IEEE
%Ingle precision floating point standard will be used as an
interf ace form for external Information. Keeping with the
* spirit of the standard and the Intent of the control system,
overflows will be given a value of Infinity. Though not
discussed in the floating point standard, conversions of
* infinity or numbers larger than the range of an integer
- value will be converted to the largest Integer value
representable. This in an attempt to minimize the
propagation of opposite control responses.
The completed primitives wIll be aggregated into a
single library file and then processed Into a format
* acceptable to Rao's Design system by use of Pollock's
* formatting utility. This will allow the primitives to be
individually tested. Being able to add a few primitives at
* a time and then have them formatted by Pollock's formatter
program can Isolate any problems Introduced by the newly
added primitives. Using Pollock's formatting program
enables a primitive library to use Ross's design program
directly, without having to make tedious computations of
various pointers. Walden's data base storage CRef. 1U3 of
24
the primitives will not be tested by this library, in order
to minimize the amount of change to the design system and
because it does not allow the entry of code from a file.
Appendix A lists the names of the primitives and a brief
description of their purpose. This list has been compiled
to reduce the volume of data that must be scanned to
understand the coverage of the library primitives. It
should be noted that in contrast to the Intel 8060 library,
many of the hardware primitives are eliminated in favor of_ -
software primitives. Furthers the aggregation of the
hardware primitive is now at the board level, rather than
the component 1level.
IV. ItrLEPEN1ATWNI2
A. MlONITOR
The original monitor structure used by Ross and Pollock
consists of an infinite loop of contingency task pairs. The
order of the pairs is determined by Ross's timing analyzer
based an the timing constraints of the various tasks.
Control is transferred by the use of an intermediate table
which contains the actual address of the task to be
executed. When a task is completedy control is then
returned to the task loop. A task counter is incrmented
and the next task is executed via the intermediate table.
When all tasks in the loop have been executed onces the task
counter is reset to point to the first task in the loop and
25
-~~.
the process repeats itself. This structure has its source
*" in the original library developed by Ross which did not have
a stack. The lack of a stack prohibited the us* of calls
- and returns for subroutines. Later a stack was added and
subroutines used to transfer control to the contingency
test, but the monitor was not changed.
The ZOO monitor, shown in Figure 3, consists of a main
loop that has a single entry and no exit. Switches cause
various submonitors to be executed from the main monitor
,loop. This was done to minimize testing of conditions that
are mutually exclusive. Timing analysis is done on the
submonitors plus the time to execute the main monitor loop
with all switches false except one. All tasks, conditions
and procedures are executed as subroutine calls from the
polling loop in the submonitor. Initialization is handled
as a submonitor without any timing constraint. The
initialization will be executed first and then the
initialization switch set to false to preclude
initializations from being executed an subsequent iterations
of the main monitor loop. Since all submonitors return to
the top of the main monitor loop, the top of the main
monitor loop resets the stack pointer to eliminate any
pending operations in the submonitor loop. This also allows
error handling to be executed by jumping to the top of the
main monitor.
26
..4%
N"_ ': g g N '_': ':'- ., , ,...... :.,..,-. ,, . . ..",'2 _, .. ... -... . ...........- '....'.' *- . -. .'- . .'.'4:- ',' ',
Working Test Purpose4000H4 1001 jump to 4000h offsget to protect loading
rom400014 4000H4 create stack and do any required
hardware ininitializations, then jumpto main monitor loop
uspvsr main monitor loopreset %tack pointeran switch 1 jump to submonitor 1an switch 2 jump to submonitor 2on switch 3 jump to submon itor 3
jump to stpvsrstubmoni tor 1
initialize variablesUser defined initializationsswitch 1 - falsejump to 41spvsr
usubmonitor 2Call1 ProceduresOn Condition do callI TaskCal I ProceduresOn Condition do call Task
If switch 2 -false jump to Qspvsrjump to Gsubmonitor 2
Osubmonitor 3Call1 ProceduresOn Condition do call TaskCall1 Procedures .
On Condition do call Task* ( V..
If switch 3 - false jump to stpvsrjump to Osubmonitor 3
ProceduresTasks
VariablesBottom of Stack
32767D 32767D Top of StackMlonitor for Z-00 Realization
Figure 3
The library supports testing the monitor prior to
building hardware and programming sprains by the use of two
switches set in GLODALS. DAT. These switches are the DEDUS
27
and switches. Three modes are allowed: Standard Board
with loading roe, program in an ALTOS CP/M computer 1/O
through standard BDOS calls, and Standard Board without
loading roe. The default mode is for both of the switches
to be false. This allows loading of programs for test into
the ram memory of the standard board system, using an ALTOS
computer. The BDOS jump location is also defined in
SLOBALS.DAT, to allow changes for computer with a BDOS jump
location other than 5.
By setting the DEDBUG switch to true to activate
conditional assembly of test components, the conditional
assembly relocates the beginning of the monitor to lOh. In
the standard board system this area would normally have the
loading monitor. That monitor has provisions for offsetting
the interrupt locations to 4000h. To keep the rest of the -
program in the same relative position during the debug mode,
a jump instruction is put at lOh to jump to 4000h. This
will cause all code to be identical above 4000h to the
breadboard system. This allows the use of a CP/M-based
machine to test the software prior to hardware construction.
The top of ram, here the stack would normally be located,
is moved down to the top of the temporary program area in
CP/Iq, to location 32767. Inputs that would normally be an
I/O request to a input board will be transformed into BO
calls for input at the keyboard. Outputs will be handled as
a 3008 request for display to the console. In bath cases
the 3005 call includes a description of the board the input
28
or output would be going to as well as the value of the
respective input or output.
In contrast to the test moni tor the working monitor will
have its initialization assembly begin at 4000h. This is
the normal starting point far the NPS Prolog loading row.
This location was chosen to allow ease in starting the
moni tor program.
If a rom is actually burned and the nps loading rom is
removed, then the conditional assembly must start at 66h.
If a non-maskable interrupt, (generated by a resset button),
is issued to the system, it will begin executing code at
66h. This permits the user of the system to use the reset
button as a start button as well as a trouble button. The
ROM is banked to start at O000hp the locations 0000 to
006h, normally unused. These locations will have no
operation codes placed there. Any maskable interrupt can
then be accidentally triggered without crashing the system.
The maskable interrupt would imerely jump to 38h. and do
NOP's until it reached the initialization routine far the
monitor.
B. ARITHMETIC
The format -for the single byte Integer operations used I-
by the 8080 realizations has been retained in the ZO O*
realization. It is a two's complement arithmetic. The add
-* and subtraction are essentially the same as in the Intel
29
o" -I,
library. The multiplication and division have been changed,
since negative numbers were not correctly implemented. In
addition, the option of checking the single byte operations
has been added by checking for an overflow after performing
the indicated operation. If an overflow occurs, the result
will be t to the largest representable positive or
negative number based on the sign of the result.
The format for the double byte integer operations is the
same as the Intel 8080. The format in stored with the least
significant byte first in memory. By using this format, the
double byte operations in the 29O Instruction set can be
use directly. This particular hardware instruction is used
because it takes less time to fetch two bytes with one
instruction, than fetching a single byte at a time and using
two instructions. Once again the addition and subtraction
are the same as the Intel 8090, since the same machine
instruction is used for the operation. The multiplication
and the division have been changed to treat negative numbers
correctly. The check for overflow is done in a similar
manner as the check done on the single precision arithmetic.
The format for the floating point operations is a
departure from those done in the Intel 8090 library, since a
floating point chip is not use in the ZO library. The
original approach was to do floating point using the IEEE
standard single precision format. Further study of this
approach has shown it to be Impractical for two reasons.
The first reason is the ZO is a two's complement machine
30
-'. .-:- ... '
and the IEEE format requires sign magnitude operations. The
second reason is the packing of the IEEE format across byte
boundaries. To use the IEEE format would require converting
the sign magnitude number to two's complement and shifting
the number to a usable format. This would have to be done
before and after every arithmetic operation. To eliminate
the overhead of the transformation, a primitive has been
made to convert the format used In the realization to and
from the IEEE format. The cost to implement the change has
been the use of an additional byte of storage. The format
used for the ZOO floating point is:
Exponent sign mantissa
39wo.&32 31 309....0
* The exponent is an eight bit number as in the IEEE standard,,
however it does not have an offset. Instead it is
represented as a two's compleomt number. The mantissa is
represented as a four byte two's complement number. The
mantissa Is fetched and stored two bytes at a time, so the
position of bytes 1, 2, 3, 4 are stored as 2, 1g 4, 3. The
additional byte Is necessary to preserve the accuracy for
rounding to the IEEE format. The leading 1 is expressed,
rather than being enc-oe as in the IEEE format.
C. CONTROL STRUCT1URES
The control structures can be divided into two
categories, selection In straight line code and subroutines*
The distinction is made because of the manipulation that
31
z--.4.
* - . - .T . r w-..-r. ~ rrrr rr - I - -+ -. -
Ross's timing analyzer dos with the order that conditions
are tested and tasks selected. In the first category four
constructs are supported: IFf, Mhile, JUMP-ON-TRUE, and
JU-ON-FALE. The IF and the WHILE support the CSDL
language constructs directly, that is, there are primitives
in two parts that will directly perform either of the two
selections. They are used by placing the first portion of
the primitive before the conditionally executed code and the
second part of the primitive directly following the code.
In the case of the IFy if the condition is not true, then a
jump is done to the code immediately following the second
portion of the if primitive. The JUP-ON-TRIE, and
JUMP-ON-FALSE support the CUlE compiler with more primitive
operations for compilation Into higher constructs. In all
of these primitives, selection around straight line code is
involved, that is, these primitives will cause a section of
code to be included based on a condition, but will not
directly support a construct such as an "else".
The second general category contains the control
structures effecting subroutines. They are TADENT, PROC and
two versions of EXITPROC. The purpose of these control
structures is to allow the timing analyzer to manipulate the -
order that conditions/tasks are called to guarantee the
maximum timing. To manipulate the timing the timing
analyzer will change the order in which condition/tasks are
polled as well as duplicating some condition/tasks to insure
that they are polled often enough to ensure the timing |_
32
, '.. ,,.',, " .," ..',, : .," ,.~~~~~~~~~~............ .. ,.,....... -..... .......-..... ,..... .,,.... -............ .. .. .... .. o... ..--. ,", .
guarantee. This manipulation is done by making successive
entries using the primitive TADENT, wdich will cause a entry
of a condition/task in the polling loop. The primitive
TADENT uses subroutines in two ways. First it uses an
unconditional call to a subroutine to evaluate a condition.
After returning from the conditional evaluation, a second
subroutine call is made to the task based an the results of
the condition. This is a change from the method that Rose
used in constructing his polling loop. He chose to minimize L
the amount of ram required at the expense of increasing the
number of jumps required to execute a contingency/task pair.
The primitive combines the functions of Rose's primitives
TASENT and TAUACCP2 into a single primitive. The increase
in mmory will only become a problem eien there are great
differences in the timing requirement of different
contingency/tasks. The great difference will cause the
timing analyzer to make multiple entries of the
contingency/task with the shortest time constraint. P0C
marks the beginning of a subroutine. EXITPROC provides both
a conditional and an unconditional return.
D. INTinLPilrs
The use of interrupts was not implemented in the 9080
library. Interrupts can offer the advantage of faster
response to a particular contingency, but they add
additional execution time to the contingency/task pairs in
the fom of interrupt overhead. Since the very nature of
. . . . . --'-" "-"-" " "'--
the design system Is guaranteed maximum timing, the faster -
esponse to a particular task is not a major issue as long
as the overall timing constraints are met.
The non-maskable interrupt is used by the Z-O library
as a means to start the controller. This is implemented by
starting the definition of the variables, input
output/ports, hardware initializations and stack
, initialization at 6&h, the non-maskable interrupt location
in the Z-80. From here the execution will take the program
* into a continuous polling loop of the contingency task
* pairs.
A problem arises in trying to control tasks where speed
is computed by the design system. Currently, the design
system guarantees that a task will be tested within a
certain time constraint, but It can be tested earlier. This
can occur when all the conditions are false and no tasks are
performed. In this case the only time required to execute
the polling loop is the time to do the actual test of
conditions. Within the structure of the primitives there is
no way to make them run in a fixed amount of time, since the
arithmetic operations take a different amount of time
depending on the particular input values. Also the polling
loop's overall timing changes depends on how many of the
tasks are executed. The only guarantee the system gives is
that the time the monitor will take to execute all the tasks
and tests of conditions will be less than some maximum. An
external reference Is needed to insure a fixed amount of
34
time has elapsed. In the case of the 8060 library a clock
was added to the system to give an external reference. To
minimize the cost and keep the system simple the Z-90
library uses the CTC chip. The particular standard board
used contains a counter timer chip with three channels as
well as the ZSOA and provisions for adding an-board memory. OWL,
One of the channels in the CTC is used to generate a
maskable interrupt in a fixed period of time. This
interrupt will be handled by incrementing a word in memory
that represents the current time. The details of the
implementation of the clock interrupt primitive are in
appendix C. Brief conditions will be recorded by using
another channel on the CTC to count the occurrences
independent of the operation of the cpus This is implemented
through another primitive that connects the external signal
directly to the third channel of the CTC chip. A second
primitive is used to read the counter in the channel and
reset the counter to zero.
This particular clock primitive has an interrupt rate of
a millisecond. It is included for use, but has a major
disadvantage in overhead. The interrupt service routine
requires 100 clock cycles to implement. This equates to
2.5 of the available monitor time. The interrupt rate can
be reduced to every 10 milliseconds for an overhead of .252.
This in turn makes the polling loop longer to accommodate
the accuracy of the clock. Because the exact point of
interrupt cannot be determined prior to execution, all of
35
* ''* '- ' -* * ' ' * ' * * ' . ." " " " .-- % - " .- "- "-"7 * . - " . . • " -
-7-~~ 7777 Uz
the times computed far the contingency/tasks must have the
interrupt service time of the clock added to their maximum
time. Several executions of the Interrupt are required to
built up same accuracy in the computation of the stored time
in 10's of milliseconds. This would be adequate for events,t'.
that are very slow (in the realm of seconds), but inadequate
for those taking fractions of a second. .,,,
E. INPUT/OUTPUT DEVICES
The selection of input or output software primitives has
an additional effect of adding an associated hardware
primitive. The hardware primitive in turn require some
initialization prior to operation. The hardware
initialization is done before any user defined
initialization in order to hide the details from the user.
Since the user is not required to consciously select all the
I/O references in the very beginning of his program, an I/O
board can be added with any 1/O reference. A method to add
the required initialization is needed that could be placed
anywhere without effecting the runtime execution of
primitives. The compilations of the hardware and software
is currently done in a single pass. This also requires that
the actual initialization code be added to the output code
file at the time of the request. A linked list was used to . .
al low the random placement of any required hardware
initializations. This does have an undesirable effect on
timing. To keep other segments of code from executing the .. ,
36
--:-- :
initialization, a uncoditional jump is used before the
initialization. Since it isn't knoun hen this is executed
by the monitor as part of a condition, the hardware adds the
time for an unconditional jump anytime an initialization is
required.
1. Qobgad MW Th3 Chfnnel QMDM TiC ChI.
The solution to the interrupt overhead dilemma was
to eliminate the interrupt driven clock. The second clock
primitive uses two of the CTC chip's channels. One is used
as in the interrupt case to create a one millisecond clock.
The second is used in lieu of a memory location and an
interrupt service routine. The second channel's clock input
is tied to the output of the one millisecond channel. The
capacity of the channel is 65g536 milliseconds or just about
a minute. This short time period is a problem for some
applications that may require more than a minute of running
time, so a 25 millisecond clock primitive was added. The
construction was the same as the I millisecond clock except
for the variable loaded into the channel 0 counter. The
other service primitives remain the same, except that the
magnitude returned represents a different elapsed time.
There are two additional primitives related to this clock:
one to read the time and one to reset the clock to 0. This
leaves one channel in the CTC on the cpu board for other
purposes.
37
- * * . . . .- . . . . ... .- *.. .. . . . . . .
The remaining channel is used to count fleeting
external events that potentially take fractions of a monitor
loop execution. That channel is initialized and read/reset
via another primitive. Since the CTC chip was included with
"* the cpu board and contains only 3 channels, the primitives
will allow a single counting channel and a clock or three
counting channels. No provisions wre made in the library
to add additional counter timer chips nor to multiplex the
channel over several inputs.
2. M A enalg T Dgitali Gtixqsionr grA-
Input of analog voltages was done by an
analog-to-digital primitive using a MOSTEK MDX-A/DO board.
The accuracy of this board is limited to 8 bits. The
primitive III allow up to 32 analog signalsp using two
separate hardware boards. Each of the requested signals are
counted using a global variable NATODE. This cannot be used
directly since each board has a sIngle port address. To
decode the address a second variable NATODP is used to
indicate the actual address used. Up to 16 signals can be
multiplexed to that part. For signals less than a board's
capacity, the NATODE variable was used to compute the proper
pin for the input signal. Fr signals greater than one
board, 16 was subtracted from the NATODE and that number was
used to assign the input signal to the second board. To
keep from changing the actual value of NATODE, a scratch
variable is changed and that value is printed in place of
NATODE. The hardware configurations of the board are
..*9
%. . %. .
.-..% '_...... ..'. ...:.. y ...".. ..-..'.v ..'.. .','..'.,;.-,:-,v ".,..,.'..'.. ..,...'..'% :..'... --.." .-'..'.. ..-. .,... ...-. .". ..... .. ,.'.-.. .','..-.'......,. .,'..,. .".. . .
controlled by the hardware primitive if a board is required,
however, the analog signal assignment to that board was done
by the software primitive. This is in contrast to the other
primitives where all the signals were assigned pin by only
the hardware primitive. This was done in the software
listing, because of the multiple signals assigned to a
single board.
DIiRital To IAa&IM enu gg urs. -°ard
Output of analog signals is planned through a
digital to analog standard bus board. The configuration of
the board is analogous to that of the analog to digital
board. The signal capacity is also planned to be the same.
4. h0 gr~t M fltk aard flum 19 Riuital IO %a
This board was intended to be used to turn devices
on and off. However, the MOSTEK MDX-DIOBl board was found
to be merely an interface from the Standard Bus to the
Digital 1/0 bus. The board was designed to multiplex 64
channel through a single standard board card. The board has
the capability to send or receive 8 bit wide signals to a
PUOSTEK digital I/O board. This is the capability that was
desired when the board was purchased. However, the digital
1/0 board that actually controlled external inputs was not
purchased. To retain some of its intended capability,
turning leds on, the address lines were wired to turn on
lamps when a particular addresses was outputted. This is
just an intermediate primitive to make use of the board
until the digital 1/O board can be purchased. Because the
39 b
,SI
light is only illuminated when the address is strobed, this
is not an adequate primitive for a working system. To keep
the light illuminated long enough for a person to see the
lamps the address is strobed for several sncondsp making the
execution time for this primitive long.
5. gjnx29WdRgLisRhs QW
This board was added to the realization library to
provide limited front panel access to the controller. This
particular board has a programmable key pad from input and
light emitting diodes and segment alphanumeric output
capability. Because of the many functions on the card, each
function is provided as a separate primitive. The card is
include only once and is initialized in the hardware
primitive. The two rocker switches are tested using
primitive S.ROCKER. The board also contains eight light
emitting diodes that are controlled using primitive
8.OUTLED. In the case of S.0UTLED the individual LED is
turned on or off based on a boolean value. The Keyboard can
be defined using . INKEY. Pressing the key associated with
a boolean flag causes the flag to be complemented. All
three of these primitives assign the key or light in the
snoftware primitive. None of the primitives associated with
the keyboard/display card will add any additional boards,
but will issue an error message if more lights or keys are
requested than are available on a single boards The last
primitive associate with this card is 8.0UTDISIT. This
primitive will print a message to the alphanumeric digits on
40
-6 %°
... *.. .*..- ..---. - - - - - - - - - -
. . . ... ~ ~.* .5 SI ~ ' *.
p T!
I- the card in the form of a scrolling banner. The code for
this primitive was provided with the board. It has a
distinct penalty in that it uses 500 bytes.
6- R5a L. :MC
This board was provided along with a bootstrap roe
an the cpu board as a method to load programs into the
controller. This provided the means of testing the boards
program using a ram board. The final controller does not
require this board unless specifically determined by the
application. No primitive is required to use this board,
but its installation is required if the MPS Bootstrap
loading prom is used. That prom assumes that the terminal
is connected to the A port and that another Altos computer
is connected to the B part of the board. In final use the
program would be contained in a roe or a prom, making the
loading unnecessary.
F. TESTIN3 -
Testing of the primitives has been done in three phases.
First, the primitives have been functionally tested
individually in the course of writing thee. They have all
passed an assembly and have been executed individually using
a debugger to insure that the outputs are appropriate. The
code associate with an initialization of a board has been
adapted from the manufacturers examples and has been
asmbled. It has not been run on the Prolog System to
41
-4%".
%° % .
check its accuracy. The primitives have been tested
individually# but have not been tested for interactions.
Because the controllers written with these primitives
can be potentially quite complex, two additional methods of
testing the controller's program are provided. The first is
the debug switch. This is a global variable that allows a -
conditional assembly of the primitives. The purpose of the
switch is to allow the program to be run on a micro computer
that has a z-0 processor and the CPH operating system. The -
switch causes all outputs to be sent to the console and all
inputs to be requested from the keyboard via a message to
the console. To Implement these features the additional
primitives wrtbin and messout are included. Their purposes
are binary output and message output respectively. The
second method is the use of the serial input/output board
and bootstrap roe to load the program from a microcomputer
into the controller. This permits the controller to be run
and controlled from the microcomputer. This also permits
the controller to be tested with its 1/0 boards for proper
operation prior to loading the program into a prom.
9. FORMATTINO OF PRIMITIME
The format of the primitives is driven by several
factors. The most obvious Is the instruction set of the
cpugand the next is the form of the arguments. The fore of
the arguments used in the Z-43O library were typically rslt,
argl, or rslt, argi, arg2. This Is the same form as the
42
* . * * 1 1 , ., -.. *. % -' d • . . o ,- - - o . . - . * * , - o'; € ,,r. .,, - ,' , ,3 .. _,: . ; _,-.. . . .,,.,.. .,.*,.; .. ,...., , . ,_- * ,..,. : " .. ,,*.. " ' ' , ,
..
Intel 8060 library. In the construction of the primitives
all results are stored at the conclusion of a primitive. In
the case of a complex evaluation this might cause a value to
be stored in memory only to be fetched by the next
primitive. This is very costly in terms of execution time.
During the construction of the primitives care was taken to
insure that all results are in the registers that initially
contain argument2. This could allow an auxiliary set of
primitives to be developed in the future to take advantage-
of the chaining of arithmetic operations. The format of the
title line and the reserve words are defined in Ross's
thesis and have not changed. ERf. 19: pp. 79-e53
Since the primitives were tested individually on a CPtI
machine prior to placing them in the library, several stages7
of collating and compromises in editing speed were made to
insure integrity of the primitive. All the code and text
associated with the primitive was kept in a single file by
primitive. To debug the primitive a header file and
trailer file was added to allow the proper assembly of each
single primitive. These three files wmre combined into the
actual test file that was assembled and debugged. All the
text that was not part of the code for the primitive but was
necessary for the operation of the primitive in the design
system was commented out in column one. Data on the
execution time of each line of code was kept as a comment
after the code. It is in the form of ;?m ??t ?b comment.
The " was the memory cycle time of the instruction. The -
43
%- ,
,...,* ', ,,... .-.-. ,,".,...,',,..,.'....'.."*.** .*- . * . %..'.*.,.,. .,....... .,..... ..........
"to was the machine cycle tie of the instruction and the
b" teas the number of ROM bytes used by the instruction.
The code format used by the design system and the z80
assembler can cause conflicts. In order to insure the
Integrity of a primitive, the entire primitive was stored in
a single file. All the text outside of the markers begin
stext and endtext is used by the design system and is not
compatible with the assembler. To keep this text from
causing assembly errors, this text was commnted out using -
the u;* The primitives when written did not have blanks in
the first five columns. Ross's program NEWCSDL. requires
that the library have a line number on each line. This can
be done by the program FIXIT however the program does not
append the program line to a line number, but rather changes
the first five columns to an appropriate line index. The
primitive had to be reformatted by adding five blanks to the
beginning of the line before sending it to the VAX. They
were run through a program that removed the U " if it
existed in the first column and stuffed five spaces in front
of all lines. The primitives were then appended together
and sent by modes to the VAX. The VAX uses a carriage
return to indicate the end of a line. When sending a file
the terminal program sands a carriage return and a line
fed, giving each line an extra linefeed. After receipt of
the file, all the line feeds added by the terminal program
had to be edited out. At this point the file is in a format
acceptable by FIXIT.
44
1. emkl~gk Fix it
Pollock expressed difficulty in trying to use Ross's
primitive format and he wrote a FORTRAN program to correct
the placement of Lntero used In the title line ERef. 20:
pp. 23-243. The problems originate in the structure of the
primitive file as designed by Mao. Each library file is
required to have an alphabetic index of all primitive title
lines. Implicit in this is the requirement to number all
the lines. Ross's format for the numbering was in the
format lvxxxxp wiere x represents the number of the line.
Within each title line there are four additional pointers,
first IWCL, first CALC9 first line of primitive and last
line of primitive. All of these pointers make any change
extremely difficult. Even simple changes require running
this program since the VAX editor creates a variable length
record f il1e and Ross' s program requires a fixed length
record file.
Pollock's program FIXIT was written to minimize the
effect of the format requirement imposed by Ross's program.
The program was written for a Cyber computer. The program
was transported here via tape, however the program did not
run due to differences in machines and program errors. The
program Is now corrected and working an a VAX 11/780. Fluch
of the program's problems were in the differences in 1/0 and
word size in the two machines. The program is now set up to
take a file of primitives named winname.datO. It produces a
file nautname.dat" of correctly formatted primitives that
45 -
~-.--.~. *-. * - - -. * ,. *.. T~-..T-.*.--. ~ - .*; 7 -- - It~ c* -
includes a sorted title directory at the beginning of the
file with pointers to the individual primitives. Without
this utility,, change to the realization would be very
tedious.
2. ROMPa MMMag
When running NEWCODL there are options to produce aso
trace by subroutine of the program execution. This Is a
very necessary utility, since the program is very complex
and sensitive to input format. The detailed trace produced
by NEWCSDL is very necessary because of the size of the
program. This became painfully obvious while trying to get
FIXIT to give an acceptable input file far the primitives.
The error messages produced by tENCUOL were incorrect due to
a format error. The carriage control has been corrected,
and the Passages are now intelligible. In using NEWCUDL
trace option in full mode, every subroutine called Is
printed to a log file along with the movement of key data.
The carriage control that was a problem in the, output of
msages was also the principal problem in the input of the
primitives. The carriage control character kept moving the
data of the input file over by one character, causing the
data to be in the wrong column. The requirement for fixed
column reads in this program precludes any editing of a
primitive file without running it through FIXIT now named
F RfIAT. The name was changed to minimize the confusion
between the various versions of the program. FOAIIAT,, in
addition to correcting any pointer inconsistencies also
46
V. V- K- -7 K
converts the file from a variable format to a fixed 80
character record format, which to the required input format
for INEkrSDL.
In writing the primitives, the desirability of a
modulo operator in the calc function became evident. The
addition of multiple boards makes this desirable in
assigning pinouts on the additional boards. Currently the
number of ports by type requested is accumulated as a
variable in SLOBALS.DAT. Ross calcit subroutine was
examined to determine if this was feasible. Currentlyp the
only primitives that could include multiple boards .are the 8
bit analog to digital primitive and the 8 bit digital to
analog primitive. Because of this limited number of boards
requiring a modulo function, a simple scratch variable and
subtraction of any values greater than the number of ports
on the board was used instead. If the number of replicated
board grows, then it may be worthwhile in the future to
change NEWCSDL to include this function.
Two additional files used by NEWCSDL are potentially
affected by new libraries. The first file MONITOR.DAT
contains primitives that are used all the time by NEWCSDL
and are included regardless of the application. Because
the intermediate table containing the order of the
contingency tasks has been eliminated, one primitive TAACP2
has been eliminated and the code in NEWCSDL needs to be
modified to eliminate the reference to that primitive. The
second file, GLOBALS.DAT, contains the names of global
47
-. .. ,. -- 7'.. .. *.* . . . .. . .* * * * * *-:-'***.
variables used by the primitive library. Because of the
change in orientation of the library from individual
components to boards, many globals were no longer needed. A
list of the global variables used with this library and
their application is given in appendix 3.
3. ftIdIuA h"M ftM In.
Walden designed a database system to eliminate the
need for the various files used in IEWCSDL. No code was
available for test at the time of the implementation of this
thesis, so no attempt was made to try inputting any of the
primitive library into a database. The method of input into
the data base specified by Walden was to type all data in at
a terminal. This is a reasonable method for the title lines
and some of the smaller files. It does not appear to be a
feasible method for entering a primitive library because of
the size of the data. A data base eliminates the need to
use the FORMAT program to correct the pointers and
eliminates same of the overhead on CALC, and INCLUDE.
However it would require typing all of the primitive's
assembly code that has been previously debuggedy with the
attendant errors and duplication of work. To be really
usable, the data base needs a method of getting the assembly
code associated with a primitive from its file used for
testing and debugging. By doing this the code could be
transferred with a minimal amount of error. The code would
still be available for separate assembly and debugging by
the primitive's author. CRef. 21]
46I'
L.%
*V. uLML_ An -.-
Preliminary results of Riley's thesis indicate that the
controller can be built using the design system. CRf. 223
This particular controller does not overly tax the design
system or the primitive librarys but does provide a
functional test.
In the course of constructing the library, integration
of the various tools became the major problem. In
constructing any library an assembler and debugger are
necessary. The Z-6O has a number of assembler programs,
however, they do not run on a VAX11/780. The transport of
the assembly file to the mainframe after construction can be
tedious. My choice was using a 300 baud modem. This was
not much of a problem when the primitives were few in
number, but became a real logistics problem as the library
neared completion.
The implementation of an interrupt driven controller has
turned out not to be desirable because of the additional
overhead. This was tried in the form of an interrupt driven
clock for the primitive library. The clock was using about
2.5Z of the monitor's available time. This required no
selection of competing interrupts3 since there was only the
single interrupt in this case. The overhead was also the
minimal possible, since only the AF and HL registers were
49
LIl
* . *::::*~. ~ **~;. *>w. .*.~~.&J2 .j:~§9 ~K.%~~K:K. -
saved. If all the primitives had the potential for
interruptp then the AF, BC, DE, HLs IX9 AF BC' DE' and HL'
would also have to be saved. For comparision, saving all .
the registers would have increased the overhead to 7.5%.
This still would not include the time necessary to select
which contingency/task pair should be executed. At this
point the interrupt driven monitor was abandoned.
Further primitives can be added to the z-80 library to
increase the number of arithmetic and control functions
available, but this may be time poorly spent. In building a
good design system a suite of libraries is necessary. The
Z-4O is the low end of the library in terms of performance
and cost. Because the costs of processors continue to fall,
it may be desirable to include the most extensive of
libraries only in higher performance chips.
50
Z:- .
APPENDIX A
PRIMITIVE TITLE INDEX
This appendix was created from the index of the .primitive title lines. Where there are multiple primitiveswith the same name, but different precisions, only one nameis listed. The function of the primitive is then brieflydescribed, and its limitations.
NAIIE FUNCTION
h.atod Include a 8 bit analog to digital conversionboard
h.cardcage Include a 8 slot card cage and power supply in -the primitive listing.
h.clock Detail the connections of the counter timer chipon the cpu board to produce a 1 millisecond or a25 millisecond clock out of channels 0 and 1.
h.dtoa Include the hardware for a 8 bit digital toanalog conversion board
h.inout Include a 8 bit 64 channel standard bus todigital i/o board with wiring to illuminate upto eight lights using the address lines on the,card
h.memary Hardware primitive to include a 16k ram boardbased on total ram and rom requirements. Thisparticular board is a battery backup board andcan also be used as a quasi rom if a writeinhibit switch is on. The board can be disabledIn 4k segments, making that particular segmentnonwriteable by the cpu.
h.processor Hardware primitive to include a Zilog Z-90a witha 4mhz clock and a three channel counter timerchip on a single board. Included also is abootstrap rom using the first 4k of addressspace.
h.tcardcage This is a primitive that is invoked when a cardslot is requested. It checks that the number ofslots requested does not exceed the numberavailable.
s.add Come in a variety of forms to support byte, twobyte and floating point addition. It provides - -
no error checking on the result of the
51
computation.
seaddck Comes in a variety of forms to support byte, twobyte and floating point addition. It provideserror checking and will not allow the result tohave an inappropriate sign. If an overflow ismade then# it will put the largest possiblevalue in the result.
s.and Perform a logical and
s.assign Performs an assignment operation.
s.assigncons Assigns a constant value to a previouslydefined variable. This does not reserve space -
for the variable, only puts a specific value inthe variable.
s.atod Primitive to perform a analog to digitalconversion
s.blockcons Primitive to mark the beginning of a submonitorblock
s.blockend Primitive to mark the end of a submonitor block
s.blockexit Primitive to leave a submanitor and reset allpending operations
s.blockstart Primitive to cause a submonitor to be executed
s.clockcons Primitive to create an interrupt driven clock
s.clockcons Primitive to create a clock using counter timerchip channels 0 and 1. No interrupt isinvolved. The accuracy of the time tick is onceevery millisecond. The time is accumulated inchannel I as a 16 bit down counter. The timecan be read by usings.rdtime. This primitive will latch the currenttime to an output buffer and subsequently inputthe latched time.
s.clockcon25 Primitive to create a clock using counter timerchip channels 0 and 1. No interrupt isinvolved. The accuarcy of the time tick is onceevery 25 milliseconds. The time is accumulatedin channel 1 as a 16 bit dawn counter. The timecan be read by using s.rdtime. This primitivewill latch the curt-ant time to an output bufferand subsequently input the latched time.
s.cold Primitive cause the system to do a cold boot*
52
* . o . . . . .. .- . . . . . . . . .- **. . .. . * . . . . . * .. . . . . . . . .
* . .* *.*, *.*. **--*..--C.
That is reinitialize all hardware and performany user directed initializations.
s.cons Define a constant. That is put a value in therom position of memory. Comes in version forbyte, two byte and floating point constants .
s.div Comes in version for byte, two byte and floatingpoint divisions.
s.dtoa Software primitive to perform an 8 bit digitalto analog conversion. O
s.end Primitive that must be last. Indicated the endof program and includes some necessary pointersfor hardware initialization.
s.eq Performs comparison of byte or word values for Pthe condition of equality and outputs booleanresult
s.every Forces execution of monitor every time by makingcondition always true.
s.exitproc "arks the end of a procedure that is executed asa subroutine. When used with a conditionalcall, this primitive will first set a booleanvariable with the same name as the procedure tofalse prior to executing a return. If it isused in conjunction with a unconditionalprocedure then it will simple execute a return.
s.float Converts a two byte variable to a floating pointvariable.
s.forend Marks end of a FOR construction
s.forstart Creates a FOR variable- date from lower toupper.
s.fptoi&ee Converts floating point format in controller toIEEE single precision format.
s.ge Performs comparison of byte or word values forthe condition of greater than or equal andoutputs boolean result
s.gt Performs comparison of byte or word values forthe condition of greater than and outputsboolean result
s.ifcons "arks to to an if construction
53
*o.. .
4 * ' S *U-...-U* -. -o* o ,
*. . . . . . . ... -,- * -
s.ifend Marks the end of an if construction
s.initalcons Marks the beginning of user definedinitialization requirements
s.initalend Marks the nd of user defined initializationrequirements. Implied in the end is setting theflag associated with the user definedinitialization to false and jumping to the topof the main monitor loop.
s, jmpf Causes a jump to a location if a variable isfalse
s.jmpt Causes a jump to a location if a variable istrue
s.le Performs comparison of byte or word values forthe condition of less than or equal and outputsboolean result
s.loc Marks a portion of a program with a label.
s.it Performs comparison of byte or word values forthe condition of less than and outputs booleanresult
s.main This construction is always required. Itinitializes some basic pointers and creates astack.
s.messout Sends a message to the output device. It isused only in the debug mode.
s.monitor Creates the top of the main polling loop andreinitializes the stack pointer
s.mult Comes in a variety of forms to support byte, twobyte and floating point multiplication. Itprovides no error checking on the result of thecomputation.
sne Performs comparison of byte or word values forthe condition of not equal and outputs booleanresult
s.not Performs a logical not.
s.or Performs a logical or
s.out Output a signal to a port.
s.perfore Primitive to invoke a procedure subroutine call.
54
....... ... .. ....... .. *.....
- .. .. %"t. " .. . . . . . . . .; .
s.proc Primitive to mark the beginning of a conditionalor unconditional subroutine call. It is used inconjunction with s.exitproc to mark the end ofthe subroutine.
s.rdtime Reads the time from the CTC chip on the cpuboard. Time is represented in eithermilliseconds or 25 milliseconds depending onwhich clock construction has been used. In bothcases the actual number read is a two bytenumber. The clock is a down counter, so thatthe elapse time goes from a negative number to apositive number to zero and then repeatsstarting with a negative number.
%.start Forces monitor execution provided forcompatability with older library. Not neededsince monitor starts at nonmaskable interruptlocation.
s.sub Comes in a variety of forms to support byte, twobyte and floating point subtraction. Itprovides no error checking on the result of thecomputation.
s.subck Comes in a variety of forms to support byte, twobyte and floating point subtraction. Itprovides error checking and will not allow theresult to have an inappropriate sign. If anoverflow is made then, it will put the largestpossible value in the result.
s.tabnd Marks the end of the main monitor polling loop.
s.tabent Put an entry in a polling loop. It is used withboth the main and submonitor loops.
s.var Defines a variable in ram
s.warm Performs a warm boot. That is jump to the topof the main polling loop, reinitialize thestack, and perform any user definedinitializations.
s.whend Mark the end of a while construction
s.whilecon Mark the beginning of a while construction.Performs the test of a condition, if false jumpsto the next instruction past the location markedby whend.
s. wrtbin Used in the debug mode to output a location to
55
. . . . .. . . . . . . .
.o . o
the screen in binary.
S. xor Perform an exclusive or.
stabaccp2 Is a dummy primitive to provide compatibilitywith the 9090 realization listing. In the 9080listing tabent is divided into two primitivestabent and tabaccp2. This requires less memoryif there are extremes in the time requirementsof different contingencies. By combining thetwo primitives an intermediate table iseliminated and the execution time is increased *
by eliminating two unconditional jumps.
56
APPENDIX B
GLOBAL VARIABLE LISTING
This appendix lists exactly the file GLOBALS.DAT underthe column name. Included in the listing are the initialvalues of the variable. Since the variables are limited tosix characters, the purpose and limitations are nor readilyapparent. The purpose of the variable and its use aredescribed in the next column.
NAME PURPOSE
arnd 0. Is a pointer in the form of "W<arnd>". Itpurpose is to allow sections of code to beplaced anywhere. This allows initializationsto be place with a primitive. In this waythe primitive can be executed and theinitialization is jumped around. The onlyway to access the initialization is to usethe inlnk chain.
chips 0. Is a count of the number of integratedcircuits that have been added.
debug 0. Is a flag that will cause the primitives tobe conditionally assembled to produce inputand output through standard BDOB calls. Thedefault is to use the normal input and outputboards. To use a cps microcomputer to testthe primitive, debug must be set to 1. Thiscan be done as an exit to the globals.datfile.
initlk0. Is a variable that is used in a pointer chainfor the initialization of hardware. Theactual form is *i<initlk>. This for thefirst link would appear as QiO the secondai 1. -
keybrdO. Is a boolean variable indicating if the 7303keyboard/display board has been requested byany primitive. This primitive was necessaryto eliminate the potential of several copiesof the board being requested by differentprimitives. There are several primitivesbecause of the number of separate functionsthat are included on the board.
natode0. Is a variable enumerating the number ofanalog to digital ports that have beenrequested. The hardware primitive will
57 *~~
• % ; 0
sT .S-0'
*0 . .,*.-.: -0~S * S 0 0* 00~
0 *~'~*.*0...00 0,
- ~ -. I I - *•. - - '
indicate a failure if the number is greaterthan 32.
natodpO. Is a variable containing the address of theI/O part. It i* initially 0. If more than16 atod ports are requested then the addressis changed to 4.
ndtoaeO. Is a variable enemurating the number ofdigital to analog ports that have beenrequested. The hardware primitive willindicate a failure if the number is greater .than 32.
ndtoapO. Is a variable containing the address of theI/0 port. Currently, not dtoa boards areavailable for the system, so the exactaddress has not been determined.
ninoutO. Is the number of inout ports that have beenrequest for the mostek mdx-diobl board. Anerror is produced it the number requestedexceeds 64. S-
nkey 0. Is a variable indicating the number of pushbutton keys that have been requested.
nled -1. Is the number of light emitting diodes that
have been requested. The maximum is eight.An error will be generated if more than eightare requested. The lights are number zerothru seven. q.
nodgt 0. Is the number of digits of the alphanumericdisplay that are requested.
norom 0. Is a flag indicating the absence of theloading rom. If the controller is to be usedwithout external support, this flag must beset to 1. This will cause the conditionalassembly to start at 6d and will allow thenormal use of interrupts. If the controlleris being simulated on a cpm computer, thisflag should be 0. The normal assembly has ajump to 4000h at 100h to accommodate the useof cpm. This does not effect the use of theloading rom, since the location lOOh can't be Laltered by the loader.
nrockrO. Is the number of rocker switches that havebeen requested for the 7303 keyboard/displayboard. Currently this is limited to twoswitches. Requesting ore than two will
58'
-.',.2-._. : "" .. f;'...,_ ,.., ,',.... . ... .. .. + .. ,. . ,+"+-..................-.........,.........................,.......-. ,..,.,. .....-
cause aerror.
raimptrO. Keeps a count an the number of bytes ofstorage that have beein requested in a RAMarea. This counter starts at zero, but willbe moved to the top of the, address space anddecremented as mermry i s requested forvariables and stack space.
ramptrO. Keeps a count on the number of bytes ofstorage that have been requested in a ROMarea. This counter starts at 0 and inincremented as instructions are added.
scrtchO. Is a scratch variable. It is used in variouswas by different primitives to computeintermediate resualts.
slot 0. Indicate the slot in the card cage that aboard will1 use. An error wil 11b generatedif more than eight cards are used.
59
:1 A
APPENDIX C
ZILOG--80 REALIZATION LISTINB
This appendix contains the listing of the library as itis required to be formatted. The first line of the librarycontains the title of the library along with the cpu's clockperiod and memory speed in quarter mircoseconds. This isfollowed by the alphabetical index of all the title lines. S
The individual primitives are listed after the index. Theformat of the individual primitive repeats the title line,has comments describing the primitive, then actual code andis unbounded until another title lines is encountered. Thismakes it possible to have multiple segments of codeinterspersed with calc statements. Not shown because it is .an extra line, is the requirement to a line after the lastline of the last primitive. If this is not included, thelast line of the last primitive will not be included, sincethe FORMAT program is looking for a last dummy primitive tomark the end of the library.
The library is listed vertically to allow the fully 80 Scolumns to be displayed.
-
* ....-.......-.. %.--.'-'.
r-r
-W CD 0M
.10 -o CcN ta- A c; li 1
T .CI . mN-t - N a. 0 - o00r. 0-00 -
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LIST OF REFEREPCER
1. "JDR Micradevices," nJ V. 9, N. 2, February 1984.
2. 01983 DP Salaries the Key Word Is Perks,"September 1993.
3. Manwaring H.o L. "A Computer-Aided Approach to theDesign of Digital System Controllers Using .Microprocessors," IMmftl Oai"C GMourWSS goCircuita tM d MLtSCs, IEEE Computer Society,November 6p 1978.
4. Ross, A. A., G9regin Afid Rei an g,Wicrmrmuar__-mud_ Gatrolljars, Ph.D. Thesis,University of California, Davis, 1976.
5. Matel an, Ff. N.qr &d", 2 kujn 2:E OAL lim-"trol ftmts, Lawrence Livermore Laboratory,December 10, 1976.
6. Ross, A. A., g gg AIdd Re sin 2:tiacrin oclar-_ a rlerfs, Ph.D. Theis,-University of California, Davis, 1978.
7. Ibid.
S. Pollock, S. 8. , ~ DMIgRJnagM t W In__aticati2nn o-GamutrzideU Rmaian at ir Aro-esrqW Vxsmv 14.S.Thesis , University of California Davis, December 1981.
- 9. Manwaringg M., L., "A Computer-Aided Approach to theDesign of Digital System Controllers UsingHicroprocesersq" Tfth ft iloWa GaftErgen 90
ircuita, ISyjas Wd G ta , IEEE Computer Society,November 6, 1978.
10. Biehl, 6., "Automatic Generation of OptimalMicrocomputer Programs for Software-Driven DigitalControllers," Ixufga ma Inc r.wutnc aicrcuroeasor Aolicati21 s, Budapest# October, 1979.
li. Sherlock, S. Ja., Uerfriendixy 8L 2=1Riratgd Input19 Ck 92alit5C AAMe ftsif ftJs , M.S. Thesis, NavalPostgraduate School, June 1983.
12. Chu, Y.9 *Concepts of a Microcomputer Design Language, "1At Mmi &s wO aa fo n MMingso IEEEComputer Societyg June 259 1979. "-
13. Hmethp J.p R.sCarrol, B., D.9 and CwIk, T., T., "An
Improved Version of COL for the Efficient Simulation of .Microprocessor and Minicomputer Systems," Jnai ofi
104
4 .
.... " - - - - - - ' ;: - " 7" - " " " " % " ";'" ". :--'.' :'-"- "-" ':"* "J": ." "-.:." _Z "- - -, ',"
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* 105
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