Implementation of Turbo Codein TI TMS320C8x

Hao Chen

Instructor: Prof. Yu Hen Hu

ECE734 Spring 2004

Turbo Codes

Shannon established the fundamental theory about the tr

ansmission rates in digital communication system The practically feasible channel utilization is almost close

d to the theory communication capacity limit;

The lower complexity of decoder is gained through two s

eparately decoder compared with one decode;

Turbo Codes play an important role in the next generatio

n communication system

Encoder of Turbo Code

Parallel concatenation convolutional codes (PCCC)

Output sequence has near uniform distribution probability with well designed interleaver.

Encoder 1

Encoder 2

Interleaver

DN, DN-1, … D5, D4, D3, D2, D1, D0

AN, An-1, … A1, A0

BN, Bn-1, …B1, B0

CN, Cn-1, … C1, C0

BN, AN, DN, Bn-1, An-1, Dn-1, … B1, A1, D1, B0, A0, D0

source information sequence

output code with code rate 1/3

BN, DN, An-1, Dn-1, … , B4, D3, A2, D2, B1, D1, A0, D0

output code with code rate 1/2

V1

V2

V3

Convolutional (RSC) Encoder

Generator matrix of a rate ½ RSC code can be defined:

1g z

G zh z

DN, DN-1, … D1, D0 AN, An-1, … A1, A0

+ ++

+ ++

+ ++

+ ++

+ ++

z-1

z-1

z-1

z-1

-h0

-h1

-h2

-h3

-h4

g0

g1

g2

g3

g4

DN, DN-1, … D1, D0 AN, An-1, … A1, A0+ + + +

+ + + +

+ + + +

+ + + +

+ + + +

g0

g1

g2

g3

g4

-h0

-h1

-h2

-h3

-h4

z-1

z-1

z-1

z-1

z-1

z-1

z-1

z-1

Viterbi Algorithm for Convolutional Code

00

01

10

110/00

1/11

0/01

( Ai-2 Ai-1)

(Ai / AiDi)

1/10

0/00

0/011/10 1/11

t=1 t=2 t=3 t=4 t=5 t=6At-2 At-1

00

01

10

11

0/00

1/11

1/10

0/01

t t+1At-1 At

(1) 00 P(1,t) S(1,t)

(4) 11 P(4,t) S(4,t)

(2) 01 P(2,t) S(2,t)

(3) 10 P(3,t) S(3,t)

P(i,t) : The min cost when the

state is i at the time t.

S(i, t): The path from time 1 to t

corresponding to the P(i,t).

A Posteriori Probability Algorithm (APP)

Minimize the symbol error probability

The code is decided by the log-likelihood ratio

Original infromation at time t

1

1

1|log

0 |

Tt

t Tt

P D LD

P D L

1 0

0t

t

DD

otherwise

1TL : The received sequence from time 1 to time T

Iterative algorithm of Turbo Code

Decoder 1

Decoder 2

BN, AN, DN, Bn-1, An-1, Dn-1, … B1, A1, D1, B0, A0, D0

output code with code rate 1/3

DN, DN-1, … D1, D0

AN, An-1, … A1, A0

BN, Bn-1, …B1, B0

Interleaver

InterleaverDeinterleaver

Decodedinformation sequence

priori probability of information sequence

priori probabilityof information

sequence

1 tD

2 tD

Two component decoders serially concatenated via an interleaver

The priori probabilities obtained from first decoder is used at the second decoder

Iterative algorithm of Turbo Code Use priori information to caculate

Forward recursion: t=1, 2, …, T

Backward recursion: t=T, T-1, …, 2, 1

log-likelihood ratio

1, , |tt t t ti m P D i L S m

1 1 10,1

, , ,t t t t ti

m M i m i M i m

1 1 10,1

, ,t t t ti

m M i m i m

1 11

1 11

1, 1,log

0, 0,

state

state

M

t t t tm

t M

t t t tm

m m M mD

m m M m

Implementation in TMS320C8x

Modify the algorithm to save memory

Apply two decoders in one DSP; (time share)

Map the algorithm to utility multiprocessor of

TMS320C8x more efficiently;

Memory location analysis

Decoder1BN, AN, DN, … B1, A1, D1, B0, A0, D0 AN, An-1, … A1, A0

BN, Bn-1, …B1, B0

,t i mTMS320C8

DN, DN-1, … D1, D0

BN, …B1, B0

2*T*MstateFP data

T FP data

DN, … D1, D0 T FP data

Step 1: Receive the code sequence; get the for decoder1. ,t i m

Memory location analysis

Decoder1Decoder1

t m t m

Decoder1

,t i mTMS320C8

2*T*MstateFP dataDecoder2

,t i m2*T*MstateFP data

Decoder1

,t i m 2*T*MstateFP data

T*MstateFP data

T*MstateFP data

Step 4: Calcualte of decoder 1 with t m t m ,t i m

Implement forward recursion

Map forward recursion to four parallel processors of

TMS320C8x

No additional memory is needed to store temporary

valuei-1 i i+1At-2 At-1

00

01

10

11

m

1

2

3

4

t

. . . . . . . . . . . .

PP 1

PP 2

PP 3

PP 4

D

D

D

D

D

D D

D

1i 1 1i

1 2i

1 3i

1 4i

2i

3i

4i

1 1i

1 2i

1 3i

1 4i

1 11 , 1 , 1i i i

output

1 12 , 2 , 2i i i

1 13 , 3 , 3i i i

1 14 , 4 , 4i i i