Implementation of Silicon Track Card (STC) as a

System-On-a-Programmable-Chip (SOPC)

Presentation by Arvindh Lalam and Dr. Reginald PerryDepartment of Electrical and Computer Engineering

Florida A&M University – Florida State University

College of Engineering

IEEE SoutheastCon 2002SEC 143

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

ExampleSilicon Track Card (STC) for the DZERO Experiment:

The DZERO Experiment is conducted at Fermi National Acceleration Laboratory.

In the D0 experiment a proton –

anti proton are made to collide after high acceleration in the TeVatron accelerator.

The TeVatron Accelerator

Overview

Physicists examine the results from the collisions in an attempt to understand the fundamental nature of matter.

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Example:Problem StatementEach “experiment” generates billions of collisions. How do you only collect data from collisions of “interest.”

Dzero Detector

http://www.fnal.gov

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Example :Conceptualization

roaddata

SMTdata

SiliconTriggerCard

SiliconTriggerCard

SiliconTriggerCard

SiliconTriggerCard

SiliconTriggerCard

FiberRoadCard

SiliconTriggerCard

TrackFit

Card

Few s Tim

e Budget

L2

DZERO

CFT

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

D0 Trigger

L1 Framework

L1CAL

L1CFT

L1Muon

L1FPD

CAL

FPS/CPS

CFT

SMT

Muon

FPD

L2Cal

L2Ps

L2Muon

L2STT

L2CFT

Level 3L2Global

Trigger

Detector

Level2Level 1

SMT

L2CTT

preprocess SMT datafind clusters

associate clusters with L1CTT tracks

fit trajectories

L1CTT

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

The Level_2 STT

SMT

L2CTT

preprocess SMT datafind clusters

associate clusters with L1CTT tracks

fit trajectories

L1CTTSTC

TFC

FRC

L3

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

D0 Trigger -

CFT A Layer

CFT H Layer2 mm road

centroids

“clusters” : Groups of strips.

SMT Layers“Si” strips

“centroid”: Centroid of a cluster.

“road” : Track information translated for the STC.

“hit” : A centroid that falls in a road.

hits

STC

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

STC - Functionality Reformats received “strip” data. Finds “Clusters” and their “centroids”. Identifies “hits”. Stores required data for debugging. Implements a Bus Arbitration scheme. Operates at 33 MHz.

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

STC - Main Data Path

Control Lines Main Control

Data Lines

Handshake Signals

Control Lines

Downloaded Parameters

Data from the main controller

Roads from FRC Hit Filter

Hits

L3 FiFos To L3

Strip Reader

SMT Data

Centroid Finder

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Centroid Finder Algorithm

0

5

10

15

20

25

30

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

0

5

10

15

20

25

30

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33

0

5

10

15

20

25

30

1 3 5 7 9

11 13 15 17 19 21 23 25 27 29 31 33

=cluster center

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Example Centroid Finder

To Hit Filter:

16..15 14..13 12..2 1..0

Data type Pulse Area Centriod Precision bits

Cluster Finder

Centroid Calculator

ToL3 Buffer

FromStrip reader

To Hit filter

Data frommemory

FIFO

To Hit filter

22..21 20 19 18..11 10..7 6..0

Data type

New data bit

End of data

Data Chip Id Strip number

From Strip Reader:

Data Streams

23 17

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VHDL Codeentity cluster_finder is

port( data_in: in unsigned(22 downto 0); -- input data word from fifo

data_threshold_1,data_threshold_2: in unsigned(7 downto 0); -- read as inputs

cluster_type: in unsigned(0 downto 0); -- use 3 or 5 strips in scalculation

800+ lines later

end behavior;

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Programmable Logic Devices (FPLDs)

Re-programmable Logic devices. Eg: CPLDs, FPGAs, FPLDS

Altera FLEX 10KE

Fast Prototyping, Fast turnaround time. STC previously used CPLDs.

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

System-On-a-Programmable-Chip (SOPC) Discrete PCB components? SOPC

Altera APEX II EP2A90 7M gates: 1.5Mbits

SRAM Xylinx Virtex E XC2V10000

10M gates: 3.4 Mbits SRAM

Altera APEX 20KE EP20K600EBC652-1X Accommodates 1 STC

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

STC - Prototype Testing Board

Control LogicBU

Silicon Track CardFAMU-FSU COE

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STC Waveforms - Hit readout

Write Signals‘HR_WR0’ & ‘HR_WR1’

Contains header & footer

STC0 : 7 hits

STC1 : 2 hits

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STC - ResourcesDevice Family

Chip Logic Elements

Memory bits

Pins

FLEX

(CPLD)

EPF10K100EBC356-1

4,340 (83%) 10,532 (21%) 257 (94%)

EPF10K200EGC599-1

2,941 (29%) 79,424 (80%) 466 (99%)

EFF10K200SFC484-1

1,860 (18%) 10,692 (10%) 292 (79%)

Total 9,141 100,648 1,015

APEX

(SOPC)

EP20K600EBC 652-1X

6,744 (27%) 105,828 (33%) 262 (53%)

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Conclusions

STC functionality successfully tested.

Circuit operational at 33 MHz.

Contention scheme for multiple channels successfully tested.

Successfully integrated STC in a SOPC.

FAMU-FSU College of EngineeringDepartment of Electrical and Computer Engineering

Acknowledgements National Science Foundation and the US Department of

Energy. Boston University

Faculty: Heintz, Narain, Popkov Engineers: Earle, Hazen Students: Zabi

Florida State University – Physics Faculty: Adams, Prosper, Wahl Postdocs: Tentindo-Repond

Florida A&M University – Florida State University COE Faculty: Perry Students: Lalam, Lolage, Meyers, Roper, Saunders

Altera, Aldec, Synopsys