impact and modeling of anti-pad array on power delivery system
DESCRIPTION
Impact and Modeling of Anti-Pad Array on Power Delivery System. Zhiping Yang 1 , Jin Zhao 2 , Sergio Camerlo 1 , Jiayuan Fang 2 1 SVS Signal Integrity & Packaging Design Group, Cisco System, Inc. San Jose, CA 95134 Tel: (408) 525-5690, Fax: (408) 525-5690, Email: [email protected] - PowerPoint PPT PresentationTRANSCRIPT
Impact and Modeling of Anti-Pad Array on
Power Delivery System
Zhiping Yang1, Jin Zhao2, Sergio Camerlo1, Jiayuan Fang2
1 SVS Signal Integrity & Packaging Design Group, Cisco System, Inc. San Jose, CA 95134
Tel: (408) 525-5690, Fax: (408) 525-5690, Email: [email protected]
2 Sigrity, Inc. Santa Clara, CA 95051
Tel: (408) 260-9344 x 104, Fax: (408) 260-9342, Email: [email protected]
EPEP 2003October 27 - 29, 2003
Westin PrincetonPrinceton, New Jersey
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Content
• Anti-pad array and its effects
• Test card structure and lab measurement setting and results
• 3D EM model extraction
• Board level modeling and simulation
• Correlation between simulation and measurement
• Conclusions and future work
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Anti-pad Array and Its Effects• Several thousands passing through vias on a typical CISCO board
• Most of the vias are located right under the BGA ASICs with regular pattern
• No commercial EDA software available for studying the effects of anti-pad array at system/board level
• Anti-pad array will impact signal transmitted and power supply system performance
Our intuition suggests that the plane inductance and resistance will increase because of the reduction of the current flowing capacity; and that cell capacitance will vary due to the change in effective area and also due to the via structures that are passing through the anti-pad array.
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Test Card Structure
Layer 24.0 mil FR4
Layer 1
Layer 11
Layer 15
Layer 16
4.7 mil FR4
21.0 mil FR4
4.7 mil FR4
Layer 3
Total thickness=93 mils
Test Card StackupTest card without
anti-pad arrayTest card with anti-pad array
Probe Location Probe Location
Two cases: open caseshort case (shorting at locations)
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Lab Measurement
Probe settingLocal ground pin
Local power pin
Probe 2 Probe 1
Probe setting detail
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Lab Measurement Results (Open Case)
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Lab Measurement Results (Short Case)
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Observations from Lab Measurement Results
• From the measurement results, it is obvious that the anti-pad array exhibits different impedance and resonance impact on 4 mils and 21 mils structures.
• For the structure with 4 mils plane separation, the impedance has been raised by 10% to 30%.
• For the structure with 21 mils plane separation, the resonant frequency has been shifted downward several tenths of MHz to 100MHz.
• According to the measurement results, ignoring the impact of anti-pad array at the design stage could lead to a weakened power delivery system.
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3D EM Field Solver Model Extraction
Solid planes One anti-pad Two anti-pads
One anti-pad with a passing through via
Two anti-pads with a passing through via
Two port S-parameter has been calculated for different structures.
A k factor has been defined as
planes Solid
via through passing a with pads-anti Two,,, ,,,
,,,
CGLR
CGLRk CGLR
Computations were performed using Ansoft HFSSTM
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Computed KR Factor
4 mils plane separation
KR_4mils = 2.3
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Computed KL Factor
4 mils plane separation
KL_4mils = 1.815
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Computed KG Factor
4 mils plane separation
KG_4mils = 0.714
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Computed KC Factor
4 mils plane separation
KC_4mils = 0.729
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Computed KR Factor
21 mils plane separation
KR_4mils = 3.15
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Computed KL Factor
KL_4mils = 1.197
21 mils plane separation
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Computed KG Factor
KG_4mils = 1.260
21 mils plane separation
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Computed KC Factor
KC_4mils = 1.337
21 mils plane separation
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K Factor SummaryKR KL KG KC
4 mils plane separation 2.30 1.850 0.714 0.729
21 mils plane separation 3.15 1.197 1.260 1.337
• The table above lists the k factors that were used in simulation for both structures with 4 mils and 21 mils plane separations.
• The inductance and resistance always increase with the anti-pad array existing on the plane for both 4 mils and 21 mils structures.
• The capacitance and admittance will be reduced for the 4 mils structure, but will increase for the 21 mils structure.
• The k factor remains constant for a reasonably broad frequency range.
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Board Level Simulation Setting
• k factors are calculated by using Ansoft HFSSTM 3D EM field solver.
• The RLGC parameters adjustment is only for the area where the anti-pad array is located on the PCB.
• This approach was successfully applied into Sigrity SPEED2000TM.
• Simulation results were compared with measurement results.
RLGC parameter adjusted area
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Simulation Results vs. Measurement Results
Short Case without Anti-pad array
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Simulation Results vs. Measurement Results
Short Case with Anti-pad array
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Simulation Results vs. Measurement Results
Open Case without Anti-pad array
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Simulation Results vs. Measurement Results
Open Case with Anti-pad array
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Conclusions and Future Work
• An effective approach for accurate consideration of anti-pad array impact on the power and ground planes is presented.
• Simulation and measurement comparison indicates that this approach is valid and the impact of the anti-pad array on the power delivery system has been captured up to several GHz.
• A frequency dependent k factor may improve the model accuracy for high frequency applications.