Approved for public release; distribution is unlimited 36th GOMACTech Conference, March 2011, Orlando, Fl

Imaging Integrated Circuits with X-ray Microscopy Michael Bajuraa, Greg Bovermana, John Tana, Gene Wagenbretha, Craig Milo Rogersa,

Michael Feserb, Juana Rudatib, Andrei Tkachukb, Stephen Aylwardc, Patrick Reynoldsc

aUniversity of Southern California, Information Sciences Institute, 4676 Admirality Way #1001, Marina Del Rey, CA 90292 USA

bXradia, Inc., 4385 Hopyard Rd. #100, Pleasanton, CA 94588 USA cKitware, Inc. 101 East Weaver St., Carrboro, NC 27510 USA

Abstract: We introduce x-ray microscopy as a method for imaging integrated circuits. Compared to physical de-layering combined with scanning electron microscopy, this method is non-destructive, requiring only sample thinning to approximately 100 um but otherwise leaving the sample intact. Using multiple views and 3D tomography, individual integrated circuit layers can be imaged. Current imaging resolution is approximately 30 nm, and is constantly improving with advances in nano-fabrication for hard x-ray optics.

Keywords: Trust; x-ray microscopy; reverse engineering

Introduction Because of the need for trusted integrated circuits (ICs) in electronic systems and the difficulty of finding trusted sources for leading-edge ICs, it has been proposed that ICs could be procured from un-trusted sources and inspected to ensure a supply of trusted ICs for critical applications. Since it is impractical to discover potentially harmful circuits in an IC by electrical testing alone, physical inspection is required to completely determine circuit structure. This work describes an approach for IC imaging using hard x-ray microscopy, which we have used to non-destructively image 90 nm technology test chips which have been thinned to 100 um. Our challenge was to develop an automated imaging method capable of scanning a large IC fast enough to make it a practical inspection method. By varying the x-ray imaging energy with a tunable source, the technique shows some sensitivity to circuit structures such as gate and active areas in addition to back end wiring interconnect layers.

Comparison of Imaging Modalities Table 1 below summarizes the capabilities of different imaging modalities. Optical methods lack the resolution to effectively image deep submicron ICs, while electron-based methods (SEM, TEM) have the needed resolution but require physically destructive sample preparation. Destructive sample preparation can be a concern if there are only a limited number of devices available for testing, since there are no do-overs after a physical delayering process. X-ray microscopy addresses these concerns, and has the potential to leave a circuit operational after

scanning depending on the circuits radiation tolerance properties. Compared to SEM approaches, the current resolution of x-ray microscopy is lower, currently around 30 nm, compared to sub-nanometer resolution possible with SEM. However the imaging resolution of x-ray microscopy has been on a Moores Law like path related to the ability to fabricate the zone plate nano-structures required to focus x-rays. This trend is depicted in Figure 1 below, for both hard (greater than 1 keV photon energy) and soft (less than 1 keV photon energy) x-rays. Over time, this trend is expected to continue to the single-digit nanometer resolution range2.

X-ray Microscope Description A high-level schematic of an x-ray microscope is presented at the top of Figure 2. A picture of a microscope constructed atop an optical table is shown in Figure 3. The x-ray microscope consists of two focusing elements similar to a light microscope. An elliptical condenser refocuses light from an x-ray source onto the sample. After passing through the sample, x-rays are focused onto a scintillator with a diffractive zone plate, and then imaged with a cooled CCD camera. The x-ray optics are key to the microscopes operation: Without them, it would be very difficult to produce sub-micron resolution images, because of the miniscule dimensions of the point x-ray source which would be required. To scan a sample, it is mounted onto a motorized stage and calibrated. A control computer moves the stage to the required positions, sets the exposure times and saves images from the CCD camera to disk. The requirement of the zone plate for monochromatic (or near-monochromatic) light for crisp focusing constrains the imaging throughput. A high-brightness source suited to the specific optical input requirements of the microscope is needed to produce images in a timely matter. Tunability of the x-ray source is desirable to perform elemental scans across specific x-ray absorption edges. The current source of choice is a synchrotron x-ray source, however compact high-flux x-ray sources are a growing and active research area3.

Approved for public release; distribution is unlimited 36th GOMACTech Conference, March 2011, Orlando, Fl

Processing Raw Images into IC Layers Raw x-ray images of a 90 nm IC with viewing angles of normal and 45-degrees are presented in Figure 4 and Figure 5. With a field-of-view of just over 30 um, and a depth-of-focus of approximately 40 um, it is possible to view a significant amount of circuitry in a single image. At normal view, much of the circuitry appears self-evident with an approximately 3% darkening, or absorption, for every metal wire structure imaged. However a single normal view cannot discern depth. Attempting to view the IC at an angle as in Figure 5 is confusing because of the metal fill structures added during the ICs manufacturing process. Computed tomography is needed to combine views of an IC from different angles to determine the structure on each layer. While the mathematics of computed tomography with filtered backprojection are well-known, the challenge of performing an accurate 3D reconstruction is aligning all the images of the chip before processing. The stated mechanical uncertainty of the sample positioning stage is a few microns, while the wiring structures present can be 100 nm or less in width. This means that image registration methods must be used to align the input images for final positioning instead of the mechanical stage. This process is depicted in Figure 2 where a mosaic scan for each imaging angle of the chip is assembled, registered, and converted into a 3D volume dataset with computed tomography mathematics. Once the 3D volume is formed, the next challenge is orienting and identifying images of individual IC layers corresponding to layers in a Computer-Aided-Design (CAD) file. Orientation is a challenge because of uncertainties in the sample stage and sample mounting on the order of milliradians which can cause the slicing algorithm to skew- sample across multiple IC layers. Similarly layer identification is a challenge due to variance in the stated manufacturing thicknesses and horizontal alignment of layers relative to each other.

Layer Imaging Detail Figure 6 depicts the quality of images formed by slicing the 3D data volume at the right layers. The contact layer is resolved into substrate and poly-contacts, and the metal layers bear a striking resemblance to their CAD file counterparts. Figure 7 and Figure 8 show exploratory images of the poly and active layers formed by tuning the x-ray microscope to specific x-ray energies and repeating the 3D reconstruction

algorithms described above. For reference the associated CAD file images for these chip areas are shown. While the contact layer complicates these images, the image response to the target layers is visible.

Conclusions and Future Work We have demonstrated an early, new technology for imaging integrated circuits with x-rays instead of electrons, on a scale of automation and accuracy which did not exist prior to our effort. As higher resolution zone plates are developed with new nano-lithographic methods, and new compact tunable x-ray sources are developed, we expect this to be a viable technology for critical needs in the future.

Acknowledgements This work was sponsored by Defense Advanced Research Projects Agency Microsystems Technology Office (MTO). Program Enhancing trust with X-ray Phase-Optimized Scanning Equipment (EXPOSE) ARPA Order No. X040/07 Program Code: 7720 Issued by DARPA/CMO under Contract No. HR0011-07-C-0102. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the Defense Advanced Research Projects Agency or the U.S. Government. Special thanks also to the support of Stanford / SSRL including Piero Pianetta, Joy Hayter, and Sean Brennan who spent many hours assisting with our experimental setup.

References 1. Tkachuk, A., Feser, M., Cui, H., Duewer, F., Chang,

H., Yun, W., High-Resolution X-ray Tomography Using Laboratory Sources, Developments in X-Ray Tomography V, edited by Ulrich Bonse, Proc. of SPIE Vol. 6318, 63181D, (2006)

2. Yun, W., Feser, M., Lyon, A., Duewer, F., Wang, Y., Pathways to sub-10 nm Xray Imaging Using Zone Plate Lens,, Design and Microfabrication of Novel X-Ray Optics II, edited by Anatoly A. Snigirev, Derrick C. Mancini, Proceedings of SPIE Vol. 5539 (SPIE, Bellingham, WA, 2004)

3. Advanced X-Ray integrated Sources (AXiS),DARPA Broad Agency Announcement , DARPA-BAA-11-11, November 22, 2010.

Approved for public release; distribution is unlimited 36th GOMACTech Conference, March 2011, Orlando, Fl

Table 1 Comparison of Imaging Modalities

Figure 1 Historical Trend for Imaging Resolution

Figure 2 X-ray Inspection Flowchart

Figure 3 X-ray Microscope at Stanford / SSRL

Figure 4 Normal View of 90 nm Integrated Circuit

Figure 5 45-Degree View of 90 nm Integrated Circuit

Approved for public release; distribution is unlimited 36th GOMACTech Conference, March 2011, Orlando, Fl

Figure 6 Imaging on Individual Wiring Layers

Figure 7 Gate Layer Imaging and Comparison with

CAD File

Figure 8 Active Layer Imaging and Comparison with

CAD File