9/25/09

CS250 Section 5Yunsup Lee

Image Courtesy www.compaq.com

Announcements

! Lab 3: ASIC Implementation of a Two-Stage SMIPSv2 Processor is out! Lab 3 due on October 6th (Tuesday) before class! Four late days you can use (including the days you have used)

! Tutorial 6: Automatic Place and Route using Synopsys IC Compiler! Tutorial 7: Power Analysis using Synopsys VCS and PrimeTime PX! Tutorial 8: Pushing SRAM Blocks through CS250’s Toolflow

! Uses SRAM32x512 example! Still working on it! Go ahead and take a look at ~cs250/examples/v-sram32x512

! Project Proposal Due on October 8th (Thursday)

Common Questions 1

! I can’t meet timing during synthesis. What should I do?! Take a look at critical path, and take a look at the gate-level netlist

! Look at the hierarchy view in Design Vision! Try to use some “magic” options for synthesis

! Normally, this wouldn’t help that much! Think hard! You need to come up with a different implementation

Common Questions 2

! I pass RTL simulation, but when I synthesize my design, gate-level

simulation doesn’t pass. What should I do?! First, clock your test harness a little bit slower.

! Negative slack doesn’t mean that your design is wrong. It

means that your design cannot be clocked at that speed! Second, try to add “+define+functional” to your VCS command

line. Re-run simulation.! Third, relax your time constraint in synthesis. Re-run simulation.! Finally, constrain your design a little bit tighter and re-run

simulation.

Common Questions 2

Branch

CondGen

Reg

FileInstruction Mem

Data

Mem

branch

pc+4

jump

jr

rd0

rd1

ir[15:0]

ir[25:0]

ir[25:21]

ir[20:16]

ir[10:6] (shamt)

ir[15:0]

ir[15:0]

Reg

File

neg?

eq?

zero?

va

l

rw

ir[1

5:1

1]

ir[2

0:1

6]

31

rf_wen

wa_sel

DecoderControl

Signals

Execute StageFetch Stage

ALU

IR

PC+4

+4

wdata

addr rdata

testr

ig_

fro

mh

ost

16

wb

_se

l

kill

F

tohost

va

l nop

pc_

se

l

tohost_en

testrig_tohost

alu

_fu

n

Sign

PC

Extend

Zero

Extend

Jump

TargGen

Branch

TargGen

Common Questions 3

! Do we need to implement MFC0?! MFC0 is used to communicate with the host interactively.! You might have noticed that assembly tests and C benchmarks

don’t use MFC0.! No need to implement MFC0.

Common Questions 4

! MTC0 $reg, $21 vs MTC0 $reg, $10. What’s the difference?! Coprocessor $10 is used to signal the test harness about start/end

recording statistics! In order to get more accurate measures of IPC! No need to implement this.

! Coprocessor $21 is used to signal the test harness about halting

execution! Notice that I added SET_STATS to the benchmarks

Common Questions 5

! Can we use different options for tools? For example, can we specify

different options for compile_ultra?! Yes! You should definitely look into the manuals and figure out

what options might benefit you.! Manuals are located in the course locker ~cs250/docs/manuals

Questions

! Any questions on Lab 2 or any tools?

Lab 3: SMIPSv2 Core

Dual Port

imemreq_bits_addr

imemreq_val

imemresp_bits_data

dmemreq_bits_rw

dmemreq_bits_addr

dmemreq_bits_data

dmemreq_val

dmemresp_bits_data

~clk

reset

smipsProc 32x1024

SRAM

clk

reset_ext

clk

reset

smipsTestHarness

smipsCore

testrig_tohost

testrig_fromhost

Lab 3: Revised SMIPSv2 Datapath

Branch

CondGen

Reg

File

Data

Mem

branch

pc+4

jump

jr

rd0

rd1

ir[15:0]

ir[25:0]

ir[25:21]

ir[20:16]

ir[10:6] (shamt)

ir[15:0]

ir[15:0]

Reg

File

neg?

eq?

zero?

va

l

rw

ir[1

5:1

1]

ir[2

0:1

6]

31

rf_wen

wa_sel

DecoderControl

Signals

Execute StageFetch Stage

Instruction Mem ALU

IR

PC+4

+4

wdata

addr rdata

testr

ig_

fro

mh

ost

16

wb

_se

l

kill

F

tohost

va

l nop

pc_

se

l

tohost_en

testrig_tohost

alu

_fu

n

Sign

PC

Extend

Zero

Extend

Jump

TargGen

Branch

TargGen

Synchronous RAM

SRAM 32x128

512 Bytes

2 Kbits

A1[6:0]

I1[31:0] O1[31:0]

CE1,WEB1,OEB1,CSB1

A2[6:0]

I2[31:0] O2[31:0]

CE2,WEB2,OEB2,CSB2

Synchronous RAM

! A1[6:0], I1[31:0], O1[31:0], A2[6:0], I2[31:0], O2[31:0] are not grouped! Use a wrapper module! Go ahead and use the SRAM32x128.wrap.v included in ~cs250/

examples/v-sram32x512

How do we make 32x512 SRAM?

32x128

32x128

32x128

32x128

O1[31:0]

O2[31:0]

A1[8:0]

I1[31:0]

A2[8:0]

I2[31:0]

CE1,WEB1,OEB1,CSB1

CE2,WEB2,OEB2,CSB2

How do we make 32x512 SRAM?

! Take a look at ~cs250/examples/v-sram32x512! Go through simulation, synthesis, place and route, and power

analysis

Lab 3: Things you need to do

! For Lab 3, you are to use a 32x1024 SRAM block! You have two projects for Lab 3

! ~cs250/lab3/v-sram32x1024! ~cs250/lab3/v-smipsv2-2stage

! Finish v-sram32x1024 project first! Go through simulation, synthesis, place and route, and power

analysis! Then start v-smipsv2-2stage project

! Copy your processor design from lab 2 and make changes! ~cs250/lab2.solution will be posted September 28th (Monday)

Lab 3: Things you need to do

! Stuff you are going to go through! vcs-sim-rtl! dc-syn! vcs-sim-gl-syn! icc-par! vcs-sim-gl-par! pt-pwr

! Important metric for Lab 3! Energy / Instruction! Area is not a concern

! We will post results on the course homepage

Lab 3: Things you need to do

! Analytic Energy Model! Power results come from pt-pwr! Total Energy = Power * Target Time! Energy/Instruction = Total Energy / # of instructions executed

! Calculate Energy/Instruction for each assembly tests! Figure out the instruction mix of a given benchmark

! Ideally now you can calculate the total energy from the calculated

energy/instruction from the previous bullet! What might be wrong? How can we fix this?

Lab 3: Things you need to do

! Come up with some micro-benchmarks to get more accurate energy/

instruction for individual instructions! Commit your micro-benchmarks to your local “smips-tests”

! Run it through the benchmarks provided and the benchmarks you

wrote for Lab 2

Lab 3: Be careful

! New format for programs - BVMH (Banked VMH)! For Lab 3, a script divides the program into 8 chunks! Source files can be found at:

! ~cs250/smips-tests-bvmh! ~cs250/smips-bmarks-bvmh

! Installed version can be found at:! ~cs250/install/smips-tests-bvmh! ~cs250/install/smips-bmarks-bvmh

Lab 3: Be careful

! Memory is a very limited resource (only 4KB)! Program starts at 0x000 rather than 0x1000! Benchmark dataset sizes have changed! Stack pointer starts at 0xFFC and grows toward 0x000! 0x1000 wraps around to 0x000

Lab 3: Screenshot