ijcsmc, vol. 5, issue. 8, august 2016, pg.187 …in order then it is called multi carrier based pwm...

M. Narendra Kumar et al, International Journal of Computer Science and Mobile Computing, Vol.5 Issue.8, August- 2016, pg. 187-198

© 2016, IJCSMC All Rights Reserved 187

Available Online at www.ijcsmc.com

International Journal of Computer Science and Mobile Computing

A Monthly Journal of Computer Science and Information Technology

ISSN 2320–088X IMPACT FACTOR: 5.258

IJCSMC, Vol. 5, Issue. 8, August 2016, pg.187 – 198

DESIGN AND SIMULATION OF NESTED

MULTILEVEL TOPOLOGIES

M. Narendra Kumar, Y. Ravindranath Tagore

M.Tech, Student Associate Professor VLITS, Vadlamudi. VLITS, Vadlamudi.

[email protected] [email protected]

Abstract- This project deals with design and simulation of multilevel topology based on the concept of nested

arrangement. It has the advantages of reduced number of diodes and consequently gives higher efficiency as compared to

the equivalent neutral point clamped inverter (NPC) topology. This method presents an optimized pulse width modulation

strategy that provides synthesizing voltage waveforms with higher quality, and losses comparison with NPC topology. The

simulation of Nested multilevel topology is to be done for 4, 5&6 levels and performance is to be compared in terms of

total harmonic distortion (THD). Also, the PMSM motor is to be fed with this nested multilevel converter with different

output voltage levels and performance comparison is to be accomplished in terms of torque ripples. The simulation is

performed using MATLAB/Simulink software.

Keywords- DC-AC power converters, multi-level inverters, power electronics, pulse width modulation technique,

permanent magnet synchronous motor.

I. INTRODUCTION A multilevel converter [3] not only achieves high power ratings, but also enables the use of renewable energy sources.

Renewable energy sources such as photovoltaic, wind, and fuel cells can be easily interfaced to a multilevel converter system

for a high power application. The concept of multilevel converters has been introduced since 1975. The term multilevel

began with the three-level converter. Subsequently, several multilevel converter topologies have been developed. However,

the elementary concept of a multilevel converter to achieve higher power is to use a series of power semiconductor switches

with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform.

Capacitors, batteries, and renewable energy voltage sources can be used as the multiple dc voltage sources. The commutation

of the power switches aggregate these multiple dc sources in order to achieve high voltage at the output; however, the rated

voltage of the power semiconductor switches depends only upon the rating of the dc voltage sources to which they are

connected. A multilevel converter has several advantages over a conventional two-level converter that uses high switching

frequency pulse width modulation (PWM). The attractive features of a multilevel converter can be briefly summarized as follows.

● Staircase waveform quality: Multilevel converters [2] not only can generate the output voltages with very low distortion,

but also can reduce the dv/dt stresses; therefore electromagnetic compatibility (EMC) problems can be reduced.



● Common-mode (CM) voltage: Multilevel converters[9] produce smaller CM voltage; therefore, the stress in the bearings

of a motor connected to a multilevel motor drive can be reduced. Furthermore, CM voltage can be eliminated by using

advanced modulation strategies such as that proposed in.

● Input current: Multilevel converters[14] can draw input current with low distortion.

● Switching frequency: Multilevel converters[7] can operate at both fundamental switching frequency and high switching

frequency PWM. It should be noted that lower switching frequency usually means lower switching loss and higher efficiency.

Unfortunately, multilevel converters do have some disadvantages. One particular disadvantage is the greater number of

power semiconductor switches needed. Although lower voltage rated switches can be utilized in a multilevel converter[8],

each switch requires a related gate drive circuit. This may cause the overall system to be more expensive and complex.

Multilevel inverters[9] give higher power. They are operated through multiple switches instead of one. They can use

environmental friendly energies like wind and solar energy and convert them to AC.

When compared with an induction servo motor, a PMSM also has many advantages. For instance, it has

the higher efficiency, resulting from the absence of rotor losses and lower no-load current below the rated speed. In addition,

its decoupling control performance is far less sensitive to the parameter variations of the motor. To achieve fast four-quadrant

operation, smooth starting, and acceleration, the field oriented control, or vector control, is used in the design of the PMSM

drive. Much research has devoted fresh attention to the control of the PMSM

Multilevel Converters[2] has been attracted a large interest in the power industry in the recent years. Industry has started to

involve in higher power equipment, which already reaches megawatt level. Conventional power electronic converters are

only able to switch each individual output link between two possible voltage levels, especially those of the internal DC

voltage link. The general structure of the multilevel converter[8] is to generate a sinusoidal voltage from several levels of

voltages which are usually obtained from capacitor voltage sources.

Three different topologies have been projected for multilevel converters:

Diode clamped converter;

Flying capacitor converter (Capacitor Clamped)

Cascaded converter.

This paper investigates multilevel topologies[2] based on the concept of nested arrangement. Such topologies are called

nested multilevel converters[15] because the central point of the legs are connected at the same point, with the external

leg involving the internal one, as observed in Fig. 1. Fig. 1(a)–(c) shows the nested multilevel configuration with four,

five & six levels

An auxiliary resonant pole is applied through the nested three and five leve[19-21]. This nested multilevel topologies is

applied four level to n level. When compared to NPC topologies, the studied configurations can be considered as an

interesting option for applications that demand a number of levels higher than or equal to four, since as far as the number of

levels increase higher is the reduction on the number of diodes employed. This paper also PMSM motor is to be fed with this

nested multilevel converter with different output voltage levels and performance comparison is to be accomplished in terms

of speed and torque ripples.

(a)



The effort in semiconductor cost is 550kVA, compared with 630kVA for the Neutral Point Clamped topology[1], but the

components of the NPC[4] will stay cooler so that they could be used at higher currents. In a comparison of maximum output

power at 16kHz, the NPC module will be lower in cost than the module for a standard half-bridge. but with the need for a

total semiconductor rating of 810kVA compared to 630kVA. Efficiency is becoming increasingly important in power

electronics. Many applications are driven by the initiatives for reduced energy consumption. The technology leaders are

inverter applications in the solar market, but also uninterruptible power supplies and motor drives have new targets for

improved efficiency.

(b)

(c)

Fig. 1. Nested multilevel configurations with (a) four level, (b) five level, and (c) six level.

II. CONVERTER DESCRIPTION

Each converter’s leg in Fig. 1(a) is constituted of two controlled switches (Sx1andSx4) and two bidirectional controlled switches (Sx2 and Sx3) with x=a, b, c. Table I shows the Pole voltage as a function of the switching states.



TABLE 1

Pole voltage as a function of the switching states

(a) (b) (c) (d)

Fig. 2. Current flow through the switches of a leg on the four- level nested configuration.

(a) (b) (c)

Fig. 3. Current flow through the switches of a leg on the four-level NPC topology

Every switch is connected certain time only because in order to eliminate the short circuit through the leg. This nested

multilevel inverter input voltages are selected as Vdc1=Vdc2=Vdc3=Vdc, which means that VC1 =VC4 =VdcandVC2

=VC3 =Vdc/2.

Sx1

Sx2

Sx3

Sx4

Vx0

1

0

0

0

Vdc1+(Vdc2/2)

0

1

0

0

Vdc2/2

0

0

1

0

-Vdc2/2

0

0

0

1

-Vdc1-(Vdc2/2)



V1=Vdc1+Vdc2/2 , V2= Vdc2/2 , V3= - Vdc2/2,

V4= -Vdc3-Vdc2/2

Fig. 2 shows the current flow directions (positive and negative currents) when the switches Sx1-Sx4 are turned ON,

respectively. If Sx2, Sx3 are bidirectional controlled switches ,this switches are employed in the inner leg and also

Sx1,Sx4 switches are used in the outer leg. When positions of the switches( Sx1–Sx4) are changed. a short circuit was appear on the leg, Due to the reason is when outer leg’s switches are turned ON in the circuit.

III. PULSEWIDTHMODULATION (PWM) STRATEGY

The pulse width modulation is a technique which is characterized by the generation of constant amplitude by pulse duration

by modulating the duty cycle. In the sinusoidal PWM technique we are having the modulated signal and the carrier signal if

the carrier signal is to be of single then it is called single carrier based pwm technique. if the carrier signal is to be of multiple

in order then it is called multi carrier based PWM control technique.

If this paper implemented by using level shift pulse width modulation technique, there are phase disposition (PD), phase

opposition disposition (POD) and alternative phase opposition disposition (APOD)

1. PHASE DISPOSITION

If phase disposition is defined as the all carriers are selected in the same phase, that is denote as phase disposition. It is used

in this nested multilevel inverter ,get the lowest total harmonic distortion, and also compared to the other modulation

technics like as POD, APOD. The output waveforms of this method four, five & six levels are shown below.

Fig.4. phase disposition of carrier wave Fig.6. THD of four level phase disposition mode

(Van) (Vbn) (Vcn)

Fig.5. four level nested configuration three phase line to line pd output voltages



(Van) (Vbn) (Vcn)

Fig.7. five level nested configuration three phase line to line pd output voltages

Fig8. THD of five level phase disposition mode

(Van) (Vbn) (Vcn)

Fig.9. six level nested configuration three phase line to line pd output voltages

Fig.10. THD of six level phase disposition mode



2. PHASE OPOSITION DISPOSITION

If the phase opposition disposition method (POD), all carrier signals are arrange the above the zero line reference voltage

and below the line by 180 degrees as shown in below figure. if this phase opposition disposition technique was giving best

harmonic results compare to the alternate phase opposition disposition. The output voltage waveforms of four, five & six

levels are shown below.

Fig.11. phase opposition disposition of carrier wave Fig.13.THD of four level phase opposition disposition mode

(Van) (Vbn) (Vcn)

Fig:12. four level nested configuration three phase line to line pod output voltages

(Van) (Vbn) (Vcn)

Fig.14. five level nested configuration three phase line to line pod output voltages



Fig.15. THD of five level phase opposition disposition mode

(Van) (Vbn) (Vcn)

Fig.16. six level nested configuration three phase line to line pod output voltages

Fig.17. THD of six level phase opposition disposition mode

3. ALTERNATE PHASE OPOSITION DISPOSITION

If the alternate phase opposition disposition method (APOD) is used to arrange the three carrier waves in disposition group,

i.e called as alternative phase opposition disposition. If all carrier signals are arrange the above the zero line reference

voltage and below the line by 180 degrees as shown in below figure. this technique is similar to the phase opposition

technique and also alternative phase opposition disposition technique was giving best harmonic results, but it was giving

higher harmonics compare to the phase disposition and alternate phase opposition disposition. The output voltage waveforms

of four, five & six levels are shown below



Fig.18. apod carrier wave Fig.20. THD of four level apod mode

(Van) (Vbn) (Vcn)

Fig.19. four level nested configuration three phase line to line apod output voltages

(Van) (Vbn) (Vcn)

Fig.21. five level nested configuration three phase line to line apod output voltages



Fig.22. THD of five level alternative phase opposition disposition mode

(Van) (Vbn) (Vcn)

Fig.23. THD of six level alternative phase opposition disposition mode

Fig.24. THD of six level alternative phase opposition disposition mode

TABLE:2. THD of four, five and six levels by using PD, POD and APOD techniques

LEVEL PD POD APOD

4 51.39 54.78 57.35

5 38.75 40.69 42.42

6 25.05 27.81 29.42



PMSM MOTOR

PMSM, it is a synchronous motor which the rotor windings are replaced by high resistivity permanent magnet material so

no induced current in the rotor i.e. the rotor is lossless. In these motors (PMSM) the permanent magnet material is placed

on the rotor by many methods. Among these methods, surface mounted magnets, inset magnets and buried magnet.

Depending on these configurations, different properties of the machine are obtained. In case of surface mounted magnets, the rotor iron is approximately round and the stator inductance is low, as well as independent of the rotor position. The

control of the machine becomes simple and the reluctance effect can be neglected. This paper also use permanent magnet

synchronous motor, this pmsm motor is connect at the load and verify speed torque ripples.

Fig: speed of the pmsm Fig: torque of the pmsm

Fig.25. four level speed torque ripples using pmsm

Fig: speed of the pmsm Fig: torque of the pmsm

Fig.26. five level speed torque ripples using pmsm

Fig: speed of the pmsm Fig: torque of the pmsm Fig.27. five level speed torque ripples using pmsm



IV. CONCLUSION

This paper was completely involving the multilevel inverter based on the nested arrangement. This nested multilevel

inverter is used to reduce the number of diodes compare to the neutral point clamping inverter and consequently get a

higher efficiency. This paper was implemented by using level shift pwm techniques (PD,POD,APOD) to get the lower

harmonics and Also, the PMSM is to be fed with this nested multilevel converter with different output voltage levels

and performance comparison is to be accomplished in terms of torque ripples.

REFERENCES [1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17,

no. 5, pp. 518–523, Sep. 1981.

[2] S. Debnath and M. Saeedifard, “A new hybrid modular multilevel con-verter for grid connection of large wind turbines,”

IEEE Trans. Sustainable Energy, vol. 4, no. 4, pp. 1051–1064, Oct. 2013.

[3] J. Barros, J. Silva, and E. Jesus, “Fast-predictive optimal control of NPC multilevel converters,” IEEE Trans. Ind.

Electron., vol. 60, no. 2, pp. 619–627, Feb. 2013.

[4] S. Pulikanti, G. Konstantinou, and V. Agelidis, “Hybrid seven-level cascaded active neutral-point-clamped-based

multilevel converter under SHE-PWM,” IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 4794–4804, Nov. 2013.

[5] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu, J. Rodriguez, M. Pe and rez, and J. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580,

Aug. 2010.

[6] A. Ghias, J. Pou, V. Agelidis, and M. Ciobotaru, “Initial capacitor charging in grid-connected flying capacitor multilevel

converters,” IEEE Trans. Power Electron., vol. 29, no. 7, pp. 3245–3249, Jul. 2014.

[7] F. Salinas, M. Gonzalez, and M. Escalante, “Voltage balancing scheme for flying capacitor multilevel converters,” IET

Power Electron., vol. 6, no. 5,835–842, May 2013.

[8] V. Roberge, M. Tarbouchi, and F. Okou, “Strategies to accelerate harmonic minimization in multilevel inverters using a

parallel genetic algorithm on graphical processing unit,” IEEE Trans. Power Electron., vol. 29, no. 10,5087–5090, Oct. 2014.

[9] P. Chan, H.-H. Chung, and S. Hui, “A generalized theory of boundary control for a single-phase multilevel inverter using

second-order switching surface,” IEEE Trans. Power Electron., vol. 24, no. 10, pp. 2298–2313, Oct. 2009.

[10] A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Voltage-sharing converter to supply single-phase

asymmetrical four-level diode-clamped inverter with high power factor loads,” IEEE Trans. Power Electron., vol. 25, no. 10, pp. 2507–2520, Oct. 2010.

[11] M. Merlin, T. Green, P. Mitcheson, D. Trainer, R. Critchley, W. Crookes, and F. Hassan, “The alternate arm converter:

A new hybrid multilevel converter with dc-fault blocking capability,” IEEE Trans. Power Del., vol. 29, no. 1, pp. 310–317,

Feb. 2014.

[12] C. Gao, X. Jiang, Y. Li, Z. Chen, and J. Liu, “A dc-link voltage self-balance method for a diode-clamped modular

multilevel converter with minimum number of voltage sensors,” IEEE Trans. Power Electron., vol. 28, no. 5,2125–2139,

May 2013.

[13] G. Buticchi, D. Barater, E. Lorenzani, C. Concari, and G. Franceschini, “A nine-level grid-connected converter topology

for single-phase trans-formerless PV systems,” IEEE Trans. Ind. Electron., vol. 61, no. 8,3951–3960, Aug. 2014.

[14]J. Mei, B. Xiao, K. Shen, L. Tolbert, and J. Y. Zheng, “Modular multilevel inverter with new modulation method and its

application to photovoltaic grid-connected generator,” IEEE Trans. Power Electron., vol. 28, no. 11,5063–5073, Nov. 2013. [15] S. Krithiga, and N. Ammasai Gounden, “Power electronic configura-tion for the operation of PV system in combined

grid-connected and stand-alone modes,” IET Power Electron.,vol. 7, no. 3, pp. 640–647, Mar. 2014.

[16] E. Villanueva, P. Correa, J. Rodriguez, and M. Pacas, “Control of a single-phase cascaded H-bridge multilevel inverter

for grid-connected photo-voltaic systems,” IEEE Trans. Ind. Electron., vol. 56, no. 11, pp. 4399– 4406, Nov. 2009.

[17] E. Ozdemir, S. Ozdemir, and L. Tolbert, “Fundamental-frequency-modulated six-level diode-clamped multilevel

inverter for three-phase stand-alone photovoltaic system,” IEEE Trans. Ind. Electron., vol. 56, no. 11, pp. 4407–4415, Nov.

2009.

[18] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “A hybrid cascade converter topology with series-connected symmetrical

and asymmetrical diode-clamped H-bridge cells,” IEEE Trans. Power Electron., vol. 26, no. 1, 51–65, Jan. 2011.

[19] F. Dijkhuizen, and J. Duarte, “Pulse commutation in nested-cell converters through auxiliary resonant pole concepts,” in

Proc. IEEE 36th Annu. Meet. Ind. Appl. Conf. Rec., Sep. 2001, vol. 3, pp. 1731–1738. [20] F. Dijkhuizen, and J. Duarte, “Basic auxiliary resonant pole (ARP) applied to three-level nested cells switching leg,” in

Proc. IEEE 35th Annu. Power Electron. Spec. Conf., Jun. 2004, vol. 6, pp. 4434–4440.

[21] M. Mizukoshi, “Multilevel power converter including switching circuits,” U.S. Patent 6 005 787, Dec. 21, 1999, pp.

1585–1591.

ijcsmc, vol. 5, issue. 8, august 2016, pg.187 …in order then it is called multi carrier based pwm...

Documents