iiita ana layout testing

5/25/2018 IIITA ANA Layout Testing

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Analog Layout Techniques


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Layout Issues

Orientation

Common centroid

Unit cell repetition

Avoiding interconnect resistance

Adding dummy layers

Symmetry


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Orientation

M1 M2 M1 M2

Matched transistors should be oriented in same direction

Photolythography process has different biases in

different axes, hence the requirement


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Symmetry

M1 M2

Metal 1

An unrelated metal line going in the vicinity of one of the transistor

M1 M2

Metal 1 Metal 1

Symmetry should be preserved by adding another similar line


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Unit cell repetitionWide transistor should be laid out as parallel transistors

of unit width to decrease gate resistance, s/d area capacitanceas well as to counter DWeffect

Disproportionate aspect ratio can be managed as below:


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Interdigitation and dummy layer

D1

D2

S

G

M1 M2

S

D1 D2

G

Dummy poly

Dummy poly line eliminates loading effect in photo and etch

Interdigitation distributes the transistors uniformly


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Common centroid

1/2M2 1/2M1

1/2M1 1/2M2

Common centroid configuration eliminates the first order

gradient effects of parameters along both the axes


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Compatibility with CMOS

TechnologyIn an n-well technology the vertical PNP BJT can be realised

The p-substrate, connected to most negative potential (Gnd) acts

as a collector whereas n-well and p+region act as base & emitter

p+p+ n+

p-substrate

n well

C E B


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Antenna Effect


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Folding of MOSFET

Multi-Finger Transistors


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So far everything looks fine. But it is not. The transistor

with a width of 20um and a length of 0.2um is not exactly

the same as having four transistors that are connected inparallel, each with a width of 5um and a length of 0.2um.

Layout cannot be fabricated exactly as drawn in the

layout due to the limitations in the manufacturing

process, such as process tolerances and mask

misalignment.

Some of the manufacturing limitations are captured in

the Spice transistor model. Two of the main parameters

in the Spice transistor model are DW and DL.

DW shows the delta difference of drawn W from effective

W. DL shows the delta difference of drawn L from

effective L.


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The next diagram shows the transistor

effective channel length can be affected by

under-etching or over-etching of the poly,as well as the amount of lateral diffusion

under the gate.

The effective channel width of thetransistor is affected by the bird peak of

the isolation scheme.

In addition, the inclination of the gate polyup to the field oxide makes it difficult to

determine the exact width of the transistor.


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Considering an example where DL is

0.015um and DW is 0.045um. To simulate

a fast corner transistor, the transistor ismodeled to have a narrower L and a wider

W.

On the contrary, a slow corner transistoris modeled with a wider L and a smaller

W.

Hence, at the fast corner DL is negative(i.e. -0.015um) and DW is positive while at

the slow corner DL is positive and DW is

negative (i.e. -0.045um).


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The layout in the second stroke can be

statistically significant.

The circuit designer would perform Monte Carlosimulation to center the design so as to

improve manufacturing yield.

In Monte Carlo simulation, a small statisticalvariation is added to W and L of every transistor

in the circuit.

Folding a transistor to four fingers means that a

larger variation in the circuit performance sincethe variation made to the four fingers is four

times larger than the same variation made to a

single transistor.


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Is folding a transistor into

multiple fingers a bad idea? Actually, it is an excellent idea.

Everyone uses it. Second stroke makes

the layout compact.

Third stroke is a continuation of the

second stroke and it will enable the design

to run at a higher speed!


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Th ird Stroke. Speed up the

transistor What can you do in the layout to make the

transistor operate faster?

Reducing the parasitic capacitance and

resistance would increases the speed of thetransistor.

We need to understand where the parasitic

capacitances and resistances are.

The following diagram shows the simplified

capacitances associated with the drain, gate and

source of a transistor to the bulk.


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Overall Csb is dependent on the area of

source (AS) and perimeter of source (PS).

Similarly, overall Cdb is dependent on thearea of drain (AD) and perimeter of drain

(PD).

Both Csb and Cdb have components thatare dependent on the diffusions in the

proximity.

The values of AS, AD, PS and PD of atransistor can be extracted from the layout.

Postlayout spice netlist should include

these parameters.


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The folded transistors have smaller gate

resistance as shown in the diagram below.

This will make the transistors turn on and

off faster than the transistor in the first

stroke.


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In general, try to fold a transistor to an even

number of fingers.

Resistivity of the poly is a few orders higher than

the resistivity of the metal. The parasitic capacitances between the poly

and the substrate, and between the metal and

the poly, are very much larger than the parasitic

capacitance between the metal to the substrate.

Hence, using poly for interconnect could

degrade the frequency response of the transistor

if the poly routing is not optimized carefully.


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WIDE Transistor

Many finger

Layout


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DIFFERENTIAL PAIR(b)Different orientations

(c) Gate Aligned(d)Parallel Gates


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Effect of Gate shadowing

Gate Aligned Vs. Parallel Gates


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Dummy Devices Added


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Gradient Effect

One Dimensional Cross


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One Dimensional Cross-

coupling


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Layout of Resistances

R2/R1=5


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Use of n-Well Resistors


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Capacitors

Layout out of Interconnected


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Layout out of Interconnected

capacitors


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