ieee verilog coding rules
DESCRIPTION
IEEE Verilog Coding RulesTRANSCRIPT
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1 IEEE Verilog Coding Rules
Introduction
This chapter provides detailed reference information for the VerilogIEEE_RTL_SYNTH_SUBSET policy for the Leda Checker tool. This policycontains the rules defining the most common synthesis subsets forRegister Transfer Level (RTL) synthesis. They are based on industrialsubsets and on the rules featured in the following document:
IEEE P1364.1 "Draft Standard for Verilog Register Transfer LevelSynthesis"
The rules are grouped into rulesets. Each ruleset imposes constraintson the elements of the language for a given chapter of the VerilogLanguage Reference Manual (LRM) and is derived from thecorresponding subsection in the IEEE P1364.1 draft document. Table 2provides an overview of the different IEEE_RTL_SYNTH_SUBSET policyrulesets for Verilog.
Table 2: IEEE_VERILOG Policy Rulesets Ruleset Descriptions
"Data TypesRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 3 ofthe Verilog LRM.
"ExpressionsRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 4 ofthe Verilog LRM.
"AssignmentsThis is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 6 of
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Ruleset" the Verilog LRM.
"Gate and SwitchLevel ModelingRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 7 ofthe Verilog LRM.
"User DefinedPrimitivesRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 8 ofthe Verilog LRM.
"BehavioralModelingRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 9 ofthe Verilog LRM.
"Tasks andFunctionsRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 10 ofthe Verilog LRM.
"HierarchicalStructuresRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 12 ofthe Verilog LRM.
"Specify BlocksRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 13 ofthe Verilog LRM.
"System Tasksand FunctionsRuleset"
This is a set of rules implementing the constraintsimposed by synthesis on elements of Chapter 14 ofthe Verilog LRM.
Data Types Ruleset
The following rules are from the data types ruleset:
SYN3_2_1_B
Message: trireg nets are not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
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SYN3_2_2
Message: Drive strengths in net declaration areignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_3
Message: Charge strengths in net declaration areignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_4
Message: Delays in net declaration are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
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Language Verilog
Type Block-level
Severity Warning
SYN3_2_5
Message: Delays (delay2) in net declaration areignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_6
Message: Delays (delay3) in net declaration areignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_7
Message: tri1 nets are not supported for synthesis
Description None
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Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_8
Message: triand nets are not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_9
Message: tri0 nets are not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_10
Message: trior nets are not supported for synthesis
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Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_9_1
Message: time declarations are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_9_2
Message: real declarations are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
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SYN3_9_3
Message: realtime declarations are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
Expressions Ruleset
The following rules are from the expressions ruleset:
SYN4_1_1_B
Message: Expressions of type mintypmax are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Warning
SYN4_1_2
Message: The case equality operator '===' is notsupported in binary operations
Description None
Policy IEEE_RTL_SYNTH_SUBSET
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Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Error
SYN4_1_3
Message: The case inequality operator '!==' is notsupported in binary operations
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Error
SYN4_1_4
Message: Real numbers are not supported forsynthesis
Description This rule tests that real literals are not used.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Error
Assignments Ruleset
The following rules are from the assignments ruleset:
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SYN6_1_1
Message: Do not use assignment in net declaration
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Error
SYN6_1_2
Message: Drive strengths in continuous assignstatements are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
SYN6_1_3
Message: Delay3 values in continuous assignstatements are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
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Severity Warning
SYN6_1_4
Message: Delay2 values in continuous assignstatements are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
SYN6_1_5
Message: Delay values in continuous assignstatements are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
Gate and Switch Level Modeling Ruleset
The following rules are from the gate and switch level modeling ruleset:
SYN7_1_1
Message: nmos switch instantiations are not
supported for synthesis
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supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_2
Message: pmos switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_3
Message: rnmos switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
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SYN7_1_4
Message: rpmos switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_5
Message: tran switch instantiations are not supportedfor synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_6
Message: rtran switch instantiations are not supportedfor synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
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Language Verilog
Type Block-level
Severity Error
SYN7_1_7
Message: tranif0 switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_8
Message: tranif1 switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_9
Message: rtranif0 switch instantiations are notsupported for synthesis
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Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_10
Message: rtranif switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_11
Message: cmos switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
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SYN7_1_12
Message: rcmos switch instantiations are notsupported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_13
Message: pull (pullup and pulldown) gateinstantiations are not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_14
Message: Drive strengths in n input gateinstantiations are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
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Type Block-level
Severity Warning
SYN7_1_15
Message: Drive strengths in n output gateinstantiations are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_16
Message: Drive strengths in enable gate instantiationsare ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_17
Message: Delay2 values in n input gate instantiationsare ignored
Description None
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Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_18
Message: Delay values in n input gate instantiationsare ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_19
Message: Delay2 values in n output gateinstantiations are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_20
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Message: Delay values in n_output gate instantiationsare ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_21
Message: Delay3 values in enable gate instantiationsare ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN7_1_22
Message: Delay2 values in enable gate instantiationsare ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
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Severity Warning
SYN7_1_23
Message: Delay values in enable gate instantiationsare ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Warning
User Defined Primitives Ruleset
The following rules are from the user defined primitives ruleset:
SYN8_1_1_B
Message: UDP declarations are not supported forsynthesis
Description User-defined primitive declarations are not supported forsynthesis.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset USER_DEFINED_PRIMITIVES
Language Verilog
Type Block-level
Severity Error
SYN8_6_1_A
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Message: UDP instantiations are not supported forsynthesis
Description User-defined primitive declaration instantiations are notsupported for synthesis.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset USER_DEFINED_PRIMITIVES
Language Verilog
Type Block-level
Severity Error
Behavioral Modeling Ruleset
The following rules are from the behavioral modeling ruleset:
SYN9_1
Message: Illegal always construct: Does not model anycombinational logic or sequential logic
Description
Combinational logic is modeled by an always statement ifits event list does not contain any edge event (posedgeor negedge). Sequential logic is modeled if the alwaysstatement has one or more edge events in the event list(that is, @(posedge clock)). One of the edge eventsspecified must represent the clock edge condition underwhich the storage device stores the value (see Section 5in IEEE P1364.1 /D1.4 Draft Standard for Verilog RTL). Forexample:
always @(posedge CLOCK)if (RESET) // RESET models the reset signal of // the storage device OUT = 1'b0; else OUT = 1'b1;
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
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Language Verilog
Type Block-level
Severity Error
SYN9_2
Message: Missing or redundant signal in thesensitivity list of an always block
Description
All the variables read in the always statement must beincluded in the sensitivity list to avoid mismatchesbetween simulation and synthesized logic.Note:unnecessary signals in the sensitivity list are alsodetected.When modeling combinational logic and latches,all the signals read in the always block must be in thesensitivity list. All other signals must not be present inthe sensitivity list.When modeling sequential logic (flip-flops) only the clock and asynchronous set-reset signalsmust be in the sensitivity list.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_3
Message: Do not mix blocking and non-blockingassignments in a combinational always block
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
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Severity Error
SYN9_4
Message: Do not use blocking assignments forvariables modeling level-sensitive storage devices(latches)
Description Prevents race conditions in Verilog simulations.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_5
Message: A level-sensitive storage device (latch) maybe inferred for this variable
Description
This rule is intended to make sure that latch inferringwas not done accidentally. This rule only checks at themodule level. There is a similar rule in the Leda generalcoding guidelines policy that you can use to check theentire design.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN9_6
Message: A sequential always block must have one
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clock signal exactly
Description
When modeling edge-sensitive storage devices, thefollowing rules apply:
SYN9_6SYN9_7SYN9_8SYN9_9SYN9_10SYN9_11
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_7
Message: Do not use blocking assignments insequential always blocks
Description
Non-blocking assignments are recommended to avoidrace conditions in Verilog simulations. When modelingedge-sensitive storage devices, the following rules apply:
SYN9_6SYN9_7SYN9_8SYN9_9SYN9_10SYN9_11
This rule is flagged for unintentional latches also.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
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Severity Error
SYN9_8
Message: Only one edge event should be present inthe event list of a synchronous always block
Description
When modeling edge-sensitive storage devices, thefollowing rules apply:
SYN9_6SYN9_7SYN9_8SYN9_9SYN9_10SYN9_11
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_9
Message: A clock expression should be of the form'posedge <clock_name>'
Description
When modeling edge-sensitive storage devices, thefollowing rules apply:
SYN9_6SYN9_7SYN9_8SYN9_9SYN9_10SYN9_11
When modeling edge-sensitive storage devices with
asynchronous set-reset, the following rules apply:
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asynchronous set-reset, the following rules apply:
SYN9_9SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_10
Message: A falling-edge clock expression should be ofthe form 'negedge <clock_name>'
Description
When modeling edge-sensitive storage devices, thefollowing rules apply:
SYN9_6SYN9_7SYN9_8SYN9_9SYN9_10SYN9_11
When modeling edge-sensitive storage devices withasynchronous set-reset, the following rules apply:
SYN9_9SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
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Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_11
Message: Multiple event lists in an always statementare not supported for synthesis
Description
When modeling edge-sensitive storage devices, thefollowing rules apply:
SYN9_6SYN9_7SYN9_8SYN9_9SYN9_10SYN9_11
When modeling edge-sensitive storage devices withasynchronous set-reset, the following rules apply:
SYN9_9SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
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SYN9_12
Message: Polarity mismatch for asynchronousreset/set/load <%context> : use 'if(<%context>)'
Description
If a variable modeling asynchronous reset/set/load has aposedge event, then it should have positive polarity inthe corresponding if condition.When modeling edge-sensitive storage devices with asynchronousreset/set/load, the following rules apply:
SYN9_9SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_13
Message: Polarity mismatch for asynchronousreset/set/load <%context> : use 'if(!<%context>)','if(~<%context>' or 'if(<%context> == 1'b0)'
Description
If a variable modeling asynchronous reset/set/load has anegedge event, then it should have negative polarity inthe corresponding if condition. When modeling edge-sensitive storage devices with asynchronousreset/set/load, the following rules apply:
SYN9_9
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Description SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_14
Message: Level sensitive events are not allowed in asequential always block
Description
When modeling edge-sensitive storage devices withasynchronous set-reset, the following rules apply:
SYN9_9SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
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SYN9_15
Message: An asynchronous sequential always blockmust have one clock signal exactly
Description
When modeling edge-sensitive storage devices withasynchronous set-reset, the following rules apply:
SYN9_9SYN9_10SYN9_11SYN9_12SYN9_13SYN9_14SYN9_15
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_16
Message: Initial constructs are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Warning
SYN9_17
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Message: Procedural continuous assign statements arenot supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_18
Message: Procedural continuous deassign statementsare not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_19
Message: Procedural continuous force statements arenot supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
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Severity Error
SYN9_20
Message: Procedural continuous release statementsare not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_21
Message: Repeat event controls in timing controlstatements are not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_22
Message: Delay values are ignored in synthesis
Description This rule tests delay values in assignment statements.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
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Language Verilog
Type Block-level
Severity Warning
SYN9_23
Message: Forever loop statements are not supportedfor synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_24
Message: Repeat loop statements are not supportedfor synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_25
Message: While loop statements are not supported forsynthesis
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Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_26
Message: Expression bound in for loop statementsshould be statically computable
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_27
Message: Initial reg assignment bound in for loopstatements should be statically computable
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
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SYN9_28
Message: Wait statements are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_29
Message: Event triggers are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_30
Message: Fork-join blocks are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
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Type Block-level
Severity Error
SYN9_31
Message: Event declarations are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_32
Message: The always statement must be followed byan event control (@)
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
Tasks and Functions Ruleset
The following rules are from the tasks and functions ruleset:
SYN10_1
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Message: Writing to global variables in functions isnot supported for synthesis
Description
Use of variables (both reading the value of and writing avalue to) that are defined outside a function declarationbut not within the enclosing module declaration is notsupported. The Checker reports an error if a variable isassigned a value in a function and defined elsewhere.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Error
SYN10_2
Message: Writing to global variables in tasks is notsupported for synthesis
Description
Use of variables (both reading the value of and writing avalue to) that are defined outside a task declaration butnot within the enclosing module declaration is notsupported. The Checker reports an error if a variable isassigned a value in a task and defined elsewhere.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Error
Hierarchical Structures Ruleset
The following rules are from the hierarchical structures ruleset:
SYN12_1
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Message: Macromodules are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset HIERARCHICAL_STRUCTURES
Language Verilog
Type Block-level
Severity Error
SYN12_2
Message: Input ports must not be assigned a value
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset HIERARCHICAL_STRUCTURES
Language Verilog
Type Block-level
Severity Error
Specify Blocks Ruleset
The following rule is from the specify blocks ruleset:
SYN13_1
Message: Specify blocks are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SPECIFY_BLOCKS
Language Verilog
Type Block-level
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Severity Warning
System Tasks and Functions Ruleset
The following rules are from the system tasks and functions ruleset:
SYN14_1
Message: System task enables are ignored
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SYSTEM_TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Warning
SYN14_2
Message: System function calls are not supported forsynthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SYSTEM_TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Error