Modelling of Co

Aayush Rustagi ECE JIITU Noida, INDIA aayushcool@gmail.com

978-1-4244-4547-9/09/$26.00 ©2009 IEEE

Abstract- Analytical model has been propointerconnect structure with ten metal striplayers. All the capacitative componentcomputed to measure the total value oComparative study has been undertaken towith least area occupancy as well as less capacitance. We have proposed a complegeometry to overcome the major proboccupancy and the total capacitance. Index Terms-Fringe capacitance, conformal mand lateral capacitance.

I. INTRODUCTION

In modern integrated circuits, interconnmodelling is a complex task. The capacitance dependent on their topology, on the distanwires above or below, and on the separation Estimation of circuit performance and signnecessary in the design phase to ensure proper

We discuss about the different ccapacitance. These components are shown in f

Figure 1 Area, lateral, and fringing com

omplex Interconnect Str Kanika Jain ECE JIITU Noida,INDIA kanikajain86@gmail.com

sed of complex ps in different ts have been

of capacitance. o have a model

value of total x interconnect

blems of area

mapping, overlap

nect capacitance of such wires is ces from other between wires.

nal integrity is r reliability[1]

components of figure 1

mponents.

The first capacitance is between acalled the grounded capacitance. capacitance in the past, but its valdue to scaling effects. The next capalines on the same layer which is calleThis is the main coupling capacitanand noise issues.

This capacitance has been incThere are two other capacitancescoupling between lines. One is froccurs between various edges andcrossing lines. The other type of couwhen two wires on different metal called area capacitance or commcapacitance.

Over the years coupling capaciwhile the grounded capacitance hacapacitance at any metal line or components Overlap capacitance, fringe capacitance.

In this paper we have propoconsisting of ten metal strips in vaTwo most important factors in an intotal value of capacitance and thmodel. Here we have tried to comhave least value of capacitance andless.

II. MODELING OF COUPL A. Fringe capacitance

To formulate the multilevel capconsider the modelling of all the dbetween two interconnects in differe

ructures

TENCON 2009

a line and the substrate This was the dominant ue has been diminishing acitance is between metal ed the lateral capacitance. ce that is source of delay

creasing over the years. that may give rise to

fringe capacitance which d surfaces between two upling capacitance occurs layers overlap and hence

monly known as overlap

tance has been increasing as been decreasing. The node consists of three lateral capacitance and

sed complex geometries arious number of layers.

nterconnect model are the e area occupied by the

mpute a model where we d area is occupied is also

ING CAPACITANCE

pacitance model, first, we ominant capacitances [2]

ent metal layers

1

Fig. 2. Capacitances between two metal lines in d

We use the following notations to describeinterlayer dielectric thickness; W width of thickness of metal line; S non overlap distancmetal lines; Edi dielectric permittivity.

Fig 2 shows the dominant capacitances beoverlapped interconnect lines in different layeassume that these two interconnects are in isolcapacitances are conventionally grouped togefringe capacitance [3] Cfr, which is given by

Cfr = Ccorner + (Csw,top1 + Csw,top2) + (Ctop,to

+ (Csw1,sw2)

The model is derived by analyzing thbetween interconnects and using technoparameters. Fringe capacitance between two given by

Cf=2( diπ

2ln [

H+ηT+ S2+(ηT)2+2H

S+H

+2( Wα di (ln 1+ 2WS + e -S+T

3S

Wπα+ H+T (ln 1+ 2WS +e -S3

+ 2(T β di ( ln 1+ 2T

H + e -H+W3H

Tπβ + S+W (ln 1+ 2TH +e -H+

3

+ di

πHS

H2+S2

different layers.

e our model: H f metal line; T ce between two

etween two non ers. Initially, we lation. All these ether and called

op1+ Ctop,top2) (1)

he electrostatics ology-dependent

metal strips is

HηT] )

)+T3S )

)

)+W3H )

)

B. Lateral Capacitance

The lateral capacitance in two dproportional to spacing ‘s’ and is giv

Clat= oxTS

C. Overlap Capacitance

The overlap capacitance is formed b2-d) of two conductors separated bycalculated using well known equatcapacitance:

Cov= r oAD(2,3

III. COMPLEX INTERCONN

A. Interconnect Geometry I

Fig 3. Interconnect

Here is a complex geometry whand ten metal strips. We took sevcapacitance which is the highestreduced as there is more space thickness difference between metal shigh area occupancy.

Fringe Capacitance is computed for we take metal strip 1 and fringe (1,4),(1,3),(1,2),(1,7),(1,6),(1,8),(1,9

dimensional is inversely ven by[4]

T

by the surface overlap (in y a distance (d) apart, it is tion[5] for parallel plate

A3)

ECT GEOMETRIES

t geometry 1

here there are seven layers ven layers so that fringe t contributing factor is and interlayer dielectric strips although it has very

all the metal strips. First capacitance is between

) and (1,10).

2

Metal strip 5:(5,4),(5,3),(5,2),(5,7),(5,6),(5,8),(Metal strip 4: (4,7),(4,6),(4,9) Metal strip 8: (8,3),(8,2),(8,7),(8,6) and (8,9) Metal strip 10:(10,9),(10,7),(10,6),(10,3) and (Metal strip 3: (3,6) Metal strip 7: (7,2) Metal strip 9: (9,6) and (9,2)

Lateral Capacitance is between metal strips (3,4).Apart from the lateral capacitance we acapacitance between the above mentionedconsists of only one component that is C(top,to

Overlap Capacitance is between (2,6),(3,7),(1,5),(8,10),(7,9) and (4,8).

Hence total Capacitance is Ctot = CF+COV+C

The table given below shows the interlthickness and spacing for fringe capacitance strips.

Spacing(s) Interlayer dielectric thickness

Fringe com

s h (1,4),(5,4),(8,7

s h1 = 3h+2t (8,3),(

s h2 = 4h+3t (1,8),(5,10)

s h3 = 5h+4t (10

s h4 = 6h+5t (1,1

s h5 = 2h+t (5,8),(4,7),(3,

Spacing (s1 = 2s+w)

Interlayer dielectric thickness

Fringe com

s1 h (1,3),(5,3),

s1 h1 = 3h+2t (1,7),(5,9),(

s1 h3 = 5h+4t (1,9),(

s1 h5 = 2h+t (4,

(5,9) and (5,10)

(10,2)

(2,3),(6,7) and also have fringe d strips which op).

metal strips

Clat.

layer dielectric between metal

mponents

7),(8,9),(10,9)

(10,7)

),(9,2),(4,9)

0,3)

10)

6),(7,2)(,9,6)

mponents

,(5,7),(8,6)

(8,2),(10,6)

(10,2)

6)

Spacing (s2 = 3s+2w)

Interlayer dielectric thickness

s2 h

s2 h1 = 3h+2t

Lateral component with spacing ‘s’ Overlap component with Interlayer dare (2,6),(3,7),(1,5),(8,10) and (7,9);thickness (3h+2t) is (4,8)

The following output was obtained incapacitance.

B. Interconnect Geometry II

Fig 4. Interconnect g

Fringe components

(1,2),(5,2),(5,6)

(1,6)

are (2,3),(6,7) and (3,4). dielectric thickness (2h+t) ; with interlayer dielectric

n Matlab for total

eometry 2

3

Here is a complex geometry where there are ten metal strips. Earlier we had complex geommetal strips in 7 layers hence occupying a verhaving low total capacitance as there was mointerlayer dielectric thickness between the strip We took four layers so that the total numcomponents gets reduced and area occupancy Now fringe capacitance is computed for all theFirst we take metal strip 3 and fringe capacita(3,1),(3,7),(3,8),(3,2),(3,9) and (3,10) Metal strip 1 : (1,5),(1,6),(1,8),(1,9) and (1,10)Metal strip 4: (4,2),(4,8),(4,9) and (4,10) Metal strip 7: (7,5),(7,10),(7,2) and (7,6) Metal strip 5: (5,9) and (5,2) Metal strip 8: (8,6) and (8,2) Metal strip 10: (10,9),(10,6) and (10,2) Lateral capacitance is between (9,8),(6,5),(8,7),(4,3),(5,4) and (1,2).Apart frcapacitance we also have fringe capacitancabove mentioned strips which consists component that is C(top,top). Overlap capacitance is between (2,6),(4,7),(5,8),(8,10),(6,9) and (1,4). Hence total capacitance is Ctot = CF+COV+C The table given below shows the interlthickness and spacing for fringe capacitance strips.

Spacing (s1 = 2s+w)

Interlayer dielectric thickness

Fringe com

s1 h (3,8),(1,6),(4,

s1 h1 = 2h+t (3,10),(1

Spacing (s) Interlayer dielectric thickness

Fringe com

s h (3,1),(3,7),(1,5(7,10),(5,2),(5,

s h1 = 2h+t (1,8),(4,10),

s h2 = 3h+2t (1,10),

four layers and metry having ten ry large area but ore spacing and ps

mber of fringe is also reduced.

e metal strips. ance is between

)

metal strips from the lateral ce between the

of only one

metal strips

Clat

layer dielectric between metal

mponents

2),(4,9),(7,6)

,9),(7,2)

mponents

5),(4,8),(7,5), ,9),(8,6),(10,9) (8,2),(10,6)

,(10,2)

Spacing (s2 = 3s+2w)

Interlayer dielectric thickness

s2 h

Lateral component with spacing ‘s’ and (5,4); with spacing (2s+w) is (1, Overlap component with interlayerare (2,6),(6,9),(5,8),(8,10),(1,4) and ( The following output was obtained in

C. Interconnect Geometry III

Fig 5. Interconnect geom

Fringe components

(3,2),(3,9)

are (6,5),(9,8),(8,7),(4,3) 2)

r dielectric thickness ‘h’ (4,7)

n Matlab.

metry 3

4

Continuing with the same complex geometry four layers and ten metal strips. In interconnect geometry 3 the metal strips haa manner such that total capacitance is dinterconnect geometry 2, considering the area Fringe Capacitance is computed for all the metFirst we take metal strip 1 and fringe capacita(1,4),(1,6),(1,7),(1,9) and (1,10) Metal strip 5: (5,9),(5,3),(5,4),(5,10) and (5,2) Metal strip 8: (8,6),(8,3),(8,4),(8,7) and (8,2) Metal strip 2: (2,4),(2,7) and (2,10) Metal strip 6: (6,3),(6,4) and (6,10) Metal strip 9: (9,7),(9,4) and (9,3) Lateral Capacitance is between (3,2),(2,1),(7,6),(6,5),(10,9) and (9,8).Apart fcapacitance we also have fringe capacitancabove mentioned strips which consists component that is C(top,top). Overlap Capacitance is between (3,4),(4,7),(5,8),(7,10),(6,9),(1,5) and (2,6). Hence total capacitance is Ctot = CF+COV+C The table given below shows the interlthickness and spacing for fringe capacitance strips.

Spacing (s) Interlayer dielectric thickness

Fringe comp

s h (5,9),(8,6),(2,4),(6,

s h1 = 2h+t (1,6),(2,7),(5,2)

s h2 = 3h+2t (1,9),(8,2),(2,

Spacing (s1 = 2s+w)

Interlayer dielectric thickness

Fringe comp

s1 h (1,4),(5,4),(5,

s1 h1 = 2h+t (1,7),(5,3)

s1 h2 = 3h+2t (1,10),(8

where there are

ave been kept in decreased from occupancy.

tal strips. ance is between

metal strips from the lateral ce between the

of only one

metal strips

Clat

layer dielectric between metal

ponents

,4),(6,10),(9,7)

),(6,3),(9,4)

,10),(9,3)

ponents

,10),(8,7)

),(8,4)

8,3)

Lateral component with (3,2),(2,1),(7,6),(6,5),(10,9) and (9,8 Overlap component with Interlayerare (3,4),(4,7),(5,8),(7,10) and (6,9);thickness (2h+t) are (2,6) and (1,5). The following output was obtained in

Following is the comparison betweenthe three geometries.

spacing ‘s’ are ) .

r dielectric thickness ‘h’ ; with interlayer dielectric

n Matlab.

n the total capacitance of

5

IV. ANALYSIS

In interconnect geometry 1, there were 10 metal strips in 7 layers , hence area occupancy was high. The total value of capacitance is less compared to other geometries because interlayer dielectric thickness difference between metal strip in first and last layer is ‘6h+5t’ which is much more compared to four layer concept. In Interconnect geometry 2, there were 10 metal strips in 4 layers, hence area occupancy was less compared to first geometry. The geometry was designed in a manner that metal strips were placed close to each other in terms of interlayer dielectric thickness where maximum difference between metal strip in first and last layer is ‘3h+2t’. As the metal strips were kept close to each other to reduce the area occupancy we see a drastic increase in total capacitance. In Interconnect geometry 3, there were 10 metal strips in 4 layers, this geometry is designed in a manner to overcome both area occupancy and total capacitance value. The metal strips are placed in a manner that total capacitance value decreases from interconnect geometry 2 and is comparable to the value of total capacitance of geometry 1.

V. CONCLUSION We finally proposed a complex interconnect geometry consisting of ten metal strips in seven layers which occupies much area and total value of capacitance comes out to be less. To reduce the area occupancy we again proposed a model of ten metal strips in four layers and we observed that area occupied was less but total value of capacitance increased drastically. Henceforth we gave a model with same number of metal strips that is ten in four layers and as a result both the total capacitance value and the area occupied decreased compared to previous geometry.

REFERENCES

[1] N. S. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, and M. Kulkarni, “Benchmarks for Interconnect parasitic resistance and capacitance,” in Proc. ISQED, 2003, pp. 163–168. [2] T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M.Shirota, K. Eikyu, Y. Ajioka, H. Makino, K.Ishikawa,S.Iwade, and Y. Inoue, “Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemto Farad resolution, ”IEEE Trans. Electron Devices, vol.51, pp. 726–735, May 2004. [3] A. Bansal, B. C. Paul, and K. Roy, “Modelling and optimization of fringe capacitance of nanoscale DGMOS devices,” IEEE Trans. Electron Devices,vol. 52, no. 2, pp. 256–262, Feb. 2005. [4] David A Hodges, Resve A Saleh, “Analysis and design of digital Integrated design”.

[5] Narain D Arora , V. Raol and Llanda M Richardson “Modeling and Extraction of interconnect Capacitances for Multilayer VLSI Circuits”.

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