ieee sf bay area council grid magazine - ieee san francisco
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F E B R U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1
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Upcoming Conferences
Feb. 6-9: DesignCon 2006 Santa Clara Convention Center [more]
Mar. 6-8: Internationalization and Unicode Conference Hyatt Regency Hotel, Burlingame [more]
Mar. 20-24: The Game Developers Conference - San Jose Convention Center - With GDC Mobile and Serious Games Summit [more]
Mar. 26-31: PCB Design Conference West Santa Clara Convention Center [more]
Mar. 27-29: Int’l Symposium on Quality Electronic Design DoubleTree Hotel, S.J. [more]Apr 3-7: Embedded Systems Conference - San Jose Convention Center [more]Co-located with ESC: D2M, and the IEEE Real-Time & Embedded Technology & Applications Symposium [more]
February 2006
Support our advertisers MARKETPLACE – Services page 3 Faculty Positions at S.F. State, NPS page 6 Engineering Week Banquet page 4 Science Fair volunteers needed page 13 Conference Calendar page 35
SCV-LEOS - 2/7 | A Primer on the Food & Drug Administration (FDA) - lasers and other radiological health products ... [more]
SCV-CPMT- 2/8 | MultiLayer Ceramic Capacitor (MLCC) Value Drift and Embedded Passives - two talks... [more]
SCV-MTT - 2/9 | Behavioral Modeling of Microwave Devices and Circuits – techniques with emphasis on nonlinearity & dynamics... [more]
SCV-CIS - 2/9 | Computation with Information Described in Natural Language - a problem of intrinsic importance ... [more]
SCV-SPS - 2/13 | Distributed Wireless Communication: A Shannon-Theoretic Perspective on Fading Multihop Networks -... [more]
SCV-EMB - 2/15 | Biometrics: A Brief History and Review of Current Programs - face and iris recognition ... [more]
SCV-SSC - 2/16 | A Fourth Generation 1.8GHz Dual-core SPARC V9 Microprocessor - implementation and productization... [more]
OEB-Comm - 2/16 | Wireless Sensor and Control Networks - the diverse technologies being employed and emerging standards ... [more]
SCV-Mag - 2/21 | Magnetic Biochips: Laboratory Curiosity or Killer App? - magnetic nanotags and spin valve sensor arrays ... [more]
SCV-EDS - 2/21 | Status on Immersion Lithography Processing - water between the lens and photoresist material... [more]
SF-Comm - 2/21 | VoIP - Implementing the New Phone System - voice characteristics, impairments, protocols, security ... [more]
SCV-Ed - 2/22 | Education Challenges in the Age of Nano-Scale Technologies - changes in the era of the nanometer generation ... [more]
SF-PES - 2/23 | Pad-Mounted Distribution Substations - lower cost & construction time, aesthetic improvement, less land... [more]
IEEE+SVEC - 2/24 | Annual Engineering Week Banquet - gala event for all engineers, guests ... [more]
ARRL - 2/25 | RadioFest 2006 - a no-cost public service & family event with Ham radio demos, vendor booths, speakers ... [more]
SCV-CAS - 2/27 | The "D" in DFM - a holistic approach to Design For Manufacturability ... [more]
SCV-CNSV - 2/28 | The Technology Behind the New IEEE-CNSV Website - the development tools and user interface ... [more]
SCV-CE - 2/28 | High-Definition Multi-Room DVRs and Hard Disk Drives - performance for streaming applications ... [more]
SCV-Rel - 3/1 | Best of RAMS - reviews from the Reliability and Maintainability Symposium in Newport Beach in January ... [more]
SCV-CPMT- 3/8 | Restriction of Hazardous Substances (RoHS) Directive Implementation Challenges - conversion to lead-free [more]
SCV-CNSV- 3/21 | Professional Selling in a Competitive Market - systematic B2B sales techniques to increase your revenue ... [more]
OEB-PES- 3/28 | Panel: Update on Nuclear Energy in US ... [more]
4-day theory+lab classes held March 29 – April 1 San Jose State Electrical Engineering Dept - DSP System Design and Implementations - FPGA DSP System Design - Wireless Transmitters - Sensor Networks/Mobile Ad-Hoc Technology - Embedded Systems & Embedded FPGAs [more] Professional Skills Courses from EMS, CPMT, ETA:
High-Impact Communication Feb 9 at LSI Logic, Milpitas [more]
Memory Power (half-day) Feb 15 at Exar Corporation, Fremont [more]
Collaborative Negotiating [more]- Feb 16 at Cypress Semiconductor, San Jose
Working Across Cultures [more]- March 9 at LSI Logic, Milpitas
Management Essentials [more]- March 16-17 at Cypress Semiconductor, San Jose
F E B R U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 2
Your Networking Partner ®
February 2006 • Volume 53 • Number 2
IEEE-SFBAC ©2006
IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for both news and opinion, the editorial objectives of IEEE GRID are to inform readers in a timely and objective manner of newsworthy IEEE activities taking place in and around the Bay Area; to publish the official calendar of events; to report on IEEE activities of a national and international scope; and to serve as a forum for comment on areas of concern to the engineering community by publishing contributed articles, invited editorials and letters to the editor. IEEE GRID is published as the GRID Online Edition
residing at www.e-GRID.net, and in a handly printable GRID.pdf edition, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.
Editor: Paul Wesling IEEE GRID 12250 Saraglen Dr. Saratoga CA 95070 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net
From the editor . . .
I always find it exciting and challenging to hear a
talk by one of the luminaries in our profession. For example, someone who has been elected an IEEE Fellow clearly has expertise that has been recognized by peers in the profession. Similarly for a winner of an IEEE Field Award.
So this month the Silicon Valley Engineering
Council (SVEC) is inducting four individuals into its Hall of Fame: Mr. Jack Baskin, Founder of the Jack Baskin School Engineering at the University California, Santa Cruz; Dr. Thomas Kailath, Hitachi America, Professor of Engineering Emeritus at Stanford University; Dr. Sass Somekh, President of Novellus Systems; and Dr. Lotfi Zadeh, Professor of Electrical Engineering & Computer Science at UC-Berkeley and the father of fuzzy logic (whom you can also hear February 9th at the CIS Chapter meeting). You are invited to attend the SVEC dinner and festivities, hear about these people (and meet them), and hear an interesting talk by Dr. Sasha Buchman, Science Mission Manager, about the Gravity Probe–B. Details are on page 4.
Also, Valentines Day is fast approaching. This is a reminder to think beyond our wonderful technology, in which we immerse ourselves (perhaps to an extreme) – consider some of the special people in your life, and honor them on this special day.
Paul Wesl ing ed i to r@e-gr id .ne t
NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net
Chairman Julian Ajello
Finance Chair Ron Kane
Editorial Board Chair Annie Kong
OEB Director Bill DeHope
SF Director James Lekas
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IEEE GRID
F E B R U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 3
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road, Palo Alto 94303
www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835
Bernie Siegal
650-961-5900
[email protected] www.thermengr.com
Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures
Mixed-Signal IC Development
• From Inception to Production Transfer • Turnkey, Design Services & Consulting • Design Reviews & TroubleShooting
Mixel, Inc. Excellence in Mixed Signal Design
(408) 274-2736 [email protected] www.mixl.com
Digital Chip Design Services
ASIC Design • EDA Evaluation • Verilog HDL • Synthesis • Design for Visibility • Timing • Scan • Verification • Low Power techniques • Power Analysis • BIST • DFT • ATPG • Silicon Debug
Testable logic for high-volume production with low DPM
Contact Mahesh Siddappa ME (CS, India), MS (EE, SUNY at Stony Brook)
[email protected] 408-981-6612
Do you provide a service? Would you like more inquiries?
• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available
Visit our Marketplace (page 3)
Download Rates and Services information: www.e-grid.net/docs/marketplace-f lyer.pdf
GRID.pdf
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ANSYS Channel Partner
• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses
Ozen Engineering (408) 732-4665
[email protected] www.ozeninc.com
Board Logic Systems
Complete Product Solutions Provider TM
Experienced consultants in the fields of: • Board & Verilog Design • Debug and Test • Signal Integrity • EMI • Power Electronics • Layout • Software Development • Documentation
www.boardlogics.com
[email protected] (650) 867-0869
Professional Services Marketplace – [email protected] for information
Say you found them in our GRID MARKETPLACE
Professional Consulting Services to assist clients in developing & executing any and all elements of Reliability throughout an Organization & Product Life Cycle.
• Assessments • Goals • Benchmarking • Reliability Prog. Plans • MTBF Pred • FMECA • EOL Assessment • Warranty Analysis • HALT/HASS • DVT/V&V • Rel. Demo. Tests • Software Reliability • CAPA/CLCA • DoE • Training/teaching • RoHS/WEEE Transition
pioneered Reliability IntegrationSM - using multiple tools in conjunction to increase the power and value of any Reliability Program.
(408) 472-3889 [email protected] www.opsalacarte.com
MET Laboratories
EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)
Facilities in Union City, Santa Clara
www.metlabs.com [email protected] 510-489-6300
Valon Technology, LLC
valontechnology.com
RF and Wireless Product Design & Development
- System Engineering - Test & Measurement - Schematic Capture & PCB layout - Expert Witness
Redwood City (650) 369-0575
F E B R U A R Y 2 0 0 5 V i s i t u s a t w w w . e - G R I D . n e t P a g e 4
Agenda 5:30 PM Reception and No-Host Bar 6:30 PM Welcome by SVEC President 6:45 PM Dinner with Friends 7:15 PM Recognition of Sponsors and Distinguished Guests 7:30 PM Discover-E Presentation
7:45 PM PM Keynote Speaker Dr. Buchman, Gravity Probe -B
8:15 PM Scholarship Presentation
8:45 PM SVEC Engineering Hall of Fame Induction Ceremony 9:15 PM Close
Hall of Fame Inductees
Mr. Jack Baskin, Founder of the Jack Baskin School Engineering at the University California, Santa Cruz Dr. Thomas Kailath, Hitachi America Professor of Engineering Emeritus at Stanford University Dr. Sass Somekh, President of Novellus Systems Dr. Lotfi Zadeh, Professor of Electrical Engineering & Computer Science at the University California, Berkeley
“The Alliance for Engineering Leaders in Silicon Valley”
Silicon Valley Engineering Council is dedicated, through a network of volunteers and local engineering societies, to meeting the needs of the engineers of today and of tomorrow.
AFE ECSCV AIAA IEEE AIChE NSPE AISES O/E#130 ASCE SAMPE ASMI SFPE ASME SME CETA SPE CSPE SWE
Visit our web page at www.svec.org
We appreciate the Silicon Valley / San Jose Business Journal’s participation in SVEC engineering activities.
We encourage you to sponsor Engineers Week 2006 Platinum Sponsor ($20,000) includes three student scholarships and special project support Gold Sponsor ($10,000) includes two student scholarships Silver Sponsor ($5,000) includes one student scholarship Bronze Sponsor ($2,500) includes special project support (Discover-E, MathCounts and Others) Blue Ribbon Sponsor ($1000)
For further sponsorship and banquet information call Jessica Teachworth, 408-742-4949, e-mail: [email protected] Tear here
2006 Engineers Week Banquet Reservation Form
$80.00 per person. Number of Attendees Total Amount $_________ No reservations accepted after 2/18/2006.
Name:
Company/Society:
Address:
City, State, Zip:
Phone:
Email:
Send Reservation forms and checks to: Silicon Valley Engineering Council c/o Society of Women Engineers P.O. Box 61333 Sunnyvale CA, 94088-1333
Make checks payable to: “Silicon Valley Engineering Council”
Dinner includes a fresh green salad, seasonal vegetables, dessert, coffee, and international teas. Enter number of each choice for dinner:
___ Chicken Breast Monterey ___ Pacific Swordfish Steak
___ Black Angus Prime Rib ___ Wild Mushroom Ravioli
Total Number of DinnersPlease include all names of attendees so name badges &
seating can be prepared in advance.
Credit Card reservations and more information available at www.svec.org/banquet
Silicon Valley Engineers Week Banquet 2006
Friday, February 24, 2006
Hyatt Santa Clara, Great America Parkway, Santa Clara (formerly the Westin Santa Clara)
F E B R U A R Y 2 0 0 5 V i s i t u s a t w w w . e - G R I D . n e t P a g e 5
March 20-24, 2006 @ the San Jose Convention Center
Next-gen game development will revolutionize every aspect of the gaming industry, and in turn influence other technology sectors that use advanced display, simulation, and interactive technologies. From increased production complexity, team sizes, and budgets to new ways to reach the mass market, GDC:06 will answer the questions critical to the industry's success. Industry luminaries will lead more than 300 lectures, tutorials, panels, roundtables and poster sessions covering all aspects of the industry for all platforms and all genres. Learn lessons from next-gen, handheld, and current game development, explore collaborations with the film industry and gain access to the people, technologies, and tools that define what's next for our industry.
25 Tutorials from which to choose. Exposition open Wed, March 22 - Friday, March 24
This year's GDC Tracks include the following: • Vision Track • Audio Track • Production Track • Programming Track • Business & Management Track • Game Design Track • Visual Arts Track
See the website for full details and a printable program.
If you are involved in implementing the Unicode Standard or working on internationalization, this is a must-attend conference – the only industry event focused on the Unicode™ Standard. The conference features a variety of tutorials and conference sessions that cover current topics related to Unicode, the web, software and internationalization. Unicode experts, implementers, clients and vendors are invited to attend this unique conference. Exchange ideas with leading experts, find out about the needs of potential clients, or get information about new and existing Unicode-enabled products. Visit the website to sign up for email updates about Unicode’06 and its tutorials and sessions. Organized by the Object Management Group, a not-for-profit consortium that produces and maintains computer industry specifications for interoperable enterprise applications, including MDA®, UML®, CORBA®, MOF™, XMI® and CWM™.
GDC Mobile 2006 March 20-21, Fairmont Hotel, San Jose
GDC Mobile is the definitive mobile gaming event for leading industry professionals looking to expand their knowledge of, and contacts within this exploding mobile entertainment sector. It provides mobile game developers from around the globe the opportunity to debate the future of their medium with executives from the leading mobile network operators, MVNOs, advanced technology providers and major console game publishers.
Serious Games Summit GDC March 20-21, Fairmont Hotel, San Jose
Serious Games are applications of interactive technology that extend far beyond the traditional videogame market, including: training, policy exploration, analytics, visualization, simulation, education and health and therapy. This forum allows game developers and industry professionals to examine the future course of serious games development in areas such as education, government, health, military, science, and corporate training.
Register by February 15th to save up to 35%! IEEE members - Use priority code IEMAPX to activate your registration. Academic, Student and Group rates are available. Visit:
www.gdconf.com
March 6-8, 2006 Hyatt Regency Hotel
Burlingame (S.F. Airport)
Tutorials 3/6; Sessions 3/7-8 Conference topics: • Web internationalization • Text and data mining • Security and phishing • New and upcoming technologies • Enterprise software in a global environment • Web services, SOA and Internationalization • Language tags and locales: implications for developers • Making scripts and languages accessible • Global development best practices • What’s new with Unicode 4.0; Successful Implementations • Internationalized Domain Names/Resource Identifiers • Tips, tricks and traps in developing international software • Globalizing your product: business cases and technical issues
Multi-attendee discounts. For more information and to register:
www.unicodeconference.org/ieee The Unicode Consortium is a non-profit organization founded to develop, extend and promote use of the Unicode Standard and related globalization standards.
F E B R U A R Y 2 0 0 5 V i s i t u s a t w w w . e - G R I D . n e t P a g e 6
Applicants for the position should be familiar with
the art, practice, and technologies of Undersea Warfare (Submarine warfare, Anti-submarine warfare and Mine warfare). Recruitment will be open to the ranks of Navy and Marine Corps officers who have discharged senior responsibilities in USW-related positions, as well as from academia, government or industrial laboratories. Candidates should have completed education at the Master’s level.
Experience in system development, requirements analysis and performance prediction for undersea warfare systems, undersea platform characteristics, multi-platform considerations, undersea warfare systems, for both littoral and blue water is required. The position is a non-tenure track or temporary assignment as Chair Professor of Undersea Warfare. The selected individual will concurrently serve as the Director of the Undersea Warfare Research Center. The position becomes available July 1, 2006, and is for two years with the possibility for renewal for an additional year. The stipend is negotiable within the salary range enjoyed by senior faculty.
This position is made available to the NPS by a
Memorandum of Understanding between the NPS and the Naval Undersea Warfare Center, Newport, R.I., the Chair sponsor. For more detailed information on the position, please contact Professor Roger Bacon at [email protected]. Please see the NPS Homepage at www.nps.navy.mil for additional information about NPS. The Undersea Warfare Curriculum Brochure and information is at www.nps.navy.mil/usw.
Interested individuals should contact Mr. Donald Aker, Technical Operations Manager, Naval Undersea Warfare Center, 1176 Howell Street, Newport, R.I. 02841. Tel: (401)832-8605; Fax: (401) 832-4660; E-mail [email protected] at the earliest opportunity. It is the intention to conduct interviews with final candidates no later than mid April. Please send both short narrative resume and a detailed chronological resume of education and experience by 13 March 2006.
San Francisco State University Assistant Professor Positions
The Engineering Department invites applications for two faculty positions: We offer a competitive salary, excellent benefits and an exceptional startup package. To apply, please send a detailed resume, statements of teaching and research interests, and a minimum of three recommendation letters to Chair, Hiring Committee, School of Engineering, San Francisco State University, 1600 Holloway Avenue, San Francisco, CA 94132. The review process will continue until the position is filled. SFSU is an equal opportunity/ affirmative action employer; applications are actively encouraged from underrepresented minorities and women.
For information about the SFSU School of Engineering, see engineering.sfsu.edu
Assistant Professor in Electrical Engineering
We invite applications for a tenure track Assistant Professor in Electrical and Computer Engineering, starting Fall 2006. Specific technical areas of interest include RF circuit design and analog electronics. We seek applicants who excel in both teaching and research. The successful candidate must be capable of pursuing externally supported research and possess a strong interest in teaching/developing new and existing courses and labs. A Ph.D. in EE or related field and an excellent record of publications in scholarly journals and conferences are required; industry experience is highly desirable.
Assistant Professor in Mechanical Engineering
We invite applications for a tenure track Assistant Professor in Mechanical Engineering, starting Fall 2006. The specific technical area of interest is materials engineering, including but not limited to the following: mechanical behavior of materials, bio-mechanical materials, electronic materials, nano materials,and composites or intelligent materials. We seek applicants who will excel in both teaching and research. The successful candidate must have the ability to pursue externally supported research, and have a strong interest in teaching/developing new and existing courses and labs in materials engineering and design. A Ph.D. or equivalent in Mechanical Engineering or a closely related field is required. Strong analytical skills with practical, hands-on design experience are highly desirable. Industry experience is a plus.
The Wayne E. Meyer Institute of Systems Engineering of the Naval Postgraduate School in Monterey is seeking a candidate for the Chair of Undersea Warfare, and Director, Undersea Warfare Research
F E B R U A R Y 2 0 0 5 V i s i t u s a t w w w . e - G R I D . n e t P a g e 7
Conference: February 6–9 Exhibition: February 7–8
Santa Clara Convention Center Developed specifically for
semiconductor and electronic design engineers, DesignCon is the essential design engineering event addressing the challenges facing these communities and providing the solutions attendees can implement immediately in their designs.
Exhibits feature leading organizations presenting EDA tools, test and measurement equipment, PCBs and related technologies, semiconductor components and IP, interconnect technologies, and more. Papers discuss leading-edge case studies, technology innovations, practical techniques, design tips and application overviews.
Technical tracks: • Chip-Level Functional Design • Chip-Level Physical Design and Verification • Power and Package Co-Design • PCB, Package, and Passive Technologies • Chip and Board Interconnect Design • High-Performance Backplane Interconnect Design • High-Speed Timing, Jitter and Noise • Power Integrity • Functional Verification • Business Issues
Technical Panels: Jitter and Its Challenges when Testing Serial Data Designs How to Choose Bypass Capacitors Strategies for Device Differentiation The Growing Impact of Power on SoC Design Ethernet Ecosystem Impact on Backplane & System Design OpenAccess Adoption and Proliferation Why So Many Chips Fail? Design Verification … and more
International Engineering Consortium www.iec.org
Keynote Speakers: Justin Rattner, Intel Sr Fellow, Corp Technology Group, Intel Brian Halla, Chmn. of the Board/CEO, National Semiconductor T.J. Rogers, Founder, President, CEO, Cypress Semiconductors Management Forum Panels: Engineering Education in the United States Today's DFM: the Supply Chain and its Effect on Designers Managing Verification ROI: Business Impact of Bug Escapes Make Technical On-Line Marketing Truly "Technical" The Growing Cost of EDA Tools: When to Build versus Buy The Business of DFM: Critical Issues and Implications … and more
Discover the latest tools and methods to overcome your design challenges and drive tomorrow’s innovations at DesignCon 2006. Semiconductor and electronic design engineers will find the right mix of technical education and networking opportunities, with access to cutting-edge design products.
Official Sponsor Diamond Sponsor
Arrive at the future of Design!
Visit: www.designcon.com
Free Exhibits Pass through February 6th!
DESIGN CHALLENGES SLOWING YOU DOWN? FIND YOUR SOLUTION AT DESIGNCON 2006
Ear ly-Bi rd D iscountRegister by March 3 and save $100
on any conference package!
GOLD SPONSOR SILVER SPONSOR MEDIA SPONSORS
CONFERENCE HIGHLIGHTS:• 12 Professional Development
Certificate Program tutorials, focus-ing on topics such as high-speeddesign, signal integrity, EMI,embedded passives, grounding,flex, HDI, lead-free and more
• 34 Technical Conference shortcourses on today’s hottest designand manufacture issues, processesand technologies
• Over 25 PCB industry experts willserve as conference speakers
For more information, downloadthe conference brochure today!
EXHIBITION HIGHLIGHTS:• Product and service Exhibition• General Sessions• FREE Tuesday, featuring a program
of free technical sessions, freeExhibitor Showcase presentationsand free admission to the exhibi-tion, Opening Night Reception andCasino Night
• 15th Anniversary Opening NightReception
• Casino Night• Year of the Designer Reception
For event details, visitthe conference Web site today!
F E B R U A R Y 2 0 0 5 V i s i t u s a t w w w . e - G R I D . n e t P a g e 9
7th International Symposium on
QUALITY ELECTRONIC DESIGN March 27-29, 2006 DoubleTree Hotel, San Jose
The International Symposium on Quality Electronic Design (ISQED) is a premier Manufacturing, Design & Design Automation conference, aimed at bridging the gap among electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues front-to-back. The conference attendees are primarily designers of the VLSI circuits & systems (IP & SoC), process/device technologists, semiconductor manufacturing specialists including equipment vendors, and those involved in the R&D and application of EDA Tools & design flows. ISQED emphasizes a holistic approach toward design quality and intends to highlight and accelerate cooperation among the IC Design, EDA, Semiconductor Process Technology and Manufacturing communities. The conference spans three days, Monday through Wednesday, in three parallel tracks, hosting over 100 technical papers, six keynote speakers, two panel discussions, workshops/tutorials and other informal meetings. ISQED proceedings are published by IEEE Computer Society and hosted in the digital library. Proceedings CD ROMs are published by ACM.
CONFERENCE HIGHLIGHTS TUTORIALS/WORKSHOPS ISQED 2006 is pleased to offer a single full-day tutorial track, presented by six experts in their respective fields. This tutorial track consists of two (2) major topics shown below. The first topic examines the critical and timely issues of "variability" and its impact in design with 65nm and finer CMOS technologies. The second topic explores the exciting field of emerging Nanoelectronic technologies and their application toward future ULSI designs. Variability and its Impact on Design Dr. Keith Bowman, Intel Corporation Dr. Michael Orshansky, University of Texas-Austin Dr. Sachin S. Sapatnekar, University of Minnesota
Emerging Technologies for VLSI Design Dr. Rajiv Joshi, IBM T J Watson Research Center, NY Dr. Kaustav Banerjee, University of California, Santa Barbara, CA Dr. Andre DeHon, California Institute of Technology, Pasadena, CA
PLENARY SESSIONS Two plenary sessions will be held on Tuesday and Wednesday mornings. Six industry & academia leaders will discuss the issues surrounding electronic design, design for yield and manufacturability and other critical topics from various points of view. Plenary keynote speakers are:
PANEL DISCUSSIONS ISQED is pleased to offer two high-power evening panel discussion sessions, where many leading experts, address the important issue of quality design. These panels would focus on the following topics:
Dr. Risto Suoranta, Principal scientist & Research Fellow, Nokia Dr. Tohru Furuyama, GM, Toshiba SoC Research and Development Center Dr. Di Ma, Vice President of Field Technical Support, TSMC Dr. Raul Camposano, Sr. Vice President, CTO, and GM, Synopsys Dr. Changhyun Kim, Vice President and Fellow, Samsung Electronics Dr. Philip Wong , Professor, Stanford University
1 Power management and optimization challenges for sub 90nm CMOS designs - What is the real cost of long battery life? 2 Soft IP Quality: Who is responsible to ensure quality throughout the design process?
LUNCHEON SPEECH Simplicity and Executability: Cornerstones of Quality Michael Keating, Synopsys
VENDOR EXHIBITION The exhibition is being held for the 1st time in conjunction with ISQED, features vendors offering design tools and methodologies in the area of design for manufacturing and quality. Exhibit floor will be open on Tuesday March 28, in parallel with technical sessions.
TECHNICAL SESSIONS ISQED Technical sessions start on Tuesday March 27, and continue until the afternoon of Wednesday, March 29. Beside the above plenary sessions, panel discussions, and workshops, the program consists of nineteen technical sessions featuring over 100 papers on various challenging topics related to design for manufacturability and quality. Detail program would be available on the web at www.isqed.org. • EDA Tools, Flows & IP Blocks; Interoperability (EDA) • Design for Manufacturability & Quality (DFMQ) • Design Verification and Design for Testability (DVFT) • Package - IC Design Interactions & Co-Design (PDI)
• Robust Device, Interconnect, and Circuits (RDIC) • Physical Design, Methodologies & Tools (PDM) • Effects of Technology on IC Design, Performance,
Reliability, and Yield (TRD) • System Level Design, Methodologies and Tools (SDM)
Please refer to ISQED web site at www.isqed.org for information regarding the tutorials, conference, and hotel registration. Direct all conference inquiries to [email protected]. Early registration is recommended to take advantage of the discounted registration fee.
www.isqed.org
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 10
Career-Advancement Short Courses with Labs March Technology Series
• Theoretical Aspects • Hands-on Experience • For working professionals • Preparation for Tomorrow • Excellent value; practical; timely topics • 5 Choices, all in the week of March 29, 2006
Digital Signal Processing -- 4-day class with labs: DSP System Design and Implementations
Overview: Today’s technology provides DSP processors that can be easily used to design very sophisticated products for instrumentation, control systems, communications, and wireless systems. This course presents DSP system design using programmable signal processors. Hands-on laboratory exercises are used to present the design and implementation aspects, using hardware and software tools for system implementation. The 5 laboratory sessions follow the lectures, where participants will apply system design concepts by designing, implementing, debugging and evaluating DSP schemes.
Digital System Design -- 4-day class with labs: FPGA DSP System Design
Overview: This course provides an in-depth and state-of-the-art coverage of the design and FPGA-based implementation of high-performance DSP systems. After presenting FPGA architectures and design tools by Xilinx and Altera, several hands-on design labs on DSP, digital communications and video/imaging will be covered, including FFT, FIR filters, error detection/correction circuits, modem, color space converter, and DWT (Discrete Wavelet Transform). Contents: Basic DSP/Communication theory, FPGA architecture/design tools, HDL (VHDL and Verilog), DSP-specific arithmetic circuits, hardware design of digital filters, FFT circuits, error detection & correction circuits, encryption/decryption circuits, and video/imaging circuits.
Analog/RF Design -- 4-day class with labs: Wireless Transmitters Overview: Power amplifiers play a major role in the overall performance of transmitters. There are a number of transmitter architectures that satisfy the linearity requirements of modulation techniques employed in short and long range communication applications. This exceptional course introduces modulation techniques and wireless standards, presents different transmitter and power amplifier architectures and compares the RF properties and performance of CMOS, SiGe and GaAs technologies. Covered are the critical relationships among linearity, power and spectral efficiencies, output power level and frequency of operation. The lab sessions involve using MATLAB/VerilogA simulators for behavioral characterization of transmitters by generating baseband signals of constant envelope and applying transmitter nonlinearities.
Department of Electrical Engineering
Review the full descriptions:
www.engr.sjsu.edu/eeshortcourse
for course overviews, prerequisites, instructor profiles, registration, map
Come to San Jose State! Easy access: class starts before most students arrive on campus, so parking in the 7th Street garage is a snap! Cost: $995 per course; $945 for IEEE Members (includes student notebook, lunches and refreshments. CDs with class notes and problem solutions for certain classes) Digital System Design -- 4-day class with labs: Embedded Systems and Embedded FPGAs Overview: This short course introduces the fundamentals of embedded system and embedded FPGA design methodology. It gives an overview of the technology, covers fundamentals and advanced issues, and gives hands-on experience with embedded FPGAs. The first part addresses fundamental concepts such as microprocessor architecture, bus functionality/arbitration, memory and I/O, interrupts, instruction set, real-time operating system (ROS), and drivers in a conventional embedded system. The second focuses on advanced embedded systems design including embedded FPGA implementation and practice. The lab provides hands-on experience with configuration of processor cores, developing IP with VHDL, writing drivers, system integration, and test. Students will be exposed to a learning experience balanced between fundamental and advanced issues, theoretical concepts and hands-on experiments that will allow them progress from novice to expert within a short time. Networking Engineering -- 4-day class with labs: Sensor Networks & Mobile Ad-Hoc Technology Overview: Mobile ad-hoc network technology with chemical, biological or solar sensors is destined to play an increasingly important role in military, security affairs, and in public. They lack any fixed infrastructure to support the mobility of the terminals in the network, and all the network intelligence must be situated inside the mobile devices that make up the network. There is a growing interest in identifying suitable wireless interfaces, network architectures, and transmitting facilities for them. This course covers architectures, protocols, hardware aspects, scalability, fault-tolerance and more.
• All classes are Wed, March 29, thru Sat, April 1 • All classes are 8:30 AM – 4:30 PM • For additional information, or assistance with
registration, contact Irma Alarcon de Rangel Telephone : (408) 924-3938
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 11
Visit www.embedded.com/esc/sv/
It's where great minds come looking for solutions and where solutions meet great minds. No matter what your role is in creating the technology of tomorrow, the Embedded Systems Conference is the place to start. All of our special events are free to registered attendees and range from keynote addresses to networking opportunities, from receptions to panel discussions, all designed to enrich your event experience. Having everyone and everything in one place at one time means comparing solutions is as easy as walking from one booth to the next. Keynote Address: Dean Kamen, Inventor and entrepreneur Tues April 4, Noon - 1:00 PM Panel Discussions Flash Memory: NOR vs. NAND or Code vs. Data Wednesday, April 5; 10 - 11 AM
Engineering Humanity: Technical Education in Crisis Thursday, April 6; 10:00 - 11:00AM
Win/Win Partnership of Academia and Industry Thursday, April 6; 5:15 – 6:15PM Plus Attendee Casino Night Reception Wednesday, April 5, 7:00 – 10:00PM ($65 in advance, $95 onsite) EE Times ACE Awards Honoring people, companies, and products
Register now to ensure your participation!
Co-Located Events (see next page for details): • 12th IEEE Real-Time and Embedded
Technology and Applications Symposium • D2M Conference
Visit the Exhibits (free admission)
The Embedded Systems exhibits floor features leading companies showcasing cutting-edge hardware, software, tools, and the full spectrum of system components. You will learn relevant new skills, meet and talk with vendors, network with peers, and develop new strategic partnerships – all under one roof, at one time, with both daytime and evening hours: Tues 1-7pm – Wed 10am-7pm – Thurs 10am-3:30pm /
Five Days. One Location.
Endless Possibilities. Technical Program
Monday & Friday full-day tutorials Practical, how-to classes: Architectural Design of Device Drivers • DSP Demystified • Embedded C • Embedded Linux Jumpstart • Scaling System Design • Real-Time Kernels • Real-Time UML • TCP/IP Networking
$695 for one full day (saving $300 before 2/7)
Over 100 three-hour and 90-minute Technical Classes on Tuesday through Thursday– see the Advance Program for listing/descriptions and times for each topic.
Open Forums: Shop Talks and Brownbag Lunches Free admission: discussions for swapping ideas with colleagues about common development problems and design challenges: Programming Conventions • Experiences in Embedded Linux Systems • Wireless Sensor Networks • The Human Aspect of Design and Development • Digital Video Compression and Codecs • Low-data-rate Wireless: Security, Stability, Suitability Six full DESIGN SEMINARS: • Analog Design (Tuesday – 2 tracks) • Linux Design (Tuesday, 2 tracks) • DSP Performance (Wednesday, 2 tracks) • Power Management (Wednesday, 2 tracks) • Consumer Video (Thursday – 2 tracks) • Wireless Networking (Thursday, 2 tracks)
… and the popular second annual Microprocessor Summit (Monday) – juried new-product introductions in AM; tracks on shipping products in PM
Ride light rail to the Convention Center in downtown San Jose
Flexible Registration Packages
• 1-day, 2-day, 3-day, full 5-day, or the ePass value
• Free Exhibits Pass (includes Keynote and Panels)
• Choose exactly what suits your needs and schedule
• Group rates – bring your team (save up to 35%)
Register by February 7th for early-bird rates!
Visit www.embedded.com/esc/sv/
for full details
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 12
Co-Located with the Embedded Systems Conference:
Real-time and Embedded Systems Infrastructure & Theory Ad-hoc networks of embedded computers; real-time resource management; real-time operating systems; distributed real-time information/databases; novel kernel-level mechanisms; real-time system modeling and analysis; formal methods; scheduling; and performance feedback control.
Embedded Applications Systems deployed in commercial industry, military, or other production environments, in automotive, avionics, telecom, industrial control, aerospace, consumer electronics, sensors.
Development, Verification, and Debug Tools for Real-Time and Embedded Systems Model-driven tools and techniques; compiler support; model-checkers, static analyzers, architecture description languages and tools; industrial experience with modeling and analysis; integrating components from multiple sources.
Embedded Systems Hardware/Software Co-Design Software architectures, design space exploration, synthesis, special-purpose function units, specialized memory structures, FPGA simulations, compilation for novel architectural aspects, software simulations of hardware components and static and dynamic power, timing and predictability challenges. Covering the spectrum – from Design to Manufacturing A2 Technologies' D2M 2006 and The Embedded Systems Conference pull the electronics industry together to deliver an industry-defining conference program. D2M 2006 connects industry decision-makers and the Who's Who of the design, power, test and measurement, green technology, embedded and component sectors of the electronics world. D2M is a market-focused, technology-driven conference, created to help today's design engineers find new solutions and products for everyday product development challenges. This three-day conference is packed with five design-focused seminars and an exhibition floor showcasing industry-leading solutions and products. • Registration includes admission to the D2M and the
Embedded Systems Conference exhibitions and receptions • All D2M sessions are held at the Crown Plaza Hotel,
across the street from the San Jose Convention Center and the Embedded Systems Conference
For detailed information, visit:
www.embedded.com/esc/sv/d2m
Additional Workshop Innovative Techniques for Certif ication of Embedded Systems Tutorials (Separate attendance allowed) • Extensible Frameworks for System-Level
Analysis of Real-Time Systems • Intrusion Tolerance: The Road to Security and
Dependability in Real-Time and Embedded Systems Free admission to the Embedded Systems Conference Exhibits
Early-Bird Rates through March 8th!
For full Advance Program, see:
www.rtas.org
For additional information or to receive a mailed advance program, call Linda Buss, 1-715-235-0487
April 4-6, 2006 Crown Plaza Hotel
Power Electronics Tuesday April 4 & Thursday April 6 Geared towards the application engineer, design engineer and program manager that uses power systems and power supplies in their work. The conference closely examines the growing complexity of product power requirements which necessitates a systems approach solution versus the traditional individual component model.
RoHS & Environmental Wednesday, April 5 In-depth information on the steps your company needs to qualify as RoHS and WEEE compliant. Experts from both industry and government give a detailed understanding of compliance issues as these initiatives reshape international business practices.
Design for Manufacturing Wednesday, April 5 The challenges of DFM, both present and future, to provide solutions to current issues and the information necessary to effectively plan for implementing process upgrades.
Emerging & Enabling Technology Wed, April 5 Eight critical briefings that examine the underlying technologies impacting our lives today and those that will enable the next generation of products and systems
Test & Measurement Wednesday, April 5 Engineers from the top test companies talking on the problems facing today's test engineer. This conference is the benchmark for practicing test engineers to get practical solutions: virtual instrumentation, data acquisition, test data management, EMC compliance testing, characterizing transient RF signals, signal integrity and LXI.
12th IEEE Real-Time and Embedded Technology and Applications Symposium
April 4 - 7, 2006 San Jose Fairmont Hotel
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 13
IEEE Professional Skills Courses High-Impact Communication
– Date/Time: Thursday, February 9, 8:30AM-4:30PM – Location: LSI Logic, Milpitas – Fee: $350 for IEEE Members; $425 non-members
Breakthrough Project Management – Date/Time: Thurs-Fri, Feb 9-10, 8:30AM-Noon – Location: Cypress Semiconductor, San Jose – Fee: $600 for IEEE Members; $650 non-members
Memory Power – Date/Time: Wed, February 15, 8:30AM-Noon – Location: Exar Corporation, Fremont – Fee: $300 for IEEE Members; $325 non-members
Speed Reading – Date/Time: Wed, February 15, 8:30AM-4:30PM – Location: Carl Zeiss Meditec, Dublin – Fee: $375 for IEEE Members; $425 non-members
Collaborative Negotiating – Date/Time: Thurs, February 16, 8:30AM-4:30PM – Location: Cypress Semiconductor, San Jose – Fee: $375 for IEEE Members; $425 non-members
Working Across Cultures – Date/Time: Thurs, March 9, 8:30AM-4:30PM – Location: LSI Logic, Milpitas – Fee: $375 for IEEE Members; $425 non-members
SCIENCE FAIR JUDGES NEEDED The IEEE sends judges to three science fairs in the Bay Area. We need all the people we can get. No experience necessary. Meals are provided. Come out and see what the kids are up to! San Mateo County Science Fair Tuesday February 7 & Wednesday February 8 Approximately 6 pm Hiller Aviation Museum 601 Skyway Road, San Carlos From San Francisco: Take Hwy 101 south to Holly Street/ Redwood Shores Pkwy exit. Go east onto Redwood Shores Pkwy. Turn right onto Airport Road. Turn right onto Skyway Road.
From San Jose: Take Hwy 101 north to Holly Street/Redwood Shores Pkwy exit. Go east onto Redwood Shores Pkwy. Turn right onto Airport Road. Turn right onto Skyway Road.
Contact Rosanna Lerma: [email protected]
SCV Chapters, Engineering Management & Components, Packaging and Manufacturing Technology Societies
Management Essentials – Date/Time: Thurs-Fri, Mar 16-17, 8:30AM-4:30PM – Location: Cypress Semiconductor, San Jose – Fee: $600 for IEEE Members; $650 non-members
Creative Problem Solving – Date/Time: Tues, April 11, 8:30AM-4:30PM – Location: LSI Logic, Milpitas – Fee: $375 for IEEE Members; $425 non-members
Leadership Skills – Date/Time: Wed, April 26, 8:30AM-4:30PM – Location: Exar, Fremont – Fee: $375 for IEEE Members; $425 non-members
Presentation Skills – Date/Time: Wed, May 3, 8:30AM-4:30PM – Location: LSI Logic, Milpitas – Fee: $450 for IEEE Members; $500 non-members
Improve your skills – register for one of these classes, or for others coming up this spring. Bring a team!
For complete course information, schedule, and registration form, see our website:
www.effectivetraining.com Santa Clara County Science Fair (Synopsys Challenge) Thursday March 9 10 am - 5 pm San Jose McEnery Convention Center 150 West San Carlos Street, San Jose
Come to the new South Hall (behind the Market Steet end of the main building). Check in at the Special Awards Judging table.
Schedule 10 am to 2 pm: project preview 2 pm to 5 pm: student interviews
Directions to the site: www.sjcc.com/getting_here/sjmccdrive.html Parking: www.sjdowntownparking.com Or take the light rail to the Convention Center
Contact Ken Doniger: [email protected] Santa Cruz County Science Fair Saturday March 11 8 am to 5 pm Santa Cruz Civic Auditorium 307 Church Street, Santa Cruz
Contact Keith Gudger: [email protected]
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 14
A Primer on the Food & Drug Administration: Lasers and Other
Radiological Health Products Speaker: Frank Eng, US FDA Time: Networking and Pizza Social at 7:00 PM,
Presentation at 8:00 PM Cost: none Place: National Semiconductor Credit Union
Auditorium, 955 Kifer Road, Sunnyvale RSVP: not required Web: www.ewh.ieee.org/r6/scv/leos
Frank Eng is a Medical Device Specialist and Electro-Optics Specialist at the Food and Drug Administration, where he has worked for 33 years. Frank performs inspections of firms that manufacture medical devices and laser products, for conformance to FDA's quality system regulations for medical devices, and FDA's laser product performance standards for laser products. He also has a background in other FDA-regulated products such as: human foods, human drugs, biologics, and bio-research (sponsor, monitor, clinical investigators and institutional review boards).
Tonight's presentation is "A Primer on the Food & Drug Administration," with some emphasis on Radiological Health Products, in general, and on Laser Products in particular.
TUESDAY FEBRUARY 7SCV Lasers and Electro Optics
Patent Agent Jay Chesavage, PE
MSEE Stanford 3833 Middlefield Road, Palo Alto 94303
www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 15
MultiLayer Ceramic Capacitor (MLCC) Value Drift
and Embedded Passives
Speakers: Dr. Daniel N. Donahoe, Exponent Inc,
and Dr. Nicholas Biunno, Sanmina-SCI Time: Seated dinner at 6:30 PM; presentations
at 7:30 PM Cost: $25 if reserved by Feb 5; $30 at the door;
presentation-only is free Place: Ramada Inn, 1217 Wildwood Ave (Fwy
101 frontage road, between Lawrence Expy and Great America Pkwy), Sunnyvale
RSVP: Please reserve and pay in advance using our PayPal on-line system or email Janis Karklins at [email protected]
Web: www.cpmt.org/scv Dr. Daniel N. Donahoe is a Managing Engineer
in Exponent’s Mechanical Engineering and Materials/Metallurgy practice. Dr. Donahoe has over two decades of industrial experience working with defense electronics and commercial electronics. Prior to joining Exponent, he has been employed at Lockheed, Motorola, Ford Aerospace, Teledyne, Compaq Computer and Iomega, and the University of Maryland’s industry and government sponsored CALCE Electronic Products, and Systems Center. His functional assignments include work as a design engineer, reliability engineer, thermal engineer, manager, technologist, and scientist. In military electronics he worked on electronics exposed to extreme environments ranging from the high acceleration loads of gun launch to thermal challenges faced in life support and the design of radar systems. In addition to electronic products exposed to exotic environments, he has worked on cost-driven commercial electronics products such as cooling of computer components. He has worked on integrating rack and stacked electronics into facilities, especially focusing on the design of HVAC (Heating, Ventilation and Air Conditioning). His electronic packaging analysis skills include thermal analysis, stress and dynamics analysis and failure analysis.
(continued, next column)
As IC progress drives more functionality onto
each IC, fewer ICs are typically placed on each PCB. In addition to this trend, ever-increasing operating frequencies and lower IC voltages require more passive components. As a result, the multilayer ceramic capacitor (MLCC) has become the most common component used in digital electronics.
The capacitor industry has not stood still while the IC industry moved forward. MLCCs have continued to shrink in size, primarily to satisfy the requirements driven by modern handheld products such as cell phones. In addition, an almost 10 times market spike in the price of palladium (electrodes were made of silver and palladium are called precious metal capacitors) forced the industry to transition to nickel electrodes. The use of nickel electrodes in a MLCC is termed base metal electrodes (BME). Today, most MLCCs are BME.
Humidity testing for both precious metal electrode and base metal electrode (BME) capacitors showed that the precious metal capacitors aged according to a well known aging mechanism, but the BME capacitors degraded to below the failure criterion at 500 hours of exposure. The reasons for this new failure mechanism are complex. This talk will outline the testing and provide a theory why this degradation was witnessed. Standard testing protocols will likely not uncover this problem.
(continued …) His Ph.D. dissertation on ceramic capacitors included failure analysis work using modern tools of failure analysis including the environmental scanning electron microscope (ESEM™), electron backscatter diffraction (EBSD) and focused ion beam (FIB). Dr. Donahoe has worked on several industry standards related to electronics. He has also served as an Associate Editor of the IEEE Transactions on Components and Packaging Technologies for seven years.
Dr. Nicholas Biunno is a Principal Scientist for
the PCB Division of Sanmina-SCI. Current projects include embedded passives, new product development and high speed electrical properties characterization for PCB laminates. He is a member of CPMT's Technical Committee on Discrete and Integral Passives.
WEDNESDAY FEBRUARY 8SCV Components, Packaging & Manufacturing Technology
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 16
Behavioral Modeling of Microwave
Devices and Circuits Speakers: Dr. David E. Root Agilent Technologies Time: social/refreshments 6:00 PM; presentation
at 6:30 PM Cost: $25 if reserved by Feb 5; $30 at the door;
presentation-only is free Place: SC12-Auditorium, Intel Corp., 3600 Juliette
Lane, Santa Clara RSVP: not required Web: www.mtt-scv.org
David E. Root (IEEE M’89-SM’01-F’02) received B.S. degrees in physics and mathematics, and, in 1986, the Ph.D. degree in physics, all from MIT, Cambridge, MA, USA. He joined the Microwave Technology Center of Hewlett-Packard Company (now Agilent Technologies, Inc.), Santa Rosa, CA in 1985. He originated and co-developed the HPFET family of measurement-based transistor and diode models (“Root models”). He has twice managed the Computer Aided Engineering, Modeling, and Advanced Characterization Group of the Microwave Technology Center, where he led the establishment of capabilities including characterization and modeling with advanced pulsed bias, pulsed S-parameters, and large-signal vector network analyzer instruments for proprietary R&D. He managed and co-developed the Agilent HBT compact model for III-V hetero-junction bipolar transistors. He is presently Principal Research Scientist at Agilent’s Technology, Components, and Architecture Labs in Santa Rosa. His current responsibilities include nonlinear behavioral and device modeling, large-signal simulation, and nonlinear measurements for new technical capabilities and business opportunities. Dr. Root was a Visiting Scholar and Lecturer at the University of California at San Diego (UCSD) for the fall, 2005 quarter.
Dr. Root is a member of the IEEE MTT-S Committee on CAD (MTT-1) and the Technical Program Committee of the International Microwave Symposium. He is a reviewer for the IEEE Transactions on Microwave Theory and Techniques. He is co-editor of the recent book Fundamentals of Nonlinear Behavioral Modeling for RF and Microwave Design, Artech House, 2005. He is a Fellow of the IEEE.
This lecture introduces general concepts and specific techniques for effective (efficient, general, and accurate) nonlinear behavioral modeling of microwave semiconductor devices and functional circuit blocks. A behavioral model is a simplified but accurate model of a lower-level component in the design hierarchy that simulates efficiently at the next higher level of abstraction. A unified treatment at both the device and functional block level is a distinguishing feature of this presentation. So too is the application to behavioral models constructed from real measurements and also from simulations starting from a detailed (complex) model. The emphasis is placed on the combination of nonlinearity and dynamics. Nonlinearity includes distortion, clipping, etc. Dynamics includes frequency-dependent effects and long-term memory from a variety of physical origins. The three major components of behavioral modeling will be reviewed. The first is the model formulation. Techniques in the time, frequency, and mixed domains will be reviewed. The second component is experiment design, the set of excitations required to elicit the dynamical and nonlinear responses of the component necessary to model it for the relevant applications. The third component is model identification, the algorithms for relating the experimentally obtained data to the model coefficients. Some of the approaches covered can be considered extensions from linear techniques, such as conventional s-parameters. Others are fundamentally nonlinear in nature. The need for novel nonlinear microwave instrumentation, not generally available from commercial manufacturers, will be described. It is demonstrated that great benefits can be achieved by formulating the models in a mathematical language closely related to the advanced simulator algorithms used to most efficiently solve the relevant problem.
THURSDAY FEBRUARY 9
SCV Microwave Theory and Techniques
Board Logic Systems
Complete Product Solutions Provider TM
Experienced consultants in the fields of: • Board & Verilog Design • Debug and Test • Signal Integrity • EMI • Power Electronics • Layout • Software Development • Documentation
www.boardlogics.com
[email protected] (650) 867-0869
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 17
Computation with Information Described in Natural Language --
The Concept of Generalized-Constraint-Based Computation
Speaker: Lotfi A. Zadeh, Department of EECS, University of California, Inventor of Fuzzy Logic
Time: 3:00 - 5:00 PM Cost: none Place: Bldg. 943, Eagle Room, NASA Research
Park, Moffett Field (directions on web) RSVP: not required Web: www.e-grid.net/docs/0602-scv-cis.pdf
Lotfi A. Zadeh joined the Department of Electrical Engineering at the University of California, Berkeley, in 1959, and served as its chairman from 1963 to 1968. Earlier, he was a member of the electrical engineering faculty at Columbia University. In 1956, he was a visiting member of the Institute for Advanced Study in Princeton, New Jersey. In addition, he held a number of other visiting appointments, among them a visiting professorship in Electrical Engineering at MIT in 1962 and 1968; a visiting scientist appointment at IBM Research Laboratory, San Jose, CA, in 1968, 1973, and 1977; and visiting scholar appointments at the AI Center, SRI International, in 1981, and at the Center for the Study of Language and Information, Stanford University, in 1987-1988. Currently he is a Professor in the Graduate School, and is serving as the Director of BISC (Berkeley Initiative in Soft Computing).
What is computation with information described in
natural language? Here are simple examples. I am planning to drive from Berkeley to Santa Barbara, with stopover for lunch in Monterey. It is about 10 am. It will probably take me about two hours to get to Monterey and about an hour to have lunch. From Monterey, it will probably take me about five hours to get to Santa Barbara. What is the probability that I will arrive in Santa Barbara before about six pm?
Computation with information described in natural language, or NL-computation for short, is a problem of intrinsic importance because much of human knowledge is described in natural language. It is safe to predict that as we move further into the age of machine intelligence and mechanized decision-making, NL-computation will grow in visibility and importance. A natural language is basically a system for describing perceptions. Perceptions are intrinsically imprecise, reflecting the bounded ability of sensory organs, and ultimately the brain, to resolve detail and store information. Semantic imprecision of natural languages is a concomitant of imprecision of perceptions.
Our approach to NL-computation centers on what is referred to as generalized-constraint-based computation, or GC-computation for short. A generalized constraint is expressed as X isr R, where X is the constrained variable, R is a constraining relation and r is an indexical variable which defines the way in which R constrains X. The principal constraints are possibilistic, veristic, probabilistic, usuality, random set, fuzzy graph and group. Generalized constraints may be combined, qualified, propagated, and counter propagated, generating what is called the Generalized Constraint Language, GCL. The key underlying idea is that information conveyed by a proposition may be represented as a generalized constraint, that is, as an element of GCL.
The generalized-constraint-based computational approach to NL-computation opens the door to a wide-ranging enlargement of the role of natural languages in scientific theories. Particularly important application areas are decision-making with information described in natural language, economics, risk assessment, qualitative systems analysis, search, question-answering and theories of evidence.
THURSDAY FEBRUARY 9
SCV Computational Intelligence
ANSYS Channel Partner
• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses
Ozen Engineering (408) 732-4665
[email protected] www.ozeninc.com
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 18
Distributed Wireless Communication: A Shannon-
Theoretic Perspective on Fading Multihop Networks
Speakers: Sumeet Sandhu, PhD & Ozgur Oyman,
PhD, Communications Technology Lab, Intel Time: 6:30 PM fast food & drinks,
Presentation at 7:00 PM Cost: $1 Donation Recommended towards
Refreshments Place: National Semiconductor Credit Union
Building (Bldg 31), 955 Kifer Rd., Sunnyvale RSVP: not required Web: www.e-grid.net/docs/0602-scv-sps.pdf
Sumeet Sandhu is the Principal Investigator for a
Strategic Research Project on “Distributed Communication” in the Corporate Technology Group at Intel Corporation in Santa Clara. Sumeet holds a PhD from Stanford University and a BS and MS from the Massachusetts Institute of Technology. She held positions at Iospan Wireless, Sprint Corporation, Hughes Research Laboratories and Bell Laboratories prior to Intel. She was one of the initiators of MIMO-OFDM research at Intel, and invented a space-frequency bit interleaver for multiple spatial streams that is expected to be a key mandatory portion of the upcoming 802.11n standard.
Ozgur Oyman is a research scientist in the Corporate Technology Group at Intel Corporation in Santa Clara. He holds M.S. (2002) and Ph.D. (2005) degrees from Stanford University and a B.S. (2000) degree from Cornell University. He was a visiting researcher at the Communication Theory Group within the Swiss Federal Institute of Technology (ETH Zurich) in 2003. His prior work experience includes internships at Qualcomm (2001) and Beceem Communications (2004).
Distributed communication is an advanced
wireless technology that allows cooperative communication by ensembles of wireless devices. Devices located close to the source cooperate by re-encoding and forwarding packets, and devices located close to the destination cooperate by sharing received packets. Such cooperation provides diversity gains against wireless channel impairments such as fading, shadowing and path-loss. It improves performance over and beyond what is possible with traditional point-to-point links in a flexible manner by harvesting diversity in the network.
The simplest form of cooperation is a multi-hop network where nodes cooperate by forwarding packets one at a time. We consider a fading multihop network with a single active source-destination pair connected via multiple hops over a row of intermediate relays. We use Shannon-theoretic tools to analyze the tradeoff between energy efficiency and spectral efficiency (known as the power-bandwidth tradeoff) for a simple communication protocol based on time-division decode and forward relaying. It is commonly believed that communication over multiple hops suffers in fading channels due to the worst link limitation. In contrast, our results indicate that hopping can significantly improve the outage behavior over slow-fading networks and stabilize links against random channel fluctuations. We prove that there exists an optimal number of hops that minimizes the end-to-end outage probability. Finally, we provide numerical performance comparisons based on realistic channel models. The talk also covers a more advanced form of cooperation known as virtual MIMO, and its advantages as well as distributed communication protocols.
MMOIN
MONDAY FEBRUARY 13
SCV Signal Processing
Valon Technology, LLC
valontechnology.com
RF and Wireless Product Design & Development
- System Engineering - Test & Measurement - Schematic Capture & PCB layout - Expert Witness
Redwood City (650) 369-0575
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 19
Biometrics: A Brief History and Review of Current Programs
Speaker: Dr. James L. Wayman, Director,
Biometric Identification Research Program, San Jose State University
Time: Dinner 6:15 PM, Presentation 7:30 PM Cost: none (parking is free after 4 PM) Place: Dinner with the speaker in the Stanford
Hospital cafeteria; Presentation in Clark Center Auditorium (see map on website)
RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs/
pages/upcoming.html
Dr. Jim Wayman is Director of the Biometric Identification Research Program of San Jose State University. He received the Ph.D. degree in engineering in 1980 from the University of California, Santa Barbara. In the 1980s, under contract to the U.S. Department of Defense, he invented and developed a biometric authentication technology based on the acoustic resonances of the human head. He joined San Jose State University in 1995 to direct the Biometric Identification Research Program, serving as Director of the U.S. National Biometric Test Center at San Jose State from 1997-2000. He has written dozens of book chapters and journal articles on biometrics and is co-editor of J.Wayman, A. Jain, D. Maltoni and D.Maio (eds) Biometric Systems (Springer, London, 2005). He is a Fellow of the British Institution of Electrical Engineers, a "Principal UK Expert" on the ISO/IEC JTC1 SC37 standards committee on biometrics, a "core member" of the U.K. Biometrics Working Group, a member Biometrics Executive Committee of the U.K. Home Office, a member of the EC-funded BioSecure Network of Excellence and a member of the International Board for External Review and Validation of the US Dept of Homeland Security. He is also a member of the U.S. National Academies of Science/National Research Council Committee "Whither Biometrics?" and previously served on the NAS "Authentication Technologies and their Implications for Privacy" committee. He holds 4 patents in speech processing and has served as a paid biometrics advisor to eight national governments. His Erdos number is four.
Although it was the Frenchman Alphonse Bertillion
who developed the first scientific method of recognizing people in the1870s, it was the British who simplified and advanced the art and science of human recognition with the development and promotion of fingerprinting in the decades that followed. It took Californians, however, to apply computers to automating these processes in the 1960s. In this talk, we will review British and Californian contributions to automated human recognition (a field now called "biometrics"), explain a bit about the recent algorithmic approaches to face and iris recognition, and discuss current national biometric programs within both governments.
WEDNESDAY FEBRUARY 15SCV Engineering in Medicine and Biology
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 20
A Fourth Generation 1.8GHz Dual-core SPARC V9
Microprocessor Speaker: Anand Dixit, Ph.D. E.E. Student,
Stanford University Time: 6:00 PM refreshments,
Presentation 6:30 PM Cost: donation for food Place: National Semiconductor Building 31
Auditorium, 955 Kifer Road, Sunnyvale RSVP: Please reserve by email to
[email protected] Web: www.ewh.ieee.org/r6/scv/ssc
Anand Dixit received the Bachelor of Technology degree from Indian Institute of Technology, Kanpur, India, and the M.S. degree from Carnegie Mellon University, Pittsburgh, PA, both in electrical engineering, in 1996 and 1998, respectively. He is currently working towards the Ph.D. degree in electrical engineering at Stanford University.
From 1998 to 2000 Anand Dixit was with National Semiconductor where he worked on touch-screen controllers, PLLs and other analog designs for the Information Appliances group. Since 2000 he has been with Sun Microsystems, where he is responsible for the I/O designs on UltraSparc III and UltraSparc IV processors. His current interests include high-speed interface design, modern integrated circuit processing and processor test/debug. He holds a US patent on a PLL lock detector.
Mr. Dixit was a recipient of the National Talent Search Scholarship from the Government of India between 1990 and 1996.
This fourth-generation processor combines two
enhanced third-generation cores using an advanced 90-nm dual-Vt, dual-gate-oxide technology. Hardware additions feature expanded caches and inclusion of a 2-MB Level-2 cache and a Level-3 tag. Layout was completely redrawn to optimize the design for manufacturability and performance in the latest technology. Special emphasis was placed on library development to improve automation and assist in custom design. The memory design methodologies were completely updated to make quality design simpler and more robust.
The chip operates at 1.8 GHz while dissipating 90 W of power at 1.1 V. Due to the big die size and complexity, converting a microprocessor design into a successful product is always a challenge - especially at new technology nodes. The second part of the talk will focus on the productization issues.
THURSDAY FEBRUARY 16SCV Solid State Circuits
Bernie Siegal
650-961-5900
[email protected] www.thermengr.com
Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 21
OEB Communications
Wireless Sensor and Control Networks
Speaker: Rick Enns, Vice President of Standards
and Technology, Dust Networks Time: 6:30 PM pizza and drinks, Presentation
7:00 PM Cost: none Place: Bishop Ranch 1, 6101 Bollinger Canyon
Road, San Ramon RSVP: Please reserve (by Feb. 15) by email to
Michael Audeh, [email protected] or call 510-305-6022
Web: www.comsoc.org/oeb
Rick Enns has over 26 years of experience in developing wireless and cable networking technologies and driving standards. Dust Networks provides hardware and software for wireless mesh networks used for sensor and control applications in industrial and building automation. Dust is the leading innovator of highly reliable, low power networks. Rick’s work at Dust concentrates on the standardization of wireless sensor networks and the development of new networking technologies. Prior to joining Dust Networks, Rick served as Vice President and Chief Technical Officer for Hybrid Networks where he led the hardware and software design efforts that pioneered cable and wireless modem systems. Rick also directed the Hybrid Networks group that drove standards in IEEE 802.14 and 802.16. At Hughes LAN Systems, Rick served as Director of Hardware Development and held various engineering and management positions at Stratacom, Bell Northern Research, Siemens Corporation, and SRI International. Over the years he has authored 12 patents in the area of cable and wireless Internet access systems, ATM technology, and integrated voice and data systems. He has consulted for a range of wireless networking products from enterprise WiFi switches to WiMAX micro-base stations. Rick holds an MSEE from Stanford University, an MS in Physics from University of Washington, and a BS from UC San Diego.
Wireless sensor and control networks are the next
new market for data communications. The networking requirements are driving new technologies. The presentation will outline the diverse markets serviced, the technologies being employed and the standards that are emerging.
THURSDAY FEBRUARY 16
Mixed-Signal IC Development
• From Inception to Production Transfer • Turnkey, Design Services & Consulting • Design Reviews & TroubleShooting
Mixel, Inc. Excellence in Mixed Signal Design
(408) 274-2736 [email protected] www.mixl.com
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 22
Magnetic Biochips: Laboratory Curiosity or Killer App?
Speaker: Prof. Shan X. Wang, Materials Science &
Engineering and Electrical Engineering; Director, Center for Magnetic Nanotechnology, Stanford University
Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM
Cost: none Place: KOMAG, 1710 Automation Parkway,
San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag
Dr. Shan Wang currently serves as the director of the Center for Magnetic Nanotechnology and is an associate professor in the Department of Materials Science & Engineering and jointly in the Department of Electrical Engineering at Stanford University. He is also with the Geballe Laboratory for Advanced Materials, and is affiliated with Stanford Bio-X Program. His current research interests lie in magnetic nanotechnologies in general and include bio-magnetic sensing, magnetic microarrays, novel magnetic nanoparticles, magnetoresistive materials and spin electronics, magnetic inductive heads and soft magnetic materials, as well as magnetic integrated inductors. He has published over 100 papers and holds 11 patents (issued and pending) on these subjects. He and Alex Taratorin also published a book titled "Magnetic Information Storage Technology" through Academic Press. Dr. Wang was among the inaugural group of Frederick Terman Faculty Fellows at Stanford University (94-97), and an IEEE Magnetics Society Distinguished Lecturer (2001-2002). He also received an IBM Partnership Award in 1999, and was selected to the CUSPEA program organized by Nobel Laureate T. D. Lee in 1986. He has served the IEEE Magnetics Society in many capacities, most recently as the Finance Chair (2002-3), Local Chair for TMRC’03 and 05, and Program Chair for Intermag’06. He received the B.S. degree in physics from the University of Science and Technology of China in 1986, the M.S. in physics from Iowa State University in 1988, and the Ph.D. in electrical and computer engineering from the Carnegie Mellon University (CMU) at Pittsburgh in 1993.
We are developing a sensitive and quantitative
DNA detection system which is based on magnetic nanotags (nanoparticles) and spin valve sensor arrays. The magnetic biochips can be used for rapid and portable DNA fingerprinting, pathogen detection, and functional genomics. We have designed and fabricated several types of such magnetic biochips (MagArray) consisting of arrays of spin valve detectors with appropriate dimensions, surface chemistry, and microfluidics. An ASIC circuit with a footprint of 2 mm by 2 mm and including row and column addressing decoders and parallel fast readout schemes have been designed and fabricated. The MagArray chips feature redundant and high density of sensors, with a sensor density as high as 0.1 million sensors per squared cm. An advanced electronic test station has been set up as a demonstration vehicle for the integrated evaluation of our magnetic biochips with the custom magnetic nanotags and DNA-based biochemistry. Real-time detection of biological events has been successfully performed in laboratories, suggesting that MagArray holds unparalleled capabilities as compared to existing biochip technologies. Several practical issues need to be addressed in time for MagArray to emerge as a killer application for biomedicine in the near future.
TUESDAY FEBRUARY 21SCV Magnetics
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VoIP - Implementing the New Phone System
Speaker: Dr. Ali Kujoory, Ad. Professor, Computer
Engr. Sci., Sonoma State University Time: Complementary dinner and Presentation at
6:30 PM Cost: none Place: The Public Utilities Commission,
505 Van Ness Av, San Francisco RSVP: Please reserve by phone (415-209-6638)
or email to Michael Butler at [email protected]
Web: www.ieee.org/sfcomsoc
Dr. Ali Kujoory is a consultant and an adjunct Professor at the Dept. of Computer Engineering Sciences, Sonoma State University. Prior to joining SSU, he was a Lead Systems Architect at Alcatel, doing forward-looking work on Voice over Packet, Passive Optical Network, Next Generation SONET, and reliability. Before Alcatel, he was a Distinguished Member of Technical Staff at AT&T Bell Laboratories in NJ for sixteen years, doing research on real-time applications over the Internet. While at AT&T, he was also an Adjunct Professor of EE and CS programs at the Stevens Institute of Technology in NJ. Dr. Kujoory, a Senior Member of the IEEE, received the Millennium Award in 2000 and IEEE Section awards for contributions to the IEEE NJ Coast Section from 1996-2000. He received the AT&T Standards Recognition Award in 1997. He has published and presented numerous papers in technical journals and conferences and holds a number of patents in the areas of IP applications, QoS and broadband technologies. He has his M.S. and Ph.D. degrees in EE from the University of Pennsylvania.
Traditionally, voice and data have used separate networks. With VOIP, the provider can consolidate the delivery of voice and data over a single network, e.g., the Internet, and cut the capital and operation expenses (CAPEX/OPEX) significantly. The Internet Protocol (IP) is, however, a connectionless technology and provides a best-effort service that results in unacceptable voice degradations compared with the legacy Public-Switched Telephone Network (PSTN). Additionally, the network devices need other protocols to provide call setup, call control, and routing to allow reliable end-to-end calls over concatenated reliable and unreliable networks and to internetwork with the legacy PSTN. In this overview, we discuss the voice characteristics and requirements, some of the mechanisms to deal with the impairments, the protocols that are used in the next generation networks for the VOIP, and the security issues.
Join us at the S.F. ComSoc meeting for
professional networking and interesting industry discussions. Make industry contacts, and maybe volunteer to make the SFComSoc active, rewarding and relevant for your needs.
The ‘Roundtable’ format we use includes informal
presentations. We prefer people who have interest and knowledge of topics and can lend some real-world experiences. You will benefit by hearing other experiences and generally networking with people with similar interests and problems.
You will also benefit from the complimentary
pizza/salad/desert dinner. (the reason for the RSVP)
TUESDAY FEBRUARY 21SF Communications
MET Laboratories
EMC – Product Safety
US & Canada
• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)
Facilities in Union City, Santa Clara
www.metlabs.com [email protected] 510-489-6300
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 24
Status on Immersion Lithography Processing
Speaker: Ivan Pollentier, IMEC (Belgium) Time: Pizza social at 6:00 PM;
Presentation at 6:15 PM Cost: none Place: National Semiconductor Corp. Building 31
Large Auditorium, 955 Kifer Road, Sunnyvale
RSVP: not required Web: www.ewh.ieee.org/r6/scv/eds/
Ivan Pollentier joined IMEC in 1993 after
receiving a PhD in Physics Engineering at the University of Gent (Belgium). Initially, he was responsible for the support of lithography in the IMEC's pilot line. Since 1996 he moved to lithography process development, where he was involved in integrating I-line, 248nm and 193nm lithography in IMEC's mainstream technologies. Currently he is managing the lithography integration and metrology group within the lithography department, responsible for lithography processes and metrology used at IMEC.
.
Compared to conventional dry lithography,
immersion lithography has introduced water as a liquid material in between the lens and photoresist material in order to enhance the imaging performance and to open ways for further scaling using an existing exposure wavelength. Due to the contact of water with photoresist material, several processing issues can be expected, such as generation of defects, diffusion of species from the resist into water, diffusion of water into the resist, etc, as well as its impact on CD-control, overlay control and defectivity. In this presentation, an overview will be given on its status at IMEC and key issues in the development.
TUESDAY FEBRUARY 21SCV Electron Devices
Digital Chip Design Services
ASIC Design • EDA Evaluation • Verilog HDL • Synthesis • Design for Visibility • Timing • Scan • Verification • Low Power techniques • Power Analysis • BIST • DFT • ATPG • Silicon Debug
Testable logic for high-volume production with low DPM
Contact Mahesh Siddappa ME (CS, India), MS (EE, SUNY at Stony Brook)
[email protected] 408-981-6612
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 25
SCV Education Education Challenges in the Age
of Nano-Scale Technologies Speaker: Dr. Ali Iranmanesh, Chairman and CEO,
Silicon Valley Technical Institute Time: Pizza/drinks at 6:30 PM;
Presentation at 6:45 PM Cost: none Place: Silicon Valley Technical Institute, 1762
Technology Drive, Suite 227, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/es
Dr. Ali Iranmanesh received his MS and Ph.D. in Electrical Engineering and Physics from Stanford University in 1983, and Master in Business administration from San Jose State University in 1995. During the past 3 decades he has been actively involved with many leading Silicon Valley companies such as Advanced Micro Devices, Fairchild, National Semiconductor, and Synopsys. He is a semiconductor industry veteran, having participated in the development of many generations of advanced semiconductor technologies and design methodologies that have resulted in many advancements in the field as well as earning him nearly 50 US and international patents. In 1999 he founded the International Society for Quality Electronic Design (ISQED), a multidisciplinary international organization devoted to the advancement of design for quality and manufacturing. The ISQED conference, which is now in its seventh year, has been a leading design and design automation conference with worldwide reputation and participation. In 2000 he joined the founding team of Tavanza Inc. a wireless communication startup that was successfully acquired by Anadigics Inc.
Dr. Iranmanesh is the chairman of Ascend Design Automation, and the founder and Chairman of Silicon Valley Technical Institute (SVTI) where he is now serving as the president and CEO. He is a Senior IEEE member, senior member of the American Society for Quality, and the Vice Chair of the IEEE Education Society Chapter in the Santa Clara Valley.
Over the past several decades, advances in
semiconductor technology and manufacturing – combined with a relentless device-scaling trend – have resulted in a phenomenal increase in the transistor count per chip. This powerful trend (known as Moore’s Law) has provided the fuel for economic growth and resulted in tremendous gains for the electronics industry in much of the industrial world. As the obstacles to traditional device scaling are mounting, emergence of Nanotechnology and its impact on Nanoelectronics promises the dawn of a new and exciting age. Nanotechnology represents a powerful set of technologies destined to shape the future of the electronics industry and create a vast array of other new and exciting industries. Throughout all these years, universities and educational organizations – which have been training generation after generation of engineers for the micrometer era – have remained relatively unchanged. However, due to recent advancements in technology and business globalization, these organizations too are finding themselves in the midst of powerful transforming changes; such changes are bound to raise many challenges and threaten to evolve the landscape of higher education for the years to come. This presentation explores these topics and examines how they could alter the future of education in the era of the nanometer generation.
WEDNESDAY FEBRUARY 22
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Pad-Mounted Distribution Substations
Speaker: John Wood, Sr. Consulting Electrical
Engineer, PG&E Time: 12:00 Noon Cost: $6.00 (includes lunch) or Free (no lunch) Place: PG&E Building, 77 Beale St. Room 308,
San Francisco RSVP: by 2/20 to Curt Irwin, [email protected],
(415) 973-8171 Web: www.e-grid.net/docs/0602-sf-pes.pdf
John Wood manages the distribution protective
and switching equipment for PG&E. He earned his electrical engineering degree from the University of Nevada and his MBA degree from John F. Kennedy University. He is a Registered Professional Engineer in the State of California. John is very active in IEEE, and is currently a Subcommittee Chair for the C37 Standards Switchgear Committee.
The distribution pad-mounted substation is a
unique design and concept utilizing metal-enclosed equipment. In comparison to the standard outdoor substation design, the pad-mounted substation has many benefits including: lower cost, less construction time, aesthetic improvement, less land requirement, improved reliability, ease of operation, ease of maintenance, etc. The first pad-mounted substation was installed in the Pacific Gas and Electric Company (PG&E) system in late 2005 with great ease and success.
John will go through the development and design of the pad-mounted substation. Actual photographs of PG&E’s first installation at Forest Substation will be shown to give the audience a real live view of how the substation looks and how it is installed.
THURSDAY FEBRUARY 23
SF Power Engineering
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 27
The "D" in DFM: Design For Manufacturability
Speaker: Carlo Guardiani, PDF Solutions Time: 6:30 PM fast food and drinks,
7:00 PM Presentation Cost: none Place: Cadence Design Systems, Building 5,
2655 Seely Avenue, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/cas
Carlo Guardiani is Senior Director of DFM Engineering and head of the Italian Operations for PDF Solutions, having joined PDF in March of 1999 as Director of Statistical Design. Prior to PDF, he held multiple positions at ST Microelectronics in Agrate (Italy) and Grenoble (France) culminating in being the R&D manager of advanced research in power and timing methodologies. Mr. Guardiani has a degree in physics with Laude from the University of Parma in Italy, holds several US and international patents and is the author of over 40 IEEE Conference and Journal papers.
Conventional thinking about DFM positions the activities that go under the name of Design For Manufacturability in the realm of layout polygons manipulation, OPC/RET optimization/verification and mask correction methods. Although all these activities are certainly key to successful chip manufacturing, it is clear that they only involve the physical level (and below) of the design flow, i.e. the one closest to the “M” side of DFM.
In this speech we will show that, analogously to power and timing, also functional and speed yield can be addressed at all design levels, and that actually most of the DFM/DFY opportunities exist at higher levels of abstraction and associated design flow tasks such as RTL design, synthesis, design floor-plan optimization and place&route.
MONDAY FEBRUARY 27SCV Circuits and Systems
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 28
The Technology Behind the New IEEE-CNSV Website
Speaker: Debra Willrett, Expert Software Consulting Time: Networking at 7:00 PM;
Presentation at 7:30 PM Cost: none Place: Keypoint Credit Union, 2805 Bowers Avenue
(between Kifer and Central), Santa Clara RSVP: not required Web: www.CaliforniaConsultants.org/notices.htm
Debra Willrett is the founder of Expert Software Consulting. She specializes in web design for member organizations such as trade associations, user groups, alumni groups and clubs. Her websites offer member services, publish online member directories, and manage membership data, group calendars, online event registration and payment processing. Debra can be reached at [email protected] 650.472.2246.
The design, technology and development tools
used to create the new IEEE-CNSV website at www.CaliforniaConsultants.org will be presented. Debra will address user interface design decisions such as navigation and page layout, the technologies used including XHTML/DHTML, DOM, CSS, JavaScript and AJAX, and the design tools used including Macromedia Studio MX, Dreamweaver, Fireworks, and the ColdFusion back-end technology which manages the database.
TUESDAY FEBRUARY 28SCV Consultants' Network of Silicon Valley
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 29
High-Definition Multi-Room DVRs and Hard Disk Drives
Speakers: Jorge Campello and Donald Molaro,
Hitachi GST Time: Networking at 7:00 PM;
Presentation at 7:30 PM Cost: IEEE Member $5, non-IEEE member $10 Place: Oak Room at HP Cupertino, on Wolfe and
Pruneridge, 19447 Pruneridge Avenue (Building 48), Cupertino
RSVP: Please reserve by email to [email protected]
Web: www.ieee.org/scvce/meetings/ 060228/2006February28.html
Jorge Campello received Electrical Engineer and
M.Sc. in Electrical Engineering degrees from Universidade Federal de Pernambuco, Recife, Brazil in 1992 and 1994 respectively. He received a PhD in Electrical Engineering from Stanford University in 1999. In 1999 he joined IBM's Almaden Research Center as a Research Staff Member, working on Coding and Information Theory applied to Magnetic Recording Systems. In 2003 he joined Hitachi GST's San Jose Research Center where he is currently a Research Staff Member working in the area of HDD applications to Consumer Electronics.
Donald Molaro is a Sr. Software Engineer with Hitachi GST research and holds a MSc. from the University of Calgary and has over fifteen years of software development experience. He has worked on a number of consumer and professional electronic products including set top and media server systems. Since joining Hitachi GST in August 2004 he has worked on addressing several issues related to the use of HDDs in high-performance multimedia systems.
The ability to store and retrieve large amounts of data quickly is becoming a key feature of new consumer electronic designs. Virtually every device category from music players to multi-room digital video recorders relies on storage in some form. In this talk we give a brief overview of how HDDs work focusing on the aspects that impact performance and quality of service for streaming applications. We will also describe the main challenges of integrating HDDs into high-performance consumer electronics devices such as High-Definition Multi-Room DVRs. We will also discuss software and systems design requirements to maximize streaming performance from a disk with a particular emphasis on the ATA-7 streaming command set.
TUESDAY FEBRUARY 28SCV Consumer Electronics
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 30
Best of RAMS: From The Reliability and Maintainability
Symposium in January
Speakers: Attendees present highlights of the best
papers Time: Refreshments at 6:30 PM;
Presentations at 7:00 PM Cost: none Place: Oak Room at HP Cupertino, on Wolfe and
Pruneridge, 19447 Pruneridge Avenue (Building 48), Cupertino
RSVP: not required Web: www.ewh.ieee.org/r6/scv/rs
The 52nd Annual Reliability and Maintainability
Symposium (RAMS) was held in Newport Beach on January 23-26, 2006. For those of you that couldn't attend, we will bring the symposium to you. This evening offers highlights of the best papers presented at RAMS during this 4 day event. The theme of this year's RAMS was "The Role of Reliability and Maintainability in Managing Risk". Information on RAMS is available on the web at http://www.rams.org/. The panel is being organized by Mike Silverman and Fred Schenkelberg. If you are interested in helping select papers, being on the panel, leading a discussion, or contributing in another way, please e-mail us at [email protected].
WEDNESDAY MARCH 1SCV Reliablility
Professional Consulting Services to assist clients in developing & executing any and all elements of Reliability throughout an Organization & Product Life Cycle.
• Assessments • Goals • Benchmarking • Reliability Prog. Plans • MTBF Pred • FMECA • EOL Assessment • Warranty Analysis • HALT/HASS • DVT/V&V • Rel. Demo. Tests • Software Reliability • CAPA/CLCA • DoE • Training/teaching • RoHS/WEEE Transition
pioneered Reliability IntegrationSM - using multiple tools in conjunction to increase the power and value of any Reliability Program.
(408) 472-3889 [email protected] www.opsalacarte.com
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 31
Restriction of Hazardous Substances (RoHS) Directive Implementation Challenges
and RoHS: Long-Term Perspective
and Legal and Trade Challenges Speakers: Thomas Ellison, Finisar and
John Burke, Optichron Time: Seated dinner at 6:30 PM; presentations
at 7:30 PM Cost: $25 if reserved by March 5; $30 at the
door; presentation-only is free Place: Ramada Inn, 1217 Wildwood Ave (Fwy
101 frontage road, between Lawrence Expy and Great America Pkwy), Sunnyvale
RSVP: Please reserve and pay in advance using our PayPal on-line system or email Janis Karklins at [email protected]
Web: www.cpmt.org/scv
Thomas Ellison has worked in electronics manufacturing for the last 17 years. His experience includes research and development work in vapor phase soldering and nitrogen inerting of reflow ovens while at Air Products and Chemicals, ASIC design management and process engineering management of a high volume surface mount assembly facility for Trimble Navigation, and SMT and fiber optic transceiver engineering for Finisar Corporation. More recently Tom has been the lead technical engineer for Finisar's RoHS compliance efforts. He provided technical leadership for Finisar's conversion to lead-free soldering processes and is currently working on component issues, materials declarations and data management aspects of RoHS compliance. He has a B.S. in Chemistry from University of Missouri - Rolla and an M.S. in Materials Science and Engineering from Iowa State University.
John Burke founded the UK based Surface Mounted and Related Technologies (SMART) Group in 1984, and has worked in the area of advanced manufacturing for many years. He has taught at various universities on technology, including university of Dundee, University of Hull, University of Limerick and University of Cambridge. (continued, next page)
RoHS Directive Implementation Challenges Implementation of the Restriction of Hazardous
Substances (RoHS) Directive presents special challenges for small and medium sized companies. Limited staff and dependence on outsourced services creates cost burdens for smaller OEMs.
The first major challenge is conversion of existing product Bills of Materials. Conversion is usually much more involved than just re-specifying RoHS compliant parts on the AVL. For some components, it may be difficult to eliminate the offending RoHS element (Cd, Pb, etc.) and still have the product function successfully. Major corporations have been active in proposing and receiving special exemptions from the TAC committee but further additions seem less likely without substantial data.
A second major challenge is the "due diligence" process of collecting, compiling and evaluating supplier certificates of compliance and materials declarations for the multiple suppliers of hundreds of components. New database systems must be added, populated and sustained. Since most "due diligence" protocols advocate random component testing, arrangements must be made to screen and chemically test sample lots from most suppliers. Testing at the assembly level for extremely low levels of the six RoHS elements at the homogenous constituent layer level is problematic for many tiny electronic components. In some cases, it may take 5-10 components to make up the minimum quantity required for chemical testing. Yet Pb is exempt in some layers while forbidden in other layers of the same component.
A third major challenge is assessing the reliability impact of conversion to RoHS. Thankfully, national and international consortia have addressed many of the major technical issues but each company must still address the impact of tin whisker mitigation strategies, SAC alloy fatigue behavior and higher reflow temperatures on their specific products. In most cases, converted products must be completely re-qualified to assess the impact of these changes on reliability.
RoHS: Long-Term Perspective The much-heralded WEEE deadlines arrived - and
passed -- with no fanfares, just another date on the calendar, and the July 1 2006 RoHS deadline will be just the same. The difference though, as we all know, is that these dates transitioned any manufacturer (continued, next page)
WEDNESDAY MARCH 8SCV Components, Packaging & Manufacturing Technology
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 32
John worked on the generation of IPC 1752 as a part
of the 2-18 committees, and dealt with reporting standards for hazardous materials. For many years he has been involved in the drive towards environmentally sound electronics assemblies, and has been heavily involved in trying to aid engineers caught up in the drive towards RoHS and JIG compliance.
John is currently employed by Optichron Inc., a fabless semiconductor vendor based out of Fremont, as the Senior Operations Manager.
Thomas Ellison
shipping products into Europe from the crystal clear waters of margin-based commerce into the murkier waters of environmental compliance.
This talk looks back on the RoHS legislation, looks at what is good about it (the environmental protection) and what is bad about it (the way it has been implemented). It considers how such legislation can be handled by the industry going forwards, particularly in view of the next impending round of legislation which will be directly impacting the product design in terms of its ease of recycling.
The talk also considers how manufacturers need to address the "worth" of compliance data from their vendors, the route by which it arrived, and the guarantees which came with it. This part of the talk will take the form of a series of "what if" scenarios should a company be challenged on its product compliance, and hopefully will throw some light onto the correct way to approach data collection and audit procedures.
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 33
Professional Selling in a Competitive Market:
Systematic B2B Sales Techniques to Substantially Increase
Your Revenue Speaker: Gerd Neumann, Ph.D., GN Consulting, LLC Time: Networking at 7:00 PM;
Presentation at 7:30 PM Cost: none Place: Keypoint Credit Union, 2805 Bowers
Avenue (between Kifer and Central), Santa Clara
RSVP: not required Web: www.CaliforniaConsultants.org/notices.htm
Dr. Gerd Neumann is President and CEO of GN Consulting, LLC, a firm that provides expertise in business consulting. Gerd has achieved measurable and lasting increases in revenue and profit with companies in a variety of business sectors by applying systematic and successful sales techniques for sales teams and management tools for sales managers. He helps managers achieve their sales goals.
Gerd has extensive experience in general management. During his work as CEO of Nokia Cable, he handled multiple business cultures and successfully developed and implemented visions for future businesses. His strong results-orientation is demonstrated by substantial revenue and profit increases during his tenure.
He has more than 20 years of experience in sales, and has been Vice President of Sales in the telecommunication and data network equipment industry. He has managed a profit center with more than 80 sales persons, and he has personally started new business sectors using his marketing and sales skills.
His educational background includes a Ph.D. in Physics from the University of Cologne, Germany, and he has extensive experience with and understanding of European cultures and businesses.
The goal of all businesses is to generate profit, which requires getting customers/clients. That’s why the process of winning customers is one of the most important processes in every company. It consists of:
a) The Marketing Cycle: How to get leads and how to turn leads into prospects?
b) The Sales Cycle: How to turn prospects into customers / clients?
After an introduction into the marketing and sales cycles, Gerd will present proven techniques which can be used to win sales projects in a competitive market without sacrificing price. He will address “Business Analysis (of your prospect’s business)” and the “Extended Value Concept” to better financially justify your business' offerings, and to differentiate them from those of your competition. Gerd will also discuss “Relationship Management,” how to make relationships measurable, and how to actively fight competition. Finally, he will address the issue of every business owner: how to make the sales process measurable so you can better judge the status of your sales projects at any time within a sales cycle.
TUESDAY MARCH 21SCV Consultants' Network of Silicon Valley
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 34
Panel: Update on Nuclear Energy in the United States
Speakers: Dr Jane Long, the Associate Director of
Energy and Environment for the Lawrence Livermore National Laboratories; Dr. Jasmina Vujic - Professor of Nuclear Engineering, UC-Berkeley; and others
Sponsorship: jointly sponsored with the Association of Energy Engineers
Time: 6:00 PM - 9:00 PM Cost: not yet determined Place: to be determined Further Information: Carole Pharr, 408-282-1500
x213 Web: www.ewh.ieee.org/r6/oeb/pes.html
Further information will be available later in February for this interesting panel discussion. Please return to the website or watch for the March issue of the GRID.
TUESDAY MARCH 28OEB Power Engineering
J A N U A R Y 2 0 0 6 V i s i t u s a t w w w . e - G R I D . n e t P a g e 35
CONFERENCE CALENDAR
The CONFERENCE CALENDAR is a service to our IEEE Members. It outlines upcoming IEEE workshops and conferences in the Bay Area. Please submit items to the GRID Editor: [email protected].
Conferences are also encouraged to purchase display space in the GRID.pdf and publicize their events on our website and in our e-GRID email notification service. For the Conference Publicity flyer, please download:
www.e-gr id.net /docs/conf- f lyer .pdf
DesignCon 2006
• February 6-9, 2006 • Santa Clara Convention Center • Exhibition: Feb. 7-8
DesignCon is Silicon Valley's premier conference and technology exhibition for the semiconductor and electronic design engineering communities. As the first major event of its kind each year, DesignCon addresses the industry's most critical business and technical issues.
See Page 7 for more details
Internationalization and Unicode Conference
• March 6-8, 2006 • Hyatt Regency Hotel, Burlingame (SF Airport) • Tutorials: Monday, March 6 • Sessions: Tuesday-Wednesday, March 7-8
Unicode experts, implementers, clients and vendors are invited to attend this unique conference on the Unicode Standard and internationalization. Exchange ideas with leading experts, find out about the needs of potential clients, or get information about new and existing Unicode-enabled products.
See Page 5 for more details
PCB West 2006 • March 26-31, 2006 • Santa Clara Convention Center • 12 Professional Development Tutorials • 34 Short Courses, over 250 speakers
This is the premier West Coast conference for PCB engineering, design and manufacturing professionals, with more than 50 technical courses and 12 Professional Development Certificate Program classes. Create your own personlized educational experience to become a better and more confident designer aware of new technological opportunities.
See Page 8 for more details
Game Developers Conference GDC:06
-- Conference March 20-24, 2006 -- San Jose Convention Center -- Exhibits March 22-24
Next-gen game development will revolutionize every aspect of the gaming industry, and in turn influence other technology sectors that use advanced display, simulation, and interactive technologies. Concurrent with:
GDC Mobile 2006 - March 20-21, 2006 - Fairmont Hotel, San Jose
Serious Games Summit GDC - March 20-21, 2006 - Fairmont Hotel, San Jose
See Page 5
For more details
Int’l Symposium on Quality Electronic Design
• March 27-29, 2006 • DoubleTree Hotel, San Jose • Tutorials: Monday, March 27 • Sessions: Tuesday-Wednesday, March 28-29
ISQED bridges the gap among electronic design tools and processes, integrated circuit technologies, processes, and manufacturing -- for VLSI circuits & systems designers (IP & SoC), process/device technologists and semiconductor manufacturing specialists.
See Page 9
Embedded Systems Conference • April 3-7, 2006 • San Jose Convention Center • Free admission to Exhibition Six full Design Seminars: - Analog Design - Linux Design - DSP Performance - Power Management - Consumer Video - Wireless Networking Over 100 three-hour and 90-minute Technical Classes, plus Tutorials and Microprocessor Summit
See Page 11 Co-located with:
D2M and IEEE Real-Time & Embedded Technology & Applications Symposium
See Page 12