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IEEE PROJECT TITLES 2015-16 - VLSI DIGITAL SIGNAL PROCESSING Designs of All pass Variable Fractional Delay Filter with Powers- Of-Two Coefficients. Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing. Fault Tolerant Parallel Filters Based on Error Correction Codes. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications. Exact and Approximate Algorithms for the Filter Design Optimization Problem. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System. Obfuscating DSP Circuits via High-Level Transformations. A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. Two-Step Optimization Approach for the Design of Multiplier less Linear-Phase FIR Filters. An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multi standard DUC.IMAGE & VIDEO PROCESSING Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications. A Discrete Tchebichef Transform Approximation for Image and Video Coding. A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications. Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform. Low-Power VLSI Architectures for DCT/DWT: Precision vs Approximation for HD Video, Biomedical, and Smart Antenna Applications. Low-Power Architecture for the Design of a One-Dimensional Median Filter. High-Throughput FPGA Implementation of QR Decomposition. A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications. Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications. Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design. Unified VLSI architecture for photo core transform used in JPEG XR.ARITHMETIC UNITS A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic. Comment on High Speed Parallel Decimal Multiplication with Redundant Internal Encodings. Variable Latency Speculative Han-Carlson Adder. Reliable Radix-4 Complex Division for Fault-Sensitive Applications. Recursive Approach to the Design of a Parallel Self-Timed Adder. Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq. Design and Analysis of Approximate Compressors for Multiplication. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. High-speed demonstration of bit-serial floating-point adders and multipliers using single-flux-quantum circuits. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding. Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design. A Modified Partial Product Generator for Redundant Binary Multipliers. Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic. Partially Parallel Encoder Architecture for Long Polar Codes.VLSI ARCHITECTURE & APPLICATION Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. Memory-Based Hardware Architectures to Detect ClamAV Virus Signatures with Restricted Regular Expression Features. Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. Economizing TSV Resources in 3-D Network-on-Chip Design. Phase Change Memory Write Cost Minimization by Data Encoding. A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. Protein Alignment Systolic Array Throughput Optimization. Z-TCAM: An SRAM-based Architecture for TCAM. A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing. Finite State Machines with Input Multiplexing: A Performance Study. Heuristic algorithm for periodic clock optimization in scheduling-based latency-insensitive design. Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems. All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion. An Encryption Scheme Using Chaotic Map and Genetic Operations for Wireless Sensor Networks. High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems. High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors. A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing.

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications. A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders. An Energy Efficient Design for ECG Recording and R-peak Detection Based on Wavelet Transform. Fault Tolerant Parallel FFTs Using Error Correction Codes and parseval Checks. FPGA Trojans through Detecting and Weakening of Cryptographic Primitives. An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems.VLSI TESTING FPGA-based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. Key Updating for Leakage Resiliency with Application to AES Modes of Operation. Test Compression for Circuits with Multiple Scan Chains. Low-Power Programmable PRPG with Test Compression Capabilities.TRANSISTOR LEVEL DESIGN Low-power, high-speed dual modulus pre scalers based on branch-merged true single-phase clocked scheme. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. Logic-in-Memory with a Nonvolatile Programmable Metallization Cell. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology.MATLAB TITLES

WIRELESS COMMUNICATION Time-Frequency Joint Sparse Channel Estimation for MIMO-OFDM Systems. A Novel Low-Complexity Pre-coded OFDM System With Reduced PAPR. OFDM Synthetic Aperture Radar Imaging With Sufficient Cyclic Prefix. Novel Frequency-Domain Oversampling Receiver for CP MC-CDMA Systems. Analysis and Design of Channel Estimation in Multi-cell Multi-user MIMO OFDM Systems. A New Equalizer in Doubly-Selective Channels for TDS-OFDM. Asymmetrically Clipped Optical Fast OFDM Based on Discrete Cosine Transform for IM/DD Systems. ICI-free equalization in OFDM systems with blanking preprocessing at the receiver for impulsive noise mitigation. BER Minimization for AF Relay-Assisted OFDM Systems. Cooperative diversity scheme using SPC in MIMO-OFDMA system. Distributed Pre coding for OFDM in Two-Way Relaying Communications. Variable Step-size MLMS Algorithm for Digital Pre distortion in Wideband OFDM Systems. Transceiver Optimization for Unicast/Multicast MIMO Cognitive Overlay/Underlay Networks. Clipping Noise Cancelation for OFDM Systems Using Reliable Observations Based on Compressed Sensing. Robust MIMO-OFDM System for Frequency-Selective Mobile Wireless Channels. Pilot-Aided Joint Estimation of Doubly Selective Channel and Carrier Frequency Offsets in OFDMA Uplink with High Mobility Users. A Bandwidth-Efficient Cognitive Radio with Two-Path Amplify-and-Forward Relaying Wireless networks. Particle Swarm Optimization based Clustering by Preventing Residual Nodes in Wireless Sensor Networks. Energy Efficient Wireless Sensor Networks Using Linear-Programming Optimization of the Communication Schedule. Non cooperative Game-Based Energy Welfare Topology Control for wireless Sensor Networks. Maximum lifetime scheduling for target coverage and data collection in wireless sensor networks. Opportunistic Routing Algorithm for Relay Node Selection in Wireless Sensor Networks. Performance Analysis of Space-Shift Keying in Decode-and-Forward Multi-hop MIMO Networks.

Minimum Mean-Square Error Estimation of Mel-Frequency cepstral FeaturesA Theoretically Consistent Approach. Fetal heart beat detection by Hilbert transform and non-linear state-space projections.IMAGE PROCESSING

Local Binary Patterns and Extreme Learning Machine for Hyper spectral Imagery Classification. Reversible Image Data Hiding with Contrast Enhancement. A New Data Transfer Method via Signal-rich-art Code Images Captured by Mobile Devices. The Mesh-LBP: A Framework for Extracting Local Binary Patterns from Discrete Manifolds. Acute Lymphoid Leukemia Classification using Two-Step Neural Network Classifier. Local Binary Pattern Based Fast Digital Image Stabilization. PSO Algorithm Applied to Codebook Design for Channel-Optimized Vector Quantization. Segmentation and Classification Using Logistic Regression in Remote Sensing Imagery. Content-Based Image Retrieval Using Features Extracted from Half toning-Based Block Truncation Coding. Sparse Hierarchical Clustering for VHR Image Change Detection. Towards Effective Image Classification Using Class-Specific Codebooks and Distinctive Local Features. Discrimination of Vegetation Height Categories with Passive Satellite Sensor Imagery Using Texture Analysis. Local Binary Patterns and Extreme Learning Machine for Hyper spectral Imagery Classification. A Novel Negative Abundance-Oriented Hyper spectral Un-mixing Algorithm. Binary Tomography Reconstructions with Stochastic Level-Set Methods. Haze Removal for a Single Remote Sensing Image Based on Deformed Haze Imaging Model. Night-time pedestrian classification with histograms of oriented gradients-local binary patterns vectors. Real-Time Impulse Noise Suppression from Images Using an Efficient Weighted-Average Filtering. Reversible Image Data Hiding with Contrast Enhancement A Regularization Approach to Blind De blurring and De noising of QR Barcodes. Energy-efficient low bit rate image compression in wavelet domain for wireless image sensor networks.