ieee journal of solid-state circuits, vol. 39, no ... modular 32-site...ieee journal of solid-state...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004 2457

A Modular 32-Site Wireless NeuralStimulation Microsystem

Maysam Ghovanloo, Member, IEEE, and Khalil Najafi, Fellow, IEEE

Abstract—This paper presents Interestim-2B, a modular 32-sitewireless microstimulating ASIC for neural prosthesis applica-tions, to alleviate disorders such as blindness, deafness, and severeepilepsy. Implanted just below the skull along with a high-densityintracortical microelectrode array, the chip enables leadless op-eration of the resulting microsystem, accepting power and datathrough an inductive link from the outside world and insertinginformation into the nervous system in the form of stimulatingcurrents. Each module contains eight current drivers, generatingstimulus currents up to 270 A with 5-b resolution, 100 Moutput impedance, and a dynamic range (headroom voltage) thatextends within 150 mV of the 5 V supply rail, and 250 mV of theground level. As many as 64 modules can be used in parallel, todrive multiprobe arrays of up to 2048 sites, with only a pair ofconnections to a common inductive–capacitive (LC) tank circuit,while receiving power (8.25 mW/module) and data (2.5 Mb/s)from a 5/10-MHz frequency shift keyed carrier. Every 4.6 mm

4.6 mm chip fabricated in a 1.5- m, 2M/2P standard CMOSprocess through MOSIS, houses two modules and generates up to65 800 stimulus pulses/s.

Index Terms—Charge balancing, current source, frequency shiftkeying, implantable electronics, inductive coupling, microstimu-lator, modular architecture, neural prosthesis, voltage compliance,wireless.

I. INTRODUCTION

AUDITORY function restoration in profoundly deaf in-dividuals has been successfully achieved by implanting

wireless microstimulators capable of electrically stimulating thecochlea or auditory brainstem [1]. In spite of extensive research,however, visual prostheses and artificial vision, which have alonger history than some of the commercialized implantabledevices such as deep-brain and spinal cord stimulators, havenot yet been widely utilized in the blind [2]–[9]. The reasonis the greater complexity of the visual system, which imposessevere technological challenges on an implant in terms of thefollowing areas.

• Number of stimulating sites: The most advanced cochlearimplants have 22–30 stimulating sites. Yet, a patient canconverse on the phone with as low as six sites. For a

Manuscript received April 23, 2004; revised July 2, 2004. This work was sup-ported in part by the National Institutes of Health under Contract NIH-NINDS-N01-NS-9-2304, and the work was performed at the WIMS Engineering Re-search Center shared facilities supported by the National Science Foundationunder Award EEC-0096866.

M. Ghovanloo is with the Bionics Laboratory, Department of Electricaland Computer Engineering, North Carolina State University, Raleigh, NC27695–7914 USA (e-mail: [email protected]).

K. Najafi is with the Center for Wireless Integrated Microsystems, Universityof Michigan, Ann Arbor, MI 48109-2122 USA.

Digital Object Identifier 10.1109/JSSC.2004.837026

visual implant on the other hand, psycho-physiologicalexperiments with a pixelized vision have shown that aminimum of 625 pixels are needed to restore a functionalvisual sensation [4], [5]. It is also envisaged that aminimum of 1000 sites would be needed for being ableto read text with large fonts [6].

• Stimulation strategy: The auditory nerve consists of about30 000 nerves, which should be tonotopically stimulatedto attain the right hearing perception. After 30 years of re-search, finding the best speech processing and stimulationstrategy is still a hot topic in biomedical signal processing[1]. The optic nerve is made up of 1.2 million nerves andthe relationship between the optical image and the activityin these nerves is yet to be understood [5]. Therefore,development of an efficient image processing and visualstimulation strategy might not happen in the near term. Asa result, today’s visual implants should provide the max-imum level of flexibility to be able to support most of thestimulation strategies that will emerge in the future.

• Power consumption: Leadless operation of the im-plantable devices is a necessity to reduce the risk ofinfection and patient discomfort as well as increase theimplant robustness. Those implants with less powerrequirement ( 100 W), such as pacemakers, have aninternal long lifetime battery that can last more thanten years. The implants with high power requirements( 1 mW) or extreme size constraints such as auditory orvisual prostheses need to be inductively powered by twomagnetically coupled coils that constitute a transformerand one of them is embedded in the implantable device[5], [9].

• Bandwidth: The human eye natural bandwidth is about60 Hz [2]. Addressing and controlling more than1000 stimulating sites based on the adopted stimula-tion strategy at this frequency needs several megahertzof bandwidth across the inductive link. Wireless net-works have achieved tens of megahertz of bandwidth byincreasing the carrier frequency well into the gigahertzrange. In biomedical implant applications, however, thechallenge is to achieve a wide bandwidth with a carrierfrequency that is limited to 20 MHz due to the hightissue electromagnetic absorption at higher frequencies[10] as well as the coupled coils self-resonance.

• Implant Size: So far, visual implants have been testedbelow/above the retina, around the optic nerve, and onthe visual cortex with planar, cuff, and, penetrating elec-trodes, respectively. Each of these methods has its ownunique set of surgical and physiological advantages and

0018-9200/04$20.00 © 2004 IEEE

2458 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004

limitations [2], [5]. Nonetheless, what is in common forall of them is the extreme limitation in size for minimalinvasiveness. Full integration and minimization of thenumber of hybrid components seem to be the only waysto achieve a visual implant with reasonable size.

Several researchers have addressed the above problems withlimited success [2]–[9], [11]–[16]. This paper presents Inter-estim-2B (IS-2B), a 32-site wireless microstimulator ASICwith a modular architecture [17]. Every IS-2B module is aself-contained, fully integrated unit (two modules per chip)that operates with only a pair of connections to a hybrid LCtank. The IS-2B individually addressable modules would allowassembling a 64-module 32-site wireless microstimulatingsystem while sharing the same hybrid LC tank. Therefore, acluster of 32 IS-2B chips in a single implant or a networkof stand-alone implants under a single external coil would becapable of addressing up to 2048 stimulating sites, which ad-vances the state-of-the-art in nearly all of the aforementioneddirections. Because of the similarities between different sen-sory or motor regions of the cerebral cortex, it is likely that ahigh-density electrode array architecture, designed for IS-2B,be well suited for several applications [2]. Hence, the ulti-mate goal is to develop multipurpose button-sized wirelessmicrostimulating three-dimensional (3-D) electrode arrays bymounting IS-2B chips on micromachined platforms that areconnected to passive microelectrodes, or implementing theIS-2B circuitry on the backend of active silicon microma-chined probes, as shown in Fig. 1 [17], [18].

Section II describes the system overview and modular ar-chitecture of the IS-2B. Section III presents the major circuitblocks in more detail along with simulation results. Experimen-tally measured results are reported in Section IV, followed bythe concluding remarks in Section V.

II. SYSTEM OVERVIEW

A. External Components

The block diagram of the IS-2B wireless neural stimulationmicrosystem is shown in Fig. 2 [17]. The external componentsof the system are enclosed in a dashed box on the left side ofFig. 2(a). The rest of the system, which is fully integrated ex-cept for the receiver tank circuit, is small enough to beimplanted in the body. Digitized image or sound information,acquired by a miniature camera or microphone for a visual or au-ditory prosthesis, respectively, is sent to a portable computer orPDA as shown in Fig. 1. The computer processes the incominginformation in real-time and generates a series of stimulationcommand-frames that can cause a set of spatiotemporal stimuluspulses based on the adopted stimulation strategy at a two-dimen-sional (2-D) or 3-D array of stimulating sites that is implanted inthe targeted neural tissue. The command-frames are arranged inbursts of nonreturn-to-zero (NRZ) serial data bit stream, whichare then modulated into a square-shaped frequency shift keyed(FSK) signal at 5 and 10 MHz by a high-speed digital I/O card(National Instruments DIO-6534) as shown in Fig. 3. To achievea high data rate close to the carrier frequency, a particular phase-

Fig. 1. Multipurpose button-sized wireless microstimulating 3-D array [18].

coherent FSK protocol is utilized in which logic “1” is trans-mitted by a single cycle of the carrier at frequency and logic“0” is transmitted by two cycles of the carrier at . The car-rier frequency switches at a small fraction of a cycle and onlyat negative-going (or positive-going) zero crossings. Choosing

, results in a constant data rate that can be as high as[19]. In practice, limitation in the inductive link bandwidth,

in spite of using a wideband series-parallel LC tank combina-tion for the transmitter coil [20], does not allow utilization ofthe modulation full-speed with an acceptably low bit-error rate(BER). In order to improve the BER, the FSK carrier spectralbandwidth was decreased by repeating every bit twice. There-fore, choosing MHz and MHz resulted in a datarate of 2.5 Mb/s, which should be enough for a visual prosthesiswith minimum functional resolution [13].

The square-wave digital FSK signal, which has a 2.5-V dccomponent, passes through dc-level adjustment circuit and aband-pass filter (10 kHz–5.6 MHz) to turn into a bipolar sinu-soidal FSK carrier (Fig. 3) before being amplified by a widebandpower amplifier (Amplifier Research, PA). Finally, the ampli-fied FSK carrier, which contains both data and power for theIS-2B implant, is transmitted through a wideband, low-Q in-ductive link that is set up by generating two zeros at andacross the transmitter 50 output with a series-paralleltank combination, to reshape the inductive link passband, as

GHOVANLOO AND NAJAFI: A MODULAR 32-SITE WIRELESS NEURAL STIMULATION MICROSYSTEM 2459

Fig. 2. (a) Block diagram of the IS-2B microsystem. (b) Current drivers schematic diagram [17].

Fig. 3. High data rate phase-coherent FSK modulation protocol [19], [20].

described in [20]. A wideband inductive link is necessary forachieving high data rates in order to eliminate residual ringing(intersymbol interference) on the receiver side when the carrierfrequency switches from to and vice versa.

B. IS-2B Architecture

The implantable part of the IS-2B wireless stimulating mi-crosystem consists of a receiver tank circuit, IS-2B mod-ules (2–64), and passive probes, which interface with the neuraltissue [21]. An IS-2B module is a system-on-a-chip (SoC) con-sisting of all the gray boxes in Fig. 2(a) and blocks in Fig. 2(b).There are two identical modules in each IS-2B chip, supportinga total of 64 stimulating sites. The receiver tank circuitprovides each module with inductively coupled power and data.

Power Supply: Implant size reduction is achieved in thepower supply block by utilizing a fully integrated full-waveCMOS rectifier [22], [23], followed by an on-chip ripplerejection capacitor . The previous implants used either


Fig. 4. Format of the IS-2B 18-b command frame.

hybrid rectifiers or an inefficient half-wave substrate diode [11],[12], [14]. A series-type regulator stabilizes at 5 V forunregulated inputs 6.7 V. In order to ensure safe operation,especially at start-up, a power-on-reset (POR) circuit activatesa global reset line at start-up, continuously monitors , andreleases the reset line 70 s after the regulator voltage exceeds4.8 V to ensure that the digital circuits start from a knownstate (reset) after transients are passed. It also shuts the entiremicrostimulator down when 3.4 V.

Receiver Block: Receiver is the second block that is con-nected directly across the tank circuit. Using a new FSKdemodulator, which is designed specifically for a phase-co-herent FSK modulated signal (Fig. 3), data bits are detectedby measuring the duration of each received carrier cycle. Thedemodulator also derives a constant frequency clock from thephase-coherent FSK carrier to sample the recovered data bitsand run the IS-2B digital circuitry [19], [20].

Digital Controller: Isochronous communication scheme isadopted to provide a fast, steady, and uninterrupted data stream,which is preferred for video applications [24]. Fig. 4 showsthe format of IS-2B 18-b command-frames, which contain adata byte and an address byte, each accompanied by a paritybit. In a burst of serial data bit stream, these command-framesare transmitted back to back, while being separated by 1-bspacers. In the digital controller block, an 18-b shift registerand a sequencer convert the serial data bit stream to parallel,while a pattern detector resets the sequencer upon receiving aunique frame (0FF0FFh) to maintain synchronization with thetransmitter. The address byte consists of a 6-b module address( – ) and a 2-b register-address ( , ). The moduleaddress is compared to the module’s hard-wired user-pro-grammable address, and if they match, and there is no parityerror, the data byte ( – ) is stored in one of the four internalregisters that is defined by the register-address. Otherwise, thereceived command-frame is ignored with no further action. Themodule’s hard-wired 6-b address, which is originally set to 3Fh,can be changed by laser-cutting the hardwired links in order toassign a unique address to each one of up to 64 modules thatcan operate in parallel in a multichip system.

Current Drivers (CD): Each module has eight currentdrivers ( – ) that are enclosed in dashed boxes inFig. 2(b). Each has both nMOS current sink andpMOS current source versions of a closed-loop circuittopology that utilizes the above transistors in deep triode regionas linearized voltage-controlled resistors (VCR) by applyinga larger than threshold , while actively maintaining their

at 80 mV [25], [26]. Each , which is multiplexedamong four stimulating sites, is controlled by two specificstatus bits ( , ) and two shared mode bits ( , ).Combinations of these bits can connect each stimulating siteto , current source, GND, current sink, common analog

line (CAL), or keep it at high- , in four different operatingmodes, as summarized in Table I. The result is a wide variety offunctions and stimulation strategies that can be used dependingon the application. An additional reference line [not shown inFig. 2(b)], which stays at high- in bipolar stimulation (be-tween two sites), can be connected to , GND, or CAL underfeedback bits ( , ) control in Mode-0 for monopolarstimulation (between one site and the reference electrode) [21],[27].

Register Bank: Two current amplitude registers [ andin Fig. 2(a)] store two sets of 5-b stimulus amplitude

and 1-b offset information for a dual pair of voltage-modedigital to analog converters: DAC-p ( , ) and DAC-n( , ). These DACs control the pMOS VCR currentsources and nMOS VCR current sinks in the CD blocks [25].The last two bits of and , called mode bits ( ,

) and feedback bits ( , ), respectively, indicatethe microstimulator mode of operation and the type of backtelemetry feedback. Two site status registers ( and )store the individual status bits ( , ) for each (seeTable I).

Timing: The timing of the stimulus pulses in IS-2B is con-trolled by the sequence of successive command-frames. In otherwords, every change in the mode of operation, sites configura-tion, and stimulus amplitude is instructed to the implant by theexternal system in real time. This method, which is described inmore detail in a measured example in Section IV, provides thehighest level of flexibilitily in generating any arbitrary stimuluswaveform from any of the sites [13]. In addition, since the ex-ternal controller takes care of the time keeping functions, there isno need for on-chip timers and their associated logic. This hassignificantly simplified the IS-2B digital circuitry, and conse-quently reduced its circuit area in a 1.5- m fabrication process.These advantages, however, come at the expense of a larger re-quired bandwidth, which is not a limiting factor with utilizationof the high-speed digital FSK demodulator that is described inSection III-B [19], [20].

Back Telemetry: The power transmission efficiency of theinductive link highly depends on the relative distance betweenthe transmitter and receiver coils [29]. Because ofthe variations in the relative coils distance with patient’s move-ments, an open-loop, constant power transmission scheme canresult in significant fluctuations in the implant received power,which might exceed the on-chip regulator dynamic range. To ex-ternally regulate the implant received power (coarse regulation),in addition to the on-chip regulator (fine regulation), a closedloop system, which monitors as a feedback, is foreseento stabilize the implant received power by adjusting the externalpower amplifier gain. Another purpose of the back-telemetryblock is to wirelessly monitor the stimulating sites potentialthrough CAL. The stimulating site voltage can be an indicator ofthe site and tissue impedance, while passing a 1-kHz sinusoidalcurrent, as well as charge balancing situation at the end of eachstimulus [27]. These measurements are necessary especially inlong-term chronic stimulations to check for the defective sitesand stimulation safety. The back-telemetry block selects one outof four possible feedbacks, , CAL, , and , basedon the feedback bits, as shown in Fig. 2(a). This block then pulse


TABLE ICURRENT DRIVER TRUTH TABLE

width modulates (PWM) the selected analog input signal, andshifts the impedance across , which is reflected back to ,due to their mutual coupling (passive back telemetry by loadshift keying) [28].

III. CIRCUIT IMPLEMENTATION

A. Integrated Full-Wave CMOS Rectifier

Diode-connected MOS transistors are used to form a fullyintegrated full-wave CMOS rectifier as shown in Fig. 5(a) [21],[23]. and conduct in the forward direction when thecoil voltage at or is higher than , while deliv-ering current from the coil to the load. passes throughthe load, which is the rest of the chip, to the grounded P-sub-strate and returns back to the coil via , , , and .The rectifier drop-out voltage, , should be min-imized to decrease power dissipation in the rectifier block, in-crease the average rectified dc voltage available at the regulatorinput, and lower the minimum operational receiver coil voltage.When passes through a diode-connected MOS

(1)

where is the MOS threshold voltage, is the intrinsictransconductance, and and are the transistor width andlength, respectively. can be minimized in the circuit byeliminating the body effect. To minimize the second term in(1), ratio should be increased as much as the rectifier sizeconstraints permit (4800 m 1.6 m).

Fig. 5(b) shows half of the rectifier symmetrical cross section.In order to protect the rectifier against latch-up and substrateleakage, the separated N-well voltage should be dynamicallycontrolled. Two auxiliary pMOS transistors are added to eachrectifying pMOS to connect the separated N-well to or thecoil terminals ( and ), whichever is at a higher potential.The source-side auxiliary pMOS shares its source andgate terminals with the diode-connected and turns onwhenever is ON, connecting the separated N-well to ,which is higher than at this time. The drain-sideauxiliary pMOS shares its source terminal with

Fig. 5. (a) Full-wave CMOS rectifier schematic. (b) Half of the rectifiersymmetrical cross section [21], [23].

and turns on whenever the coil voltage is less than by atleast , connecting the separated N-well to . Sinceno current passes through the auxiliary MOSFETs when theyturn on, their drain-source voltage is close to zero. Therefore,they prevent the parasitic vertical PNP transistors from turningon and leave little chance for latch-up or any leakage currentto the substrate. Another advantage of this circuit, which isalso used in charge pumps [30], is eliminating the body effect


on the rectifying pMOS transistors, thus, reducing the rectifierdrop-out voltage according to (1). On the nMOS transistorsside, common-collector vertical PNP transistors and parasiticdiodes in parallel to and facilitate current returnback to the coil when its voltage goes below the groundedsubstrate by a diode-drop . To decrease the risk oflatch-up even further, the pMOS complexes and the nMOSpair are widely separated in the layout and protected by Nand P guard-rings, respectively [31].

B. High Data Rate Digital FSK Demodulator

Fig. 6(a) shows the receiver block schematic diagram, whichis a high-speed digital FSK demodulator, and Fig. 6(b) showssimulated waveforms at different nodes of the receiver block[19], [20]. A cross-coupled differential pair that is directly con-nected across the tank squares up the incoming sinusoidalFSK carrier signal . An -b ripple counter runsby a time-base clock , which is generated by a five-stagering oscillator, only when is high and resets when islow. The oscillator frequency, MHz, is chosen basedon

(2)

which yields MHz MHz, such that the countermost significant bit (MSB) goes high during long carrier half-cycles at and stays low during short carrier half-cycles at

. Therefore, MSB discriminates between short (logic “0”) andlong (logic “1”) carrier cycles by generating short pulses associ-ated only with the long cycles. A digital circuit then derives thedemodulated serial data bit stream (Data_Out) and a constantfrequency clock (Clock_Out) from a combination of MSB and

.It should be noted that this scheme is highly robust, and as

long as is in the desired range, indicated by (2), the phasenoise and process-dependent frequency variations of the on-chipring oscillator or the external transmitter do not affect the dataand clock recovery performance [20]. In the specific simula-tion of Fig. 6(b), for example, and are chosen equal to8 and 4 MHz, respectively. Nevertheless, the demodulator stillworks because the carrier frequencies still satisfy (2). A latencyof exists between the transmitted and received data,which does not cause a significant problem in this biomedicalapplication.

C. Large Voltage Compliance, High Output ImpedanceCurrent Driver

In current microstimulation applications, the load is highlycapacitive, due to the electrode–electrolyte impedance at theinterface of the metallic stimulating sites and tissue fluids,and variable from one site to another, or during the lifetime ofone site. Therefore, the stimulator output voltage can changesignificantly, which should not affect the desired stimuluscurrent level. Cascode or wide swing cascode current mir-rors are the conventional current sources that are used inmany microstimulator designs including [11]–[16] to generatesite-voltage-independent stimulus currents, while providinghigh output impedance. High output impedance in these cir-

Fig. 6. (a) Phase-coherent FSK demodulator schematic diagram.(b) Demodulator simulated waveforms [19], [20].

cuits comes at the expense of a reduction in voltage compliance(headroom), and an increase in power dissipation in the currentsource due to the unused voltage, both of which are unde-sirable in a wireless implantable microstimulator, where thesupply voltage and permissible temperature rise due to powerdissipation are limited. In IS-2B, pMOS and nMOS versionsof a voltage-to-current conversion circuit, called VCR currentsource and shown in Fig. 2(b), are used in CDs to generatethe stimulus pulses. The VCR current sources/sinks, whichare controlled by voltage-mode DACs, provide larger voltagecompliance, show higher output impedance, and occupy lesscircuit area compared to their conventional counterparts [25],[26]. The following discussion focuses on the nMOS currentsinks, however, it also applies to their dual pMOS currentsource circuits.

In Fig. 2(b), a pMOS-input folded-cascode operational am-plifier (Amp-p) maintains at mV, while DAC-ncontrols the gate voltage according to . All thebiasing and reference voltages and currents are generated froma band-gap reference generator, such that many process-depen-dent parameter variations would cancel out [26]. As long as

, operates in the trioderegion, and the output stimulus current will be defined by

(3)


Fig. 7. (a) Circuit simulation of the VCR output current and transconductanceversus DAC-n control voltage. (b) Comparison between the outputcharacteristics of the VCR and other conventional current sources [25],[26].

which is linear for small values close to . For larger, decreases due to the carrier mobility degradation at

high vertical field and the actual stimulus current is less thanwhat is predicted by (3). On the other hand, the nMOS draincurrent goes above the linear trace versus when it is biasedin saturation. This suggests that if the drain current of in thetriode region is added to the drain current of another transistor,

, biased in the saturation region by receiving a fraction ofon its gate , even though the individual transistor

currents are nonlinear, their sum can be tailored to be linear. Thisprocedure can be repeated when goes out of saturation athigher by adding another parallel nMOS until the entirerange of from to is linearized.

Fig. 7(a) shows the simulated contribution of each indi-vidual parallel nMOS transistor ( – ) to , whichis the sum of all four drain currents, versus . It alsoshows the fairly constant slope of the curve( A/V), which is a measure of the VCRcurrent sink linearity. The effect of each parallel transistor is

Fig. 8. IS-2B die microphotograph and floor-plan [17].

evident from one of the peaks in this curve. Increasing thenumber of parallel transistors reduces the transconductanceripple at the expense of larger circuit area. Fig. 7(b) shows asimulated comparison between the output current versus drivenoutput voltage of the VCR and conventional current sources.All of the current sources were designed to occupy roughly thesame area on a chip mm and sink 100 when thestimulating site voltage is 2.5 V. It is obvious from Fig. 7(b)curves that the VCR current source has the closest outputcharacteristics to an ideal current source [26].

IV. MEASUREMENT RESULTS

The IS-2B chip was fabricated in the AMI 1.5- m two-metaltwo-poly n-well standard CMOS process through the MOSISfoundry by fitting two identical IS-2B modules in a 4.6 mm

4.6 mm die. Fig. 8 shows a die microphotograph andfloor-plan of the IS-2B. The chip was operated as describedin Section II-A, and shown in Fig. 2(a). The command-frameswere generated automatically from user-defined stimulationparameters that were entered into a graphical user interface,called digital pattern generator (DPG-6), running in LabView-7environment. Table II summarizes the experimentally measuredIS-2B specifications [17].

Fig. 9 shows the receiver block measured waveforms. Thereceived 5/10 MHz FSK carrier, which is measured at andas well as their subtraction across the tank, can be seen onthe three lower traces. Depending on the transmitter and receivercoil designs and their orientation, the power amplifier gain ismanually adjusted such that at a nominal coupling distance of5 mm, 24–28 is induced across the tank. The uppertwo traces from top show the recovered clock and demodulatedserial data bit stream at 2.5 MHz and 2.5 Mb/s, respectively. Tothe authors’ knowledge, this is the fastest data rate reported sofar in inductively powered applications [9]–[14]

Fig. 10(a) shows the linearity of the measured stimuluscurrent versus 5-b stimulus amplitude command (DAC’sdigital input) for both VCR current source and current sinkcircuits in the 270 A full-scale current range [also seeFig. 7(a)]. Fig. 10(a) also shows a good matching between


TABLE IIINTERESTIM-2B SPECIFICATIONS

the sourcing and sinking currents for the entire range, whichis important in generating charge balanced stimulus pulses.Fig. 10(b), which is measured with an HP4155A semiconductorparameter analyzer, shows the sinking and sourcing stimuluscurrents at different digital amplitude levels, while sweepingthe site voltage from GND to [also see Fig. 7(b)]. TheVCR current sink (source) can achieve a voltage compliance of97% (95%) of the 5-V supply voltage, while maintaining highoutput impedance in the 100 M range to keep the desiredstimulation currents constant within 1%, irrespective of the siteand tissue impedances [25].

A sample measured stimulation burst is shown in Fig. 11. Thetwo upper traces show the integrated full-wave CMOS rectifierand series regulator outputs. It takes 350 s for the regu-lator to startup and sink current. Meanwhile, the rectifier outputrapidly increases up to 15 V, while charging , which is in-creased to 10 nF with an off-chip surface-mount capacitor toimprove ripple rejection. As soon as the regulator starts sinkingcurrent, the rectified dc voltage reduces to 8 V and stays atthis level, while the regulator stabilizes at 5 V. One advan-tage of the FSK modulation for this application over the morepopular ASK scheme is the absence of the low-frequency rip-ples on the rectified carrier signal due to the carrier amplitudemodulation. The POR activates the global reset line (third trace)at the startup and keeps the entire implant in the reset-mode until70 s after 4.8 V to safely start the digital circuitry froma known state. The receiver block immediately starts recovering

Fig. 9. Receiver block measured waveforms. Top two traces: recovered clockand demodulated data (5 V/div). Bottom three traces: received FSK carrieracross the L C tank (20 V/div) [19].

Fig. 10. (a) Measured current driver I versus 5-b digital current-amplitudecommand. (b) Measured stimulus currents at different digital amplitude levels,while sweeping a stimulation site voltage from GND to V [25], [26].

the serial data bit stream at 2.5 Mb/s (fourth trace), which con-sists of back to back command-frames in the format shown inFig. 4. The stimulation burst, shown on the three lower traces,starts as soon as the digital controller block synchronizes withthe transmitter by detecting the unique frame 0FF 0FFh which issent between every two biphasic stimulation pulses in this spe-cific example.


Fig. 11. Experimentally measured stimulation burst waveforms. From top:CMOS rectifier output, regulator output, POR output, demodulated data bitstream, Site0 single-ended voltage, differential voltage across a 10-k resistorconnected between Site0 and Site4, Site0 single-ended voltage (5 V/div) [17].

A 10-k load, resembling sites and tissue impedances, is con-nected between Site0 and Site4, and the site voltages are mea-sured both differentially and single ended. In this experiment,no external capacitor was added to the resistive load to keep thecurrent and voltage waveforms proportional. Fig. 11 inset showsa magnified view of the four lower traces. In this example, priorinitialization commands have switched and outputmultiplexers to Site0 and Site4, respectively, set the stimuluscurrent amplitudes to full-scale for both phases ( ,

), and selected the operation in Mode-3 (Table I).In every bipolar-biphasic pulse between Site0 and Site4, the firststimulation command connects Site4 (Site0) to a source (sink).As a result, 270 A flows from Site4 to Site0 in the first stimulusphase for the duration of the next command-frame (7.6 s). Thesecond command puts both sites in the high- state to create aninter-phase delay. The third command swaps the sites status andtherefore, 270 A flows back from Site0 to Site4 in the secondstimulus phase. Finally, the fourth command deactivates bothsites by returning them to the high- state. The timing resolu-tion of the IS-2B system is equal to the duration of every 18-bcommand-frame plus the spacer bit, which is 7.6 s at 2.5 Mb/s.This is an order of magnitude finer than the actual neural signalsbandwidth ( 10 kHz). Considering that at least two commandsare required per stimulation phase, IS-2B is capable of gener-ating up to 65 800 pulses/s. The timing accuracy of the IS-2Bsystem (50 ns) depends on the external timing controller, whichis the DIO-6534 high-speed digital I/O card (National Instru-ments, TX) with a 20-MHz internal time-base.

V. CONCLUSION

IS-2B, a 32-site wireless neural microstimulation system ona chip, is developed with a modular stand-alone architecture,which is easily extendable to 64 modules (2048 sites) withonly two connections between every module and a commonreceiver LC tank. IS-2B modules receive inductive power(8.25 mW/module) and high-speed data (2.5 Mb/s) from a5/10 MHz FSK carrier, while generating up to 65 800 stimulus

pulses/s at 270 A full-scale current. Eight current driversper module provide large voltage compliance up to 97% of the5-V supply, and high output impedance in the 100-M range,which are two key parameters in wireless microstimulators.Every 4.6 mm 4.6 mm IS-2B chip, fabricated in the AMI1.5- m standard CMOS process, houses two modules and has atotal of 13 000 transistors. A prototype implant is developed foracute wireless neural microstimulation, using the IS-2B chip.Further in vitro measurements in saline and in vivo experimentsin an animal model (rat) are under way [21], [27].

ACKNOWLEDGMENT

The authors would like to thank Prof. K. D. Wise and Dr. W. J.Heetderks for their guidance.

REFERENCES

[1] J. P. Rauschecker and R. V. Shannon, “Sending sound to the brain,” Sci-ence, vol. 295, pp. 1025–1029, Feb. 2002.

[2] R. A. Normann. (2004, Apr.) “Sight restoration for individuals withprofound blindness”. [Online] Available: http://www.bioen.utah.edu/cni/projects/blindness.htm

[3] E. Zrenner, “Will retinal implants restore vision?,” Science, vol. 295, pp.1022–1025, Feb. 2002.

[4] K. Cha, K. Horch, and R. A. Normann, “Simulation of a phosphene-based visual field: visual acuity in a pixelized vision system,” Annu.Biomed. Eng., vol. 20, no. 4, pp. 439–449, 1992.

[5] E. Margalit, M. Maia, J. D. Weiland, R. J. Greenberg, G. Y. Fujii, G.Torres, D. V. Piyathaisere, T. M. O’Hearn, W. Liu, G. Lazzi, G. Dagnelie,D. A. Scribner, E. de Juan, and M. S. Humayun, “Retinal prosthesis forthe blind,” Survey Ophthalmol., vol. 47, pp. 335–356, Jul. 2002.

[6] J. Weiner. (2003, winter) “Sight seeing”. USC Health Magazine. [On-line] Available: http://www.usc.edu/hsc/info/pr/hmm/win03/sight.html

[7] G. S. Brindly and W. S. Lewin, “The sensation produced by electricalstimulation of visual cortex,” J. Physiology, vol. 196, pp. 479–493, 1968.

[8] M. Bak, J. P. Girvin, F. T. Hambrecht, C. V. Kufta, G. E. Loeb, and E. M.Schmidt, “Visual sensations produced by microstimulation of the humanoccipital cortex,” Medical Biol. Eng. Comp., vol. 28, pp. 257–259, May1990.

[9] P. R. Troyk, “Reports and presentations,” NIH-NINDS, ContractN01-NS-7-2365, 1997–2001.

[10] J. C. Lin, “Computer methods for field intensity predictions,” in CRCHandbook of Biological Effects of Electromagnetic Fields, C. Polk andE. Postow, Eds. Boca Raton, FL: CRC Press, 1986, ch. 2, pp. 273–313.

[11] W. Liu et al., “A neuro-stimulus chip with telemetry unit for retinal pros-thetic device,” IEEE J. Solid-State Circuits, vol. 35, pp. 1487–1497, Oct.2001.

[12] G. J. Suaning and N. H. Lovell, “CMOS neuro-stimulation ASICwith 100 channels, scalable output, and bidirectional radio-frequencytelemetry,” IEEE Trans. Biomed. Eng., vol. 48, pp. 248–260, Feb. 2001.

[13] K. E. Jones and R. A. Normann, “An advanced demultiplexing systemfor physiological stimulation,” IEEE Trans. Biomed. Eng., vol. 44, pp.1210–1220, Dec. 1997.

[14] K. Arabi and M. A. Sawan, “Electronic design of a multichannelprogrammable implant for neuromuscular electrical stimulation,” IEEETrans. Rehab. Eng., vol. 7, pp. 204–214, June 1999.

[15] C. Kim and K. D. Wise, “A 64-site multishank CMOS low-profile neuralstimulating probe,” IEEE J. Solid-State Circuits, vol. 31, pp. 1230–1238,Sep. 1996.

[16] S. C. DeMarco, W. Liu, P. R. Singh, G. Lazzi, M. S. Humayun, and J. D.Weiland, “An arbitrary waveform stimulus circuit for visual prosthesesusing a low-area multibias DAC,” IEEE J. Solid-State Circuits, vol. 38,pp. 1679–1690, Oct. 2003.

[17] M. Ghovanloo and K. Najafi, “A modular 32-site wireless neural stimu-lation microsystem,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb.2004, pp. 226–227.

[18] M. Ghovanloo, K. D. Wise, and K. Najafi, “Toward a button-sized 1024-site wireless cortical microstimulating array,” in Proc. 1st IEEE/EMBSConf. Neural Engineering, Mar. 2003, pp. 138–141.

[19] M. Ghovanloo and K. Najafi, “A fully digital frequency shift keyingdemodulator chip for the wireless biomedical implants,” in Proc. IEEESouthwest Symp. Mixed-Signal Design, Feb. 2003, pp. 223–227.


[20] , “A wideband frequency shift keying wireless link for biomedicalimplants,” IEEE Trans. Circuits Syst. II, to be published.

[21] , “A multichannel monolithic wireless microstimulator,” presentedat the Proc. IEEE 26th EMBS Conf., Sept. 2004, pp. 4197–4200.

[22] , “Fully integrated power-supply design for wireless biomedical im-plants,” in Proc. IEEE-EMBS Special Topic Conf. Microtechnologies inMedicine and Biology, May 2002, pp. 414–419.

[23] , “Fully integrated wideband high-current rectifiers for inductivelypowered devices,” IEEE J. Solid-State Circuits, vol. 39, pp. 1976–1984,Nov. 2004.

[24] Quatech. (2004, July) “Isochronous serial communication overview”.[Online] Available: http://www.quatech.com/support/comm-over-isochserial.php

[25] M. Ghovanloo and K. Najafi, “A small size large voltage complianceprogrammable current source for biomedical implantable microstimula-tors,” in Proc. IEEE 25th EMBS Conf., Sept. 2003, pp. 1979–1982.

[26] , “A compact large voltage compliance high output impedanceprogrammable current source for biomedical implantable microstimu-lators,” IEEE Trans. Biomed. Eng., to be published.

[27] M. Ghovanloo, K. J. Otto, D. R. Kipke, and K. Najafi, “In vitro andin vivo testing of a wireless multichannel stimulating telemetry mi-crosystem,” presented at the Proc. IEEE 26th EMBS Conf., Sept. 2004,pp. 4294–4297.

[28] Z. Tang, B. Smith, J. H. Schild, and P. H. Packham, “Data transmissionfrom an implantable biotelemeter by load-shift keying using circuit con-figuration modulator,” IEEE Trans. Biomed. Eng., vol. 42, pp. 524–528,May 1995.

[29] W. J. Heetderks, “RF powering of millimeter and submillimeter-sizedneural prosthetic implants,” IEEE Trans. Biomed. Eng., vol. 35, pp.323–327, May 1988.

[30] J. Shin, I. Chung, Y. J. Park, and H. S. Min, “A new charge pump withoutdegradation in threshold voltage due to body effect,” IEEE J. Solid-StateCircuits, vol. 35, pp. 1227–1230, Aug. 2000.

[31] A. Hastings, The Art of Analog Layout. Upper Saddle River, NJ: Pren-tice-Hall, 2001.

Maysam Ghovanloo (S’00–M’04) was born in1973. He received the B.S. degree in electrical engi-neering from the University of Tehran, Tehran, Iran,in 1994, and the M.S. (Hons.) degree in biomedicalengineering from the Amirkabir University of Tech-nology, Tehran, in 1997. He also received the M.S.and Ph.D. degrees in electrical engineering from theUniversity of Michigan, Ann Arbor, in 2003 and2004, respectively. His undergraduate research wasfocused on developing an 8-kW power supply forNd:YAG lasers. At the Etrat Institute of Technology,

he worked on computer interfaces for industrial automotive robotic applica-tions. His M.S. thesis was on development of a multisite physiologic recordingsystem for investigation of neural assemblies, and his Ph.D. research was ondeveloping a wireless microsystem for neural stimulating microprobes.

From 1994 to 1998, he worked part-time at the IDEA Inc., Tehran, wherehe participated in the development of the first modular patient care monitoringsystem in Iran. In December 1998, he founded Sabz-Negar Rayaneh Co. Ltd. tomanufacture physiology and pharmacology research laboratory instruments. Inthe summer of 2002, he was with Advanced Bionics Inc., Sylmar, CA, workingon the design of spinal-cord stimulators. He joined the faculty of North CarolinaState University in August 2004, where he is currently an Assistant Professor inthe Department of Electrical and Computer Engineering.

Dr. Ghovanloo has received awards in the operational category of the 40th and41st DAC/ISSCC student design contest in 2003 and 2004, respectively. He is amember of Tau Beta Pi, the IEEE Solid-State Circuits Society, and biomedicalengineering societies.

Khalil Najafi (S’84–M’86–SM’97–F’00) was bornin 1958. He received the B.S., M.S., and the Ph.D.degrees in 1980, 1981, and 1986 respectively, all inelectrical engineering from the Department of Elec-trical Engineering and Computer Science, Universityof Michigan, Ann Arbor.

From 1986 to 1988, he was employed as aResearch Fellow, from 1988 to 1990 as an AssistantResearch Scientist, from 1990 to 1993 as an AssistantProfessor, from 1993 to 1998 as an AssociateProfessor, and since September 1998, he has been

Professor and Director of the Solid-State Electronics Laboratory, Departmentof Electrical Engineering and Computer Science, University of Michigan.His research interests include micromachining technologies, micromachinedsensors, actuators, MEMS, analog integrated circuits, implantable biomedicalmicrosystems, micropackaging, and low-power wireless sensing/actuatingsystems.

Dr. Najafi was awarded a National Science Foundation Young InvestigatorAward from 1992 to 1997, and was the recipient of the Beatrice Winner Awardfor Editorial Excellence at the 1986 International Solid-State Circuits Confer-ence, the Paul Rappaport Award for co-authoring the best paper published inthe IEEE TRANSACTIONS ON ELECTRON DEVICES, and the Best Paper Award atISSCC 1999. In 2003, he received the EECS Outstanding Achievement Award.He received the Faculty Recognition Award in 2001, and the University ofMichigan’s Henry Russel Award for outstanding achievement and scholarshipin 1994, and was selected Professor of the Year in 1993. In 1998, he was namedthe Arthur F. Thurnau Professor for outstanding contributions to teachingand research, and received the College of Engineering’s Research ExcellenceAward. He has been active in the field of solid-state sensors and actuators formore than twenty years, and has been involved in several conferences and work-shops dealing with solid-state sensors and actuators, including the InternationalConference on Solid-State Sensors and Actuators, the Hilton-Head Solid-StateSensors and Actuators Workshop, and the IEEE/ASME Micro-Electromechan-ical Systems (MEMS) Conference. He is the Editor for Solid-State Sensorsfor IEEE TRANSACTIONS ON ELECTRON DEVICES, an Associate Editor forthe Journal of Micromechanics and Microengineering, Institute of PhysicsPublishing, and an editor for the Journal of Sensors and Materials. He alsoserved as the Associate Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS

from 2000 to 2004, and the Associate Editor for IEEE TRANSACTIONS ON

BIOMEDICAL ENGINEERING from 1999 to 2000.

ieee journal of solid-state circuits, vol. 39, no ... modular 32-site...ieee journal of solid-state...

Documents