IEEE Catalog No. O4CH37 533

Copyright O2004 by the Institute ofElectrica1 and ElectronicEngineers,Inc. 455 Hoes Lane, P.0. Box 1331, Piscataway, NJ08855-1331 *IEEE

IEEE International

Reliability Physics

Symposium Proceedings

nd 42 Annual Phoenix, Arizolia April 2529,2004

Sponsored by the IEEE Electron Devices Society and the IEEE Reliability Society

2804 ~[NTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM

SYMPOSIUM @FIcERS

..................................................... GENERAL CHAIR B.M. Pietrucha, Rowan University

.................................................... VICE GENERAL CHAIR T.G Rost, Texas Instruments

.......................................................................... SECRETARY P. Bechtold, Agere Systems

FINANCE ................................................................................... T.M. Moore, Omniprobe

TECHNICAL PROGRAM ...................................................................... C.D. Graas, IBM

PUBLICITY .................................................................... S. Krishnan, Texas Instruments

REGISTRATION ........................................................ D.L. Barton, Sandia National Labs

ARRANGEMENTS ................................................................................ J . . Suehle, NIST

AUDIO.VISUAL ........................................................ C.R. Messick, Northrop Gnunman

PUBLICATIONS .................................................................................... Yew. Eu, TSMC

EXHIBITS ................................................................. E.I. Cole, Jr., Sandia National Labs

TUTORIAL ........................................................ R.C. Lacoe, The Aerospace Corporation

WORKSHOPS .................................................................... G.B. Alers, Novellus Systems

CONSULTANT ................................................................... R.C. Walker, SAR Associates

CONSULTANT ........................................................... D.F. Barber, Scien-Tech Associates

E.S. Snyder, Chair Intel

A.N. Campbell N.R. Mielke Sandia National Labs Intel

L.A. Kasprzak Consultant

B.M. Pietrucha Rowan University

H.A. Schafft NIST

A.G. Street QUALCOMM

J.W. McPherson T. A. Rost W.R. Tonti Texas Instruments Texas Instruments IBM

PUBLISHED BY THE ELECTRON DEVICE SOCIETY AND THE RELIABILITY SOCIETY

OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC.

Copyright and Reprint Permission: Abstracting is pennitled with credit to the source. Libraries are permitted to photocopy beyondihe limits of US. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the permpy fee indicated in the code is paidthrough the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Sewice Center, 445 Hoes Lane, P.O. Box 1331, Piscalaway, NJ 00855.1331. All rights reserved. Copyright @ 2004 by the Institute of Electrical and Electronics Engineers, Inc.

IEEE Catalog No. 04CH37533 ISBN: 0-7803-8315.X SoftboundEditmn

Library of Congress Number: 82-640313

Nega S. MI

Hot c M.F.

Mod H. A

Two S. TJ

A m S.S.

The R.C P.4 J. d

PREFACE by Bernie Pietrucha

This 42nd edition of the IRPS proceedings represents not only the fine work of a record number of authors but also the many hours of labor by the Technical Program and Management committees whose only reward is your satisfaction. The extensive IRPS review process assures that presented papers and posters deal with state-of-the-art developments in microelectronic reliability. Our proceedings should prove to be a valuable reference for you when you return to your company and implement some of the knowledge and experience that you gained during our time together at the Symposium.

Our keynote speaker, Dr. Hans Stork, the chief technical officer of Texas Instruments, will provide us with his keen insight into current issues affecting our industry on Tuesday morning to kick off the Symposium technical sessions. On the lighter side, Dr. Jim Lloyd from IBM will speak at the Tuesday evening poster and awards reception. He will recount some of the major developments in the history of flight coupled with some of his own experiences as a pilot.

The CDROM companion to the proceedings, which you received as part of your registration package, contains files where color is used which can make viewing data graphsand charts a little easier. Abstracts ofthe Sunday and Monday tutorials can also be found on the last two pages of these proceedings.

A virtual IRPS 2004 on DVD-ROMs will be available soon after the Symposium (check www.irps.org for availability) that contains video, audio, and presentation material for all of the technical presentations. We hope that you enjoy the Symposium and that you will consider joining us again at another IRPS.

NOVELTRANSISTOR RELIABILITY FINDINGS Broad energy distribution of NBTI-induced interface states in P-MOSFETs with ultra-thin nitrided oxide J.H. Stathis, G. LaRosa, and A. Chou ....................................................................................................................................................... 1

Negative bias temperature instability in triple gate transistors S. Maeda, J. -A. Choi, J. -H. Yang, Y. -S. Jin, S. -K. Bae, Y.-W. Kim, and K.-P. Suh ............................................................................... 8

Investigation of hot carrier effects in n-MISFETs with HfSiON gate dielectric M. Takayanagi, T. Watanabe, R. Iijima, K. Zshimaru, and Y. Tsunashima ........................................................................................... 13

Hot carrier degradation in novel strained-Si nMOSFETs M.F. Lu, S. Chiang, A. Liu, S. Huang-Lu, MS. Yeh, J.R. Hwang, T.H. Tang, W.T. Shiau, M.C. Chen, and T. Wang ......................... 18

TRANSISTORS I Modeling of NBTI degradation and its impact on electric field dependence ofthe lifetime

....................................................................... H. Aono, E. Murakami, K. Okuyama, A. Nishida, M. Minami, Y. Ooji, and K. Kubota 23

Two concerns about NBTI issue: gate dielectric scaling and increasing gate current S. Tsujikawa, Y. Akamatsu, H. Umeda, and J. Yugami .......................................................................................................................... 28

A new waveform-dependent lifetime model for dynamic NBTI in PMOS transistor S.S. Tan, T.P. Chen, C.H. Ang, and L. Chan .......................................................................................................................................... 35

Hole trapping effect on methodology for DC and AC negative bias temperature instability measurement in PMOS transistors .......................................................................................................................................................................... V: Huard andM. Denais 40

SRAM subthreshold current recovery after unipolar AC stressing ................................................................................................... a S. Kurnar, W.B. Knowlton, S. Kasichainula, C. Payan, andA. Thupil 46

BACK-END INTEGRATION (Invited) Convergence and interaction of BEOL and BE reliability methodology

I .................................................................................................................. S. Rzepka, M. Lepper, M. Bottcher, R Bauer, andS. Weber 49

Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric R.G. Filippi, J.F. McGrath, T.M. Shaw, C.E. Murray, H.S. Rathore, P.S. McLaughlin, V. McGahay, L. Nicholson, P.-C. Wang, J.R. Lloyd, M. Lane, R. Rosenberg, X. Liu, Y.-Y. Wang, W. Landers, T. Spooner, J J. Demurest, B.H. Engel, J. Gill, G. Goth, E. Barth, G. Biery, C.R. Davis, R.A. Wachnik, R. Goldblatt, T. Ivers, A. Swinton, C. Barile, andJ. Aitken ............. 61

Measurements of effective thermal conductivity for advanced interconnect structures with various composite low-k dielectrics F. Chen, J. Gill, D. Harmon, T. Sullivan, B. Li, A. Strong, H. Rathore, D. Edelstein, C-C. Yang, A. Cowley, andL. Clevenger ........ 68

iii

Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies S.-C. Lin, A. Basu, A. Keshavarzi, V. De, A. Mehrotra, and K. Banerjee .............................................................................................. 74

GATE DIELECTRICS I-S102 Impact of gate oxide breakdown of varying hardness on narrow and wide nFET's B. Kaczer, A. De Keersgieter, S. Mahmood, R. Degraeve,, and G. Groeseneken ................................................................................. 79

Off-state mode TDDB reliability for ultra-thin gate oxides: new methodology and the impact of oxide thickness scaling E. Wu. E. Nowak, and W. Lai .................................................................................................................................................................. 84

Acceleration factors and mechanistic study of progressive breakdown in small area ultra-thin gate oxides J. S. Suehle, B. Zhu, Y. Chen, andJ.B. Bernstein .................................................................................................................................. 95

Impact of stress induced leakage current on power-consumption in ultra-thin gate oxides W. Lai, J. Sune, E. Wu, andE. Nowak .................................................................................................................................................. 102

Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics B.J. Cheek, N. Stutzke, S. Kumar, R.J. Baker, A.J. Moll, and W.B. Knowlton ..................................................................................... 110

Gate dielectric degradation mechanism associated with DBIE evolution ................................................................................ K.L Pey, R. Ranjan, C.H. Tung,' L.J. Tang, W.H. Lin, andM.K. Radhakrishnan 117

Degradation of ultra-thin oxides with tungsten gates under high voltage: wear-out and breakdown transient F. Palumbo, S. Lombardo, J.H. Stathis, K Narayanan, F.R. McFeely, andJ.J. Yurkas ..................................................................... 122

LATCHUP Contention-induced latchup J. T. Mechler, C. Brennan, J. Massucco, R. Rossi, L. Wissel ................................................................................................................. 126

Model-based guidelines to suppress cabIe discharge event (CDE) induced latchup in CMOS Ics ........................................... K. Chatty, P. Cottrell, R. Gauthier, M. Muhammad, F. Stellari, A.J. Weger, P. Song, andM. McManus 130

The influence of deep trench and substrate resistance on the latchup robustness in a BICMOS silicon germanium technology S.H. Voldman and A. Watson 135 ................................................................................................................................................................. The influence of heavily doped buried layer implants on electrostatic discharge (ESD) latchup and silicon germanium heterojunction bipolar transistor in a BICMOS SIGE technology S.H. Voldman, L. Lanzerotti, W. Morris, and L. Rubin ........................................................................................................................ 143

PRODUCTS AND CIRCUITS I Reliability and design qualification of a sub-micron tungsten silicide E-fuse W.R. Tonti, J.A. Fzfield, J. Higgins, W.H. Guthrie, W. Berry, andC. Narayan .................................................................................... 152

A new experimental method for evaluation electric field at the junctions of DRAM cell transistors and the effect of electric field strength on the retention characteristics of DRAM Y. Mori, Y. Takeda, S. Kimura, K. Ohyu, H. Uchiyama, andR.4 Yamada ...... : .................................................................................. 157

Characterization of the time-dependent reliability fallout as a function of yield for a 130nm S U M device and application to optimize production burn-In K.R. Forbes andP. Schani ..................................................................................................................................................................... 165

PMOS NBTI-induced circuit mismatch in advanced technologies M. Agosfinelli, S. Lau, S. Pae, P. Marzog H. Muthali, andS. Jacobs ................................................................................................. 171

GATE DIELECTRICS II-HIGH K Reliability assessment of ultra-thin HfO, oxides with TiN gate and polysilicon-n+ gate X. Garros, C. Leroux, G. Reimbold, J. Mitard, B. Guillaumot, F. Martin, andJ.L. Autran ................................................................ 176

Correlation between stress-induced leakage current (SILC) and the HfFO, bulk trap density in a SIO,/HfOZ stack F. Crupi, R. Degraeve, A. Kerber, D.H. Kwak, and G. Groeseneken ................................................................................................. 181

Carrier separation analysis for clarifying leakage mechanism in unstressed and stressed H£4IO$3O2 stack dielectric layers W. Mizubayashi, N. Yasuda, H. Ota, H. Hisamatsu, K. Tominap, K. Iwamoto, K. Yamamoto, T. Horikawa, T. Nabatame, and A. Toriumi 188 ................................................................................................................................................................

MEMORY l (Invited) Magnetoresistive Random Access Memory (MRAM) and reliability

......................................................................................................................................................................................... B. Hughes

Reliabi J. Rod J. McP

Reliab A. Chi

(Invite C. -K. Rosen

The ir M. H. Y.J. C

Stress C.J. i

Ident of plr T. U!

Inve J. -H

Cali' J. M. Wall

Wid J. T.

Reliability properties of low voltage PZT ferroelectric capacitors and arrays J. Rodriguez, K. Remack, K. Boku, K.R. Udayakumar, S. Aggarwal, S. Summegelt, T. Moise, H. McAdams, J. McPherson, R. Bailey, M. Depner, and G. Fox ................................................................................................................................ 200

Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories A. Ztri, D. Zelmini, A.L. Lacaita, A. Pirovano, F. Pellizzer, andR. Bez ................................................................................................ 209

Reliability of flash memory erasing operation under high tunneling electric fields .................................................................................................................................................................... A. Chimenton and P. Olivo 216

INTERCONNECTS (Invited) Effects of overlayers on electromigration reliability improvement for CuAow k interconnects C.-K. Hu, D. Canaperi, S.T. Chen, L.M. Gignac, B. Herbst, S. Kaldor, M. Krishnan, E. Liniger, D.L. Ruth, D. Restaino, R.

............................................................................................... Rosenberg, J. Rubino, S. -C. Seo, A. Simon, S. Smith, and W. -T. Tseng 222

The improvement of copper interconnect electromigration resistance by capldielectic interface treatment and geometrical design M.H. Lin, Y.L. Lin, J.M. Chen, C.C. Tsai, MS. Yeh, C.C. Liu, S. Hsu, C.H. Wang, Y.C. Sheng, K.P. Chang, K.C. Su,

....................................................................................................................................................................... Y. J. Chang, and T. Wang 229

Stress modeling of Cu/low-k BEOL - application to stress migration C.J. Zhai, H. W. Yao, P.R. Besser, A. Marathe, R.C. Blish ZZ, D. Erb, C. Hau-Riege, Sidharth, and K.O. Taylor .............................. 234

Stress-induced voiding in multi-level CopperAow-k interconnects Y.K. Lim, Y.H. Lim, C.S. Seet, B.C. Zhang, K.L. Chok, K.H. See, T.J. Lee, L.C. Hsia, and K.L. Pey ................................................. 240

Identification of electromigration dominant diffusion path for Cu damascene interconnects and effect of plasma treatment and barrier dielectrics on electromigration performance T. Usui, T. Oki, H. Miyajima, K. Tabuchi, K. Watanabe, T. Hasegawa, and H. Shibata .................................................................. 246

MEMS Investigation of reliability problems in thermal inkjet printhead

.................................................................................... J.-H. Lim, K. Kuk, S.-J. Shin, Baek, Y.-J. Kim J.- W. Shin, and Y.S. Oh 251

Calibration and optimization of interconnects based MEMS test structures for predicting thermo-mechanical stress in metallization J.M.M. dos Santos, A.B. Horsfall, J. C. Prata Pina, N.G. Wright, A.G. 0 'Neill, K. Wang, S.M. Soare, S.J. Bull, J.G. Terry, A. J.

.................................................................................................................................... Wahon, A.M. Gundlach and J. T.M. Stevenson. 255

Wideband and high reliability RF-MEMS switches using PZT/HfOZ multi-layered high k dielectrics J. Tsaur, K. Onodera, T. Kobayashi, M. Zchiki, R. Maeda, and T. Suga ......................................................................................... 259

TRANSISTORS II PMOS drain breakdown voltage walk-in: a new failure mode in high power BiCMOS applications D. Brisbin, A. Strachan, andP. Chaparala ........................................................................................................................................... 265

Dynamic positive bias temperature instability characteristics of ultra-thin HfO, NMOSFET S.J. Rhee, Y. H. Kim, C.Y. Kang, C.S. Kang, H.-J. Cho, R. Choi, C.H. Choi, MS. Akbar, andJ.C. Lee ............................................ 269

A comprehensive framework for predictive modeling of negative bias temperature instability S. Chakravarthi, A.T. Krishnan, K Red& C.F. Machala and S. Krishnan ........................................................................................ 273 .. Hot-carrier injection in step-drift RF power LDMOSFET

.................................................................................................................................................................. G. Cao and M.M. De Souza 283

SERISEU Comparison between Neutron-Induced Sy stem-SER and Accelerated-SER in SRAMs H. Kobayashi, H. Usuki, K. Shiraishi, H. Tsuchiya, N. Kawamoto, G. Merchant, and J. Kase ........................................................ 288

Process impact on SRAM alpha-particle SEU performance ...................................................... Y.Z. Xu, H. Puchner, A. Chatila, 0 . Pohland, B. Bruggeman, B. Jin, D. Radaelli, andS. Danieli 294

SRAM SER in 90,130 and 180 nrn bulk and SO1 technologies ................................................................................................. E.H. Cannon, D.D. Reinhardt, M.S. Gordon, andP.S. Makowenskyj 300

Neutron-induced soft-error in logic device using quasi-monoenergetic neutron beam S. Yamamoto, K. Kokuryou, Y. Okada, J. Komori, E. Murakami, K. Kubota, N. Matsuoka, and Y. Nagai ....................................... 305

Transistor sizing for radiation hardening ................................................................................................................................................................... Q. Zhou and K. Mohanram 310

BACK-END DIELECTRICS (Invited) Comprehensive reliability evaluation of a 90 nm CMOS technology with CuPECVD low-k BEOL D. Edelstein, H. Rathore, C. Davis, L. Clevenger, A. Cowley, T. Nogami, B. Agarwala, S. Arai, A. Carbone, K. Chanda, F. Chen, S. Cohen, W. Cote, M. Cullinan, T. Dalton, S. Das, P. Davis, J. Demurest, D. Dunn, C. Dziobkowski, R. Filippi, J. Fitzsimmons, P. Flaitz, S. Gates, J. Gill, A. Grill, D. Hawken, K. Ida, D. Klaus, N. Klymko, M. Lane, S. Lane, J. Lee, W. Landers, W-K Li, Y-H. Lin, E. Liniger, X-H. Liu, A. Madan, S. Malhotra, J. Martin, S. Molis, C. Muzzy, D. Nguyen, S. Nguyen, M. Ono, C. Parks, D. Questad, D. Restaino, A. Sakamoto, T. Shaw, Y. Shimooka, A. Simon, E. Simonyi, A. Swift, T. Van Kleeck, S. Vogt, Y-Y. Wang, W. Wille, J. Wright, C-C. Yang, M. Yoon, and T. Ivers ......................................................... 316

Highly reliable dielectriclmetal bilayer sidewall diffusion barrier in Cu/porous organic ultra low-k interconnects Z. Chen, K. Prasad, C. Y. Li, P. W. Lu, S.S. Su, andL.J. Tang .............................................................................................................. 320

Impact of the barrierldielectric interface quality on reliability of cu porous-low-k interconnects Z. Tokei, V Sutclzfe, S. Demuynck, F. Iacopi, P. Roussel, G.P. Beyer, R.J.OM. Hoofian, and K. Maex ......................................... 326

Reliability improvement using buried capping layer in advanced interconnects K.Y. Yiang, T.S. Mok, W.J. Yoo, andA. Krishnamoort/y ..................................................................................................................... 333

TDDB reliability assessments of 0.13 pm Cullow-k interconnects fabricated with PECVD low-k materials N. Hwang, M. C. A. Micaller-Silvestre, C.F. Tsang, J. Y.-J. Su, C.C. Kuo, and A.D. Trigg .......................................................... 338

FAILURE ANALYSIS Finding voids in dual damascene Cu vias and their impact on reliability

.................................................................................................... W. Dong, J. Ji, S. Liang, M. Zhang, S. Liao, C. Niou, and K. Chien 343

A new breakdown failure mechanism in HfO, gate dielectric R. Ranjan, K.L. Pey, L.J. Tang, C.H. Tung, G. Groeseneken, M.K Radhakrishnan, B. Kaczer, R. Degraeve, S. De Gendt ............ 347

C-V and C-P characterization sensitivities for fast and slow-state traps in very thin oxide MOSFETs J.-Y. Rosaye, Y. Yasuda, A. Sakai, P. Mialhe, J.-P. Charles, and Y. Wafanabe .................................................................................... 353

Thermal laser stimulation of active devices in silicon-a quantitative FET parameter investigation C. Boit, A. Glowacki, S. Brahma, andK. Wirth .................................................................................................................................... 357

Positive photon discrimination for ultra low voltage IC analysis R. Desplafs, M. Remmach, G. Faggion, F. Beaudoin, P. Perdu, M. Leibowitz, K. Sanchez, S. Guilaume, T. Lundquist, and D. Lewis ....................................................................................................................................... 361

Transient-LU failure analysis of the ICs, methods of investigation and computer aided simulations ........................................................................ K. Domanski, S. Bargstadt-Franke, W. Stadler, M. Streibl, G. Steckert, and W. Bala 370

Structural analysis of integrated circuits using scanning laser ultrasonics G. Andriamonje, V. Pouget, Y. Ousten, D. Lewis, B. Plano, andY. Danto ....................................................................................... 375

ESD Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13 pm CMOS integrated circuits M.-D. Ker and K.-C. Hsu ............................ ............... .......................................................................................................................... 381

Base pushout driven snapback in parasitic bipolar devices between different power domains .................................................................... U. Glaser, J. Schneider, M. Streibl, K. Esmark, S. Druen, H. Gobner, and W. Fichtner 387

Effects of hot spot hopping and drain ballasting in integrated vertical DMOS devices under TLP stress ..................................................................................................... P. Moens, S. Bychikhin, K. Reynders, D. Pogany, andM. Zubeidat 393

Gate dielectric breakdown: a focus on ESD protection BE. Weir, C.-C. Leung, P.J. Silverman, andM.A. Alum ...................................................................................................................... 399

A PMOSFET ESD failure caused by localized charge injection J.-H. Chun, C. Duwury, G. Boselli, H. Kunz, andR W. Dutton .......................................................................................................... 405

RF PRODUCTSAND CIRCUITS RF HCI testing methodology and lifetime model establishment W.L. Ng, and N. Toledo ......................................................................................................................................................................... 412

Reliability evaluation and comparison of Class-E and Class-A power amplifiers with 0.18 pm CMOS technology W.-C. Lin, L. -J. Du and Y.-C. King ................................................................................................................................................. 4 15

Effects of hot-carrier stress on the performance of CMOS low noise amplifier S. Naseh andM.J. Deen ......................................................................................................................................................................... 417

RF S-pa J.P. Wa

(Invited K. Merer

A metb P. W. A4

A chip, Y. Che?

Hot-cal Z. Jin, . Qua1 ifi Y.P. KI

Hot ca T. TSUI

Enhan D.Q. 1

Degral Y.C. C Q. Ka,

Bipolr VA. T,

Failur G. Me A. CG

Integl G. Be J. Pe

Impa' m d g K.-Y. J. -B.

Patte J.R. : Inve! J. G. A. L

I

A 14 L. ~1

Cha. T. C.

C.

RF S-parameter degradation under hot carrier stress .................................................................................................................................................................... J.P. Walko andB. Abadeer 422

PRODUCTSAND CIRCUITS I 1 (Invited) 6-T cell circuit dependent GOX SBD model for accurate prediction of observed vccmin test voltage dependency K. Mueller, S. Gupta, S. Pae, M. Agostinelli, andP. Aminzadeh .................................................................................................... 426

A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits P. W. Mason, A.J. La Duca, C. H. Holder, MA. Alum, andD.K. Hwang ............................................................................................. 430

A chip and pixel qualification methodology on imaging sensors Y. Chen, S.M. Guertin, M. Petkov, D.N. Nguyen, and F. Novak .......................................................................................................... 435

Hot-carrier stress induced low-frequency noise degradation in 0.13 pm and 0.18 pm RF CMOS technologies ........................................................................... 2. Jin, J.D. Cressler, W. Abadeer, X. Liu, M. Hauser, andA.J. Joseph : ................. 440

Qualification method for DRAM retention by leakage current evaluation using subthreshold characteristics of cell transistors Y.P. Kim, B. J. Jin, S. -G. Lee, S. Choi, U. Chung, J. T. Moon, and S. U. Kim ........................................................................................ 445

COMPOUND SEMICONDUCTORS Hot carrier reliability of SiGeISi hetero-interface in SiGe MOSFETs T. Tsuchiya, M. Sakuraba, and J. Murota ............................................................................................................................................ 449

Enhanced hot-electron performance of strained Si NMOS over unstrained Si ......................................................................................... D.Q. Kelly, D. Onsongo, S. Dey, R. Wise, R. Cleavelin, andS.K. Banerjee 455

Degradation mechanism of GaAs PHEMT power amplifiers under elevated temperature lifetest with RF-overdrive Y.C. Chou, R. Lai, R. Grundbacher, M. Yu, D. Leung, L. Callejo, D. Eng, D. Okazaki, B. Yamane, K. Kiyono,

............................................................................................................................................................................... Q. Kan, and A. Oki 463

Bipolar SCR ESD protection in 0.25 pm Si-Ge process using sub-collector region modification V.A. Vashchenko, A. Concannon, M. ter Beek and P. Hopper .............................................................................................................. 469

Failure mechanisms of GaN-based LEDs related with instabilities in doping profile and deep levels G. Meneghesso, S. Levada, E. Zanoni, G. Salviati, N. Armani, F. Rossi, M. Pavesi, M. Manjedi, A. Cavaflini,

............................................................................................................................................... A. Castaldini, S. Du, andl. Eliashevich 474

PROCESS INTEGRATION Integration issues of high-k gate stack: process-induced charging G. Bersuker, J. Gutt, N. Chaudhary, N. Moumen, B.H. Lee, J. Barnett, S. Gopalan, G. Brown, Y. Kim, C.D. Young, J. Peterson, H.-J. Li, P.M. Zeitzofi J.H. Sim, P. Lysaght, M. Gardner, R. W. Murto, and H.R. Huff ................................................ 479

Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced-drain-leakage stress conditions K.-Y. Lim, S.-A. Jang, Y. S. Kim, H.-J. Cho, J.-G. Oh, S.-0. Chung, S.-J. Lee, W.-K. Sun, J. -B. Suh, H.3. Yang, and H.-C. Sohn ................................................................................................................................................. 485

Pattern density effect of trench isolation-induced mechanical stress on device reliability in sub-0.1 pm technology J.R. Shih, R. Wang, Y.M. Sheu, H.C. Lin. J.J. Wang, andKen Wu ....................................................................................................... 489

Investigation of misfit dislocation leakage in supercritical strained silicon MOSFETs J.G. Fiorenza, G. Braithwaite, C. Lei@ M.T. Currie, Z.Y. Cheng, V.K. Yang, T. Langdo, J. Carlin, M. Somerville, A. Lochtefeld, H. Badawi, andM.T Bulsara ....................................................................................................................................... 493

A low cost test vehicle for embedded DRAM capacitor: Investigation and monitoring of the process L. Lopez, D. Nee, P. Masson, and R. Bouchakour ................................................................................................................................ 498

Characterization and reliability of TaN thin film resistors T.C. Lee, K. Watson, F. Chen, J. Gill, D. Harmon, T. Sullivan, and B. Li ...................................................................................... 502

MEMORY I I Statistical analysis of nanocrystal memory reliability C.M. Compagnoni, D. Zelmini, AS. Spinelli, A.L. Lacaita, C. Gerardi, andS. Lombardo ............................................................... 509

A new channel percolation model for VT shift in discrete-trap memories D. Zelmini, C.M. Compagnoni, A.S. Spinelli, A.L. Lacaita, and C. Gerardi ..................................................................................... 515

Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell W.J. Tsai, N.K. Zous, M.H. Chou, S. Huang, H.Y. Chen, Y.H. Yeh, M.Y. Liu, C.C. Yeh, T. Wang, J. Ku, and C.-Y. Lu .................... 522

vii

Retention loss characteristics of localized charge-trapping devices ........................................................................................ E. Lusky, Y. Shacham-Diamand, A. Shappir, I. Bloom, G. Cohen, B. Eitan 527

ASSEMBLY AND PACKAGING Electrical Fails Specific to Pressure Cooker Test

............................................................................................... L. Wiggins, C. Peny, J. Cofin, E. Dyll, M. Fausse, and K. Masanori 531

Degradation mechanisms of siloxane-based thermal interface materials under reliability stress conditions S.L.B. Dal .............................................................. : .............................................................................................................................. 537

Dendrite fuse re-growth kinetics on organic substrates for microprocessors ...................................................................................................................................... D. Lambert, R. Gannamani, and R. C. Blish I1 543

Effect of vacuum on high-temperature degradation of gold/aluminum wire bonds in PEMs A. Teverovsky ......................................................................................................................................................................................... 547

Packaging effect on reliability for Cu/low k structures G. Wang, S.K. Groothuis, andP.S. Ho ................................................................................................................................................. 557

ASSEMBLY AND PACKAGING POSTERS The detection of tin plating and tin whisker mitigation W.D. Bjorndahl, L. Singleton, R. Griese, andE Chong ....................................................................................................................... 563

Electromigration reliability enhancement of flip chip interconnects using Cu-doped SnPb solder J.D. Wu, C.W. Lee, S.Y. Wu, andS. Li ................................................................................................................................................... 565

Reliability and microstructure of lead-free solder die attach interface in silicon power devices ............................................................................... D. Hufi D. Katsis, K. Stinson-Bagby, T. Thacker, G.-Q. Lu, and J. D. van Wyk 567

Interfacial degradation mechanism of AU-AL bonding in quad flat package J. Park, B.4. Kim, H.-J. Cha, Y.-B. Jo, S.-C. Shin, G.-R. Kim, J.-K. Park, M.-Y. Shin, K.-I. Ouh, andH.-G. Jeon .......................... 569

BACK-END DIELECTRICS POSTERS Analysis of leakage mechanisms and leakage pathways in intra-level Cu interconnects

....................................................................................................................................... KC. Ngwan, C. Zhu, andA. Krishnamoorthy 571

Reliability of silicon nitride dielectric-based metal-insulator-metal capacitors T. Remmel, R. Ramprasad, D. Roberts, M. Raymond, M. Martin, D. Qualls, E. Luckowski, S. Braithwaite, M. Miller, andJ. Walls ......................................................................................................................................................................... 573

COMPOUND DEVICES POSTERS The impact of process optimization on planar THz-Schottky device reliability

............................................................................... B. Mottet, C. Sydlo, B. Kogel, Q. de Robillard, 0. Cojocari, and H.L. Hartnagel 575

A study of output power stability of GaN HEMTs on S i c substrates KS. Boutros, P. Rowell, andB. Brar ..................................................................................................................................................... 577

GATE DIELECTRICS POSTERS Lifetime projections and conduction mechanisms for Hafnium based high-k capacitor dielectrics using low thermal budget process

J. H. Lee, J.P. Kim, J. -H. Lee, Y. -S. Kim, H. -J. Lim, H. -S. Jung, S.J. Doh, N. -I. Lee, and H. -K. Kang .............................................. 579

Direct determination of interface and bulk traps in stacked HfO, dielectrics using charge pumping method T.H. Hou, M.F. Wang, K.L. Mai, Y.M. Lin, M.H. Yang, L.G. Yao, Y. Jin, S.C. Chen, andM.S. Liang ............................................... 581

Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxides F. Palumbo, S. Lombardo, K.L. Pey, L.J. Tang, C.H. Tung, W.H. Lin, M.K. Radhakrishnan, and G. Falci ................................... 583

Influence of charge trapping on AC reliability of high-k dielectrics M. Kerber, R. Duschl, H. Reisinger, S. Jakschik, U. Schroder, T. Hecht, andS. Kudelka ................................................................. 585

Effects of thin SiN interface layer on transient I-V characteristics and stress induced degradation of high-k dielectrics C.Y. Kang, H.J. Cho, C.S. Kang, R. Choi, Y.H. Kim, S.J. Rhee, C.H. Choi, S.M. Akbar, and J.C. Lee ........................................ 587

Drain biased TDDB lifetime model for ultra thin gate oxide C.-Y. KO, Y.S. Tsai, P. J. Liao, J.J. Wang, AS. Oates, and K. Wu ..................................................................................................... 589

Polarity dependence of charge trapping in poly-silicon gate HfO, MOSFETs H.M. Bu,X.W. Wang, D.C. Guo, L.Y.Song, T.P. Ma, H. Tseng, andP. Tobin .................................................................................. 591

viii

Gate ox H.-M. f

Effects Y.H. Ki

Charge C.D. Yc

The las K.P. CI

Freque C. She?

Chip4 S. Dru

Enhan~ V. Vas

High c J.H. L<

Compi J. H. L

Failur S. Hsi

Sidem Q. Ga

Gold 1

J.L. K

Gate ! AN. i

Effec H. V.

Effec W. Ll

Stres X. Fe

The i aPPrc H. R

Elec D.A.

Voic Y. -B

Tesl Y. R

The D. A

Gate oxide multiple soft breakdown (multi-SBD) impact on CMOS inverter ............................................................................... H.-M. H~ang, C. Y. KO, M.L. Yang, P.1 Liao, J.J. Wang, A.S. Oates, and K. Wu 593

Effects of gate electrodes and barrier heights on the breakdown characteristics and Weibull slopes ofHfO, MOS devices ............................................................................................................... Y.H. Kim, R. Choi, R. Jha, J.H. Lee, V. Misra, andJ. C. Lee 595

Charge trapping and device performance degradation in MOCVD hafnium-based gate dielectric stack structures ............................................................. C.D. Young, G. Bersuker, G.A. Brown, P. Lysaght, P. Zeitzofj; R. W. Murto, and H.R. HuSf 597

The last trap that form the percolation path-the stress voltage effect ........................................................................................................................................................................................... K.P. Cheung 599

Frequency dependent dynamic charge trapping in HfO, and threshold voltage instability in MOSFETs ............................................................ C. Shen, H.Y. Yu, X.P. Wang, M.-F. Li, Y.C. Yeo, D.S.H. Chan, K.L. Bera, andD.L. Kwong 601

ESD POSTERS Chip-level ESD simulation for fail detection and design guidance S. Druen, M. Streibl, F. Zangl, J. Schneider, U. Glaser, K. Esmark, W. Stadler, H. Gossner, and D. Schmitt-Landsiedel 603 .............. Enhanced ESD protection robustness of a lateral NPN structure in the advanced CMOS

...................................................................................................................... V. Vassilev, G. Groeseneken, M. Steyaert, and H. Maes 605

High current characteristics of copper interconnect under transmission-line pulse (TLP) stress and ESD zapping J.H. Lee, J.R. Shih, K.F. Yu, Y.H. Wu, J.Y. Wu, J.L. Yang, C.S. Hou, and T.C. Ong ........................................................................... 607

Comparison of ultra-thin gate oxide ESD protection capability of silicided and silicideblocked MOSFETs J.H. Lee, J.R. Shih, K.F. Yu, Y.H. Wu, andT.C. Ong ............................................................................................................................ 609

FAILURE ANALYSIS POSTERS Failure analysis on resistive opens with scanning SQUID microscopy S. Hsiung, K. V. Tan, A.J. Komrowski, D.J.D. Sullivan, J. Gaudestad, A. Orozco, E.Talanova, and L.A. Knauss ............................ 61 1

Sidewall damage induced by FIB milling during TEM sample preparation ................................................................................................................................. Q. Gao, M. Zhang, C. Niou, M. Li, and K. Chien 613

Gold dendrite simulation and growth kinetics .......................................................................................................................................................... J.L. Kersey, Jr. andR.C. Blish, II 615

Gate fault isolation and parametric characterization through the use of atomic force probing ......................................................................................................................................................................................... A.N. Erickson 617

INTERCONNECTS POSTERS Effect of thermal gradients on the electromigration lifetime in power electronics H.V. Nguyen, C. Salm, B. Krabbenborg, K. Weide-Zaage, J. Bisschop, A.J. Mouthaan, andF.G. Kuper .......................................... 619

Effects of low k film properties on electromigration performance ............................................................... W. Lu, Y.K. Lim, A. See, T.J. Lee, L.C. Hsia, J. Hander, H. Fu, L.S. Wong, andF.P. Fen 621

Stress induced degradation of 9Onm node interconnects ........................................................................................................................................................................................... X. Feders~iel 623

The influence of surface fluctuations on early failures in single-damascene Cu wires: a weakest link approximation analysis

.............................................................................................................................................. H. Wang, C. Bruynseraede, and K. Maex 625

Electromigration performance enhancement of Cu interconnects with PVD Ta cap ................................................................................................................... D.A. Gajewski, T. Meixner, B. Feil, M. Lien, andJ. Walls 627

Void and extrusion induced failure of submicron multilevel interconnects ..................................................................................................................... Y.-B. Jo, J. Park, C.-H. Jeon, K.-I. Ouh, and H.-G. Jeon 629

MEMS POSTERS Test structures and DRIE topography for bulk silicon MEMS devices

................................................................................................................................................ Y. Ruan, D. Zhang, X. He, and Y. Wang 631

Thermomechanical behavior and reliability of AdSi MEMS structures ................................................................................. D. Miller, C. Herrmann, K. Spark, D. Finch, S. George, C. Stoldt, and K. Gall 633

MEMORY POSTERS Multi-level programming of NOR flash EEPROMs by CHISEL mechanism D.R. Nair, S. Mahapatra, S. Shukuri, and J. Bude ............................................................................................................................... 635

Flash memory under cosmic & alpha irradiation A.D. Fogle, D. Darling, R.C. Blish, IZ, and G. Daszko ....................................................................................................................... 637

Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique S.H. Gu, M. T. Wang, C. T. Chan, N. K. Zous, C.C. Yeh, W.J. Tsai, T. C. Lu, T. Wang, J. Ku, and C. -Y. Lu ..................................... 639

Different approaches for reliability enhancement of p-channel flash memory S.S. Chung, Y. -J. Chen, and H. - W. Tsai ................................................................................................................................................ 64 1

Statistical modeling for post-cycling data retention of split-gate flash memories L.-C. Hu, A.-C. Kang, I. -T. Liec, Y. -F. Lin, K. Wu, and Y. -C. King ....................................................................................................... 643

PRODUCTSAND CIRCUITS POSTERS Development and use of a miniaturized health monitoring device V. Rouet and B. Foucher ........................................................................................................................................................................ 645

Standby current prediction model for microprocessors reliability risk assessment B. Lisenker ............................................................................................................................................................................................. 647

CMOS transistor electrical ageing experiments to build VHDL-AMS behavioral models B. Mongellaz, F. Marc, and Y. Danto .................................................................................................................................................... 649

Local redesign for reliability of CMOS digital circuits under device degradation X. Xuan, A. Chattetjee, andA.D. Singh ................................................................................................................................................ 651

Soft breakdown effects on MOS switch and passive mixer A. Sadat, Y.Liu, J. Yuan, andH. Xie ....................................................................................................................................................... 653

Thermal runaway avoidance during burn-in Arman Vassighi, OlegSemenov, andManoj Sachdev .................................................................................................................... 655

Reliability model and implementation for EEPROM emulation using flash memory C. He, P. Kuhn, T. Jew, andM. Niset .................................................................................................................................................... 657

New screen methodology for ultra thin gate oxide technology A. Wang, C.H. Wu, R.Y. Shiue, H.M. Huang, andK. Wu ..................................................................................................................... 659

The challenge to record correct fast WLR monitoring data from productive wafers and to set reasonable limits A. Martin, J. Fazekas, A. Pietsch, and W. Muth .................................................................................................................................... 661

PROCESS INTEGRATION POSTERS Layout design dependence of NBTI for I/O p-MOSFET V. Koldyaev ............................................................................................................................................................................................ 663

Effect of magnetic field on plasma damage during VIA etching in sub-micron CMOS technology NS. Kim, H.G. Yoon, C.K. Lee, J. Zhao, C.Y. Tuck, Y.S. Cheah, W. W. Yew, P. Southworth, S.H. Han, andK.S. Pey ...................... 665

Thermal degradation of DRAM retention time: characterization and improving techniques Y.X. Kim, K.H. Yang, and W.S. Lee ........................................................................................................................................................ 667

SEFUSEU POSTERS Threshold energy of neutron-induced single event upset as a critical factor Y. Yahagi, E. Ibe, Y. Takahashi, Y. Saito, A. Eto, M. Sato, H. Kameyama, M. Hidaka, K. Terunuma, T. Nunomiya, and T. Nakamura ........................................................................................................................................................... 669

An alpha immune and ultra low neutron SER high density SRAM P. Roche, F. Jacquet, C. Caillat, andJ. -P. Schoellkopf.. ....................................................................................................................... 67 1 I

Modeling and verification of single event transients in deep submicron technologies ~ M.J. Gadlage, R.D. SchrimpJ J.M. Benedetto, P.H. Ealon, and T.L. Turflinger ................................................................................ 673

I Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs T. Heijmen, B. Kruseman, R. van Veen, andM. Meijer ....................................................................................................................... 675

Neutron. J. Bag@ B. S a p

NBTI el Y.J. Lee

PMOS 1 M.S Akl

Hydrog J . 3 Le

New f i ~ J. Zhan

Mechal B. Zhu,

Locali2 B.H. LI

Biogra:

Page K

~ ~ ~ t ~ ~ ~ - i ~ d u ~ e d SEU in bulk and SO1 SRAMs in terrestrial environment J. Baggio, D. Lambert, V. Ferlet-Cavroi~, C. D'hose, K. Hirose, H. Saito, J.M. Palau, F. Saignd, . . B. Sagnes, N. Buard, and T. Carrrere ................................................................................................................................................... 677

TRANSISTORS POSTERS Reliability investigations on a unique direct-tunneling-induced high performance partially-depleted 501 PMOS device s.-S. Chen, S. Huang-Lu, T.-H. Tang, and W.-T. Shiau ....................................................................................................................... 679

NBTI effects of pMOSFETs with different nitrogen dose implantation Y.J. Lee, Y.C. Tang, M.H. Wu, T.S. Chao, P.T. Ho, D. Lai, W.L. Yang, and T.Y. Huang ................................................................. 681

PMOS thin gate oxide recovery upon negative bias temperature stress M.S Akbar, M. Agostinelli, S. Rangan, S. Lau, C. Castillo, S. Pae andS. Kashyap ............................................................................ 683

~~drogen-related extrinsic oxide trap generation in thin gate oxide film during negative-bias temperature instability stress J.-S. Lee, J. W. Lyding, and K. Hess ...... ... ..... ........ ..... ... ..... . . ........ . . . ..... ... ... ..... ..... ........ ........ ... ............. . . . . ........ . . . 685

New findings on NBTI in partially depleted SO1 transistors with ultra-thin gate dielectrics J. Zhang, A. Marathe, K. Taylor, E. Zhao, andB. En ..................................................................................................... ...................... 687

Mechanism for reduced NBTI effect under pulsed bias stress conditions 8. Zhu, J.S. Suehle, andJ.B. Bernstein .................................................................................................................................................. 689

Localized transient charging and it's implication on the hot carrier reliability of HfSiON MOSFETs B.H. Lee, J.H. Sirn, R. Choi, G. Bersuker, K. Matthew, N. Moumen, J.J. Peterson, and L. Larson ................................................. 691

Biographies ............................................................................................................................................................................................. 693

Page Number Cross-reference to Sessionk'oster Paper # ............................................................................................... . ................ 737

2004 Committees .................................................................................................................................................................................. 738

2002 Paper Awards .............................................................................................................................................................................. 743

2004 Tutorial Program Abstracts .......................................................................................................................................................... 745