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Reduction of Positive Feedback Gain on Anti- Islanding Method Based on Frequency Cassius R. Aguiar, Amilcar F. Q. Gonc;alves, Renan F. Bastos, Giovani G. Pozzebon, Jose R. B. A. Monteiro, Ricardo Q. Machado University of Sao Paulo, Sao Carlos, SP, Brazil E-mails:[email protected]@sc.usp.br Abstract - This paper presents a study to reduce the positive feedback gain in Anti-islanding detection methods based on frequency positive feedback. The main idea is to reduce the injection of disturbances at the point of common coupling (peC) during the grid-connected operation. This proposal refers to the closed-loop frequency adjustment of the synchronization algo- rithm PLL (phase Locked Loop). Firstly, is presented the anti- islanding method used in this work and introduced the controller design of the PLL algorithm for islanding detec- tion. In order to evaluate the paper, simulation and experimental results are shown to support these statements. Index Terms - Islanding Detection, Distributed Generation, PLL. I. INTRODUCTION The connection of distributed generation (DG) systems us- ing AC-DC voltage source inverter (VSI) are the target of intense research in order to promote solutions to the problems of instability and detection of contingencies when DG sys- tems operate connected to the main grid. In this context, an important requirement for the integra- tion of DG systems in the electric power system is the ability of the DG to detect contingencies. The islanding is defined as a portion of the utility system that contains both load and distributed resources that remains energized while it is isolat- ed from the remainder utility system [1]. It may lead to power-quality issues, equipment damage, malfunction in protection devices, and even safety hazards to the personnel staff. Anti-islanding (AI) is still a major issue to DG users and utilities since the possibility of islanding occurrence increases as the DG penetration has drastically been growing over the last decade [1]. AI methods which reside in the controller of the VSI can be classified as passive and active methods. Passive methods continuously monitor the system parameters, such as fre- quency, voltage, harmonic distortion, etc. In this method, these parameters have been considerably changed when the grid is islanded [2, 3] however passive islanding detection techniques suffer from large non-detection zones (NDZs) [3]. Active methods have been designed to force DG to be un- stable when a contingency occurs. These methods enable the continuous effect of positive feedback (PF) on voltage or frequency shift and effectively destabilize the system in is- landing operation [4]. The main advantages of active methods over passive methods are their small NDZ. However, the main drawbacks of the active methods are that the injected disturbances may reduce the power quality at the PCC [5]. A higher PF gain will contribute to AI more positively in islanded conditions, whereas it will give more negative im- pacts on power quality in grid-connected conditions [4, 6]. In this paper is presented a study about the impact ofPLL algorithm in the performance of active AI method based on frequency PF. The main idea is to reduce the PF gain without degrading the performance of the AI method and consequently low injection disturbances at the PCC. The paper is arranged as follows: Section II describes the analysis of the AI method. The design of PLL is presented in the sections III. Finally, the section IV and V presented the simulation and experimental results and the section VI con- cludes the paper. II. ANALYSIS ANTI-ISLANDING METHODS AI methods with PF can be implemented in two different ways for inverter-based DGs to prevent islanding, known as the voltage and frequency AI method. The frequency AI method applies a PF to the PCC voltage's frequency and it tries to destabilize the DG by modifying the inverter's output current in order to detect the islanding. The voltage AI meth- od uses the variation in the voltage magnitude at the PCC to obtain the output !lid [7] . A. Frequency Positive Feedback (FPF) The frequency positive feedback AI, proposed in [8, 9] de- tects the variations in the frequency (Wpll) to generate the output !liq which disturbs the quadrature-axis current refer- ence to the DG iq]ef [6, 7]. Fig. 1 demonstrates the Frequency PF method. The frequency PF consists of a washout filter, a gain and a first-order filter. The critical settings include [10]: • The frequency of the washout filter, Tw • The PF gain, k FPF The low pass filter frequency, To The transfer function of the frequency PF is represented in (1) [7, 11, 12]. sTw HFPF(s) = k FPF (1 + sTw)(1 + sTo) (1) The combined washout and the low-pass filter constitute a band-pass filter. The selection of PF gain is a compromise between the high enough gain to ensure islanding detection quickly and the low PF gain to have minimal impact on the DG system under the grid-connected operation [7, 11 , 12]. 978-1-4799-0224-8/13/$31.00 © 2013 IEEE 7795

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Page 1: [IEEE IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society - Vienna, Austria (2013.11.10-2013.11.13)] IECON 2013 - 39th Annual Conference of the IEEE Industrial

Reduction of Positive Feedback Gain on Anti­Islanding Method Based on Frequency

Cassius R. Aguiar, Amilcar F. Q. Gonc;alves, Renan F. Bastos, Giovani G. Pozzebon, Jose R. B. A. Monteiro, Ricardo Q. Machado

University of Sao Paulo, Sao Carlos, SP, Brazil E-mails:[email protected]@sc.usp.br

Abstract - This paper presents a study to reduce the positive feedback gain in Anti-islanding detection methods based on frequency positive feedback. The main idea is to reduce the injection of disturbances at the point of common coupling (peC) during the grid-connected operation. This proposal refers to the closed-loop frequency adjustment of the synchronization algo­rithm PLL (phase Locked Loop). Firstly, is presented the anti­islanding method used in this work and introduced the controller design of the PLL algorithm for islanding detec­tion. In order to evaluate the paper, simulation and experimental results are shown to support these statements.

Index Terms - Islanding Detection, Distributed Generation, PLL.

I. INTRODUCTION

The connection of distributed generation (DG) systems us­ing AC-DC voltage source inverter (VSI) are the target of intense research in order to promote solutions to the problems of instability and detection of contingencies when DG sys­tems operate connected to the main grid.

In this context, an important requirement for the integra­tion of DG systems in the electric power system is the ability of the DG to detect contingencies. The islanding is defined as a portion of the utility system that contains both load and distributed resources that remains energized while it is isolat­ed from the remainder utility system [1]. It may lead to power-quality issues, equipment damage, malfunction in protection devices, and even safety hazards to the personnel staff. Anti-islanding (AI) is still a major issue to DG users and utilities since the possibility of islanding occurrence increases as the DG penetration has drastically been growing over the last decade [1].

AI methods which reside in the controller of the VSI can be classified as passive and active methods. Passive methods continuously monitor the system parameters, such as fre­quency, voltage, harmonic distortion, etc. In this method, these parameters have been considerably changed when the grid is islanded [2, 3] however passive islanding detection techniques suffer from large non-detection zones (NDZs) [3].

Active methods have been designed to force DG to be un­stable when a contingency occurs. These methods enable the continuous effect of positive feedback (PF) on voltage or frequency shift and effectively destabilize the system in is­landing operation [4]. The main advantages of active methods over passive methods are their small NDZ. However, the main drawbacks of the active methods are that the injected disturbances may reduce the power quality at the PCC [5].

A higher PF gain will contribute to AI more positively in islanded conditions, whereas it will give more negative im­pacts on power quality in grid-connected conditions [4, 6].

In this paper is presented a study about the impact ofPLL algorithm in the performance of active AI method based on frequency PF. The main idea is to reduce the PF gain without degrading the performance of the AI method and consequently low injection disturbances at the PCC.

The paper is arranged as follows: Section II describes the analysis of the AI method. The design of PLL is presented in the sections III. Finally, the section IV and V presented the simulation and experimental results and the section VI con­cludes the paper.

II. ANALYSIS ANTI-ISLANDING METHODS

AI methods with PF can be implemented in two different ways for inverter-based DGs to prevent islanding, known as the voltage and frequency AI method. The frequency AI method applies a PF to the PCC voltage ' s frequency and it tries to destabilize the DG by modifying the inverter's output current in order to detect the islanding. The voltage AI meth­od uses the variation in the voltage magnitude at the PCC to obtain the output !lid [7] .

A. Frequency Positive Feedback (FPF)

The frequency positive feedback AI, proposed in [8, 9] de­tects the variations in the frequency (Wpll) to generate the output !liq which disturbs the quadrature-axis current refer­ence to the DG iq]ef [6, 7]. Fig. 1 demonstrates the Frequency PF method.

The frequency PF consists of a washout filter, a gain and a first-order filter. The critical settings include [10]:

• The frequency of the washout filter, Tw

• The PF gain, kFPF

• The low pass filter frequency, To

The transfer function of the frequency PF is represented in (1) [7, 11, 12].

sTw HFPF(s) = kFPF (1 + sTw)(1 + sTo) (1)

The combined washout and the low-pass filter constitute a band-pass filter. The selection of PF gain is a compromise between the high enough gain to ensure islanding detection quickly and the low PF gain to have minimal impact on the DG system under the grid-connected operation [7, 11 , 12] .

978-1-4799-0224-8/13/$31.00 © 2013 IEEE 7795

Page 2: [IEEE IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society - Vienna, Austria (2013.11.10-2013.11.13)] IECON 2013 - 39th Annual Conference of the IEEE Industrial

L1iq FPF· Frequency Positive Feedback

Fig. 1 : Block diagram of the Frequency PF.

III. SYNCHRONIZATION ALGORITHM

Due to the high sampling and switching frequency Ta ~ 0, the delay block can be dismissed in the PLL closed-loop transfer function and the third-order system can be reduced to canonical form of second-order as in (2), without influence on the controllability of the system [13, 14]. The block dia­gram of Fig. 2 is a simplified representation of this synchronization algorithm.

kps + k i 2(wns + wn2

Hel = S2 + kps + k i S2 + 2(wns + wn2 (2)

Thus, the gains of the PI regulator can be adjust­ed according to the equation (2), resulting in (3) and (4).

(3)

(4)

The PI parameters can be adjusted choosing the more ap­propriate values for the natural undamped frequency (wn ) and the damping ratio @ . It is observed that reducing the closed­loop frequency (wn ) , the PLL algorithm is less sensitive to noise or harmonic distortion of the input signal. Howev­er, reducing the closed-loop frequency makes the transient response of the PLL slower.

For applications using islanding detection methods that work with variables generated by the PLL algorithm (8pll ,

Wpll) it is important to have a fast dynamic response in order to detect the islanding within the standard permissible time. At the same time, is difficult to get fast dynamic response and low overshoot.

To improve the dynamic response of the PLL algorithm is used the anti-wind-up proposed in [15]. This meth­od separates the limits of the proportional and integral of the PI controller, so that the abrupt transitions, the proportional controller acting in the regulation, while the integral is lim­ited or even reset until the system converges. Fig. 3 shows the block diagram of the controller with anti-wind-up action. Where Ymax is the controller output limit and Lint is the integral output limit.

(5)

"

W" ,in -7[

Fig. 2: Synchronization algorithm PLL.

~a,

'i'

Li:1l I I + ~ 'i'

Fig. 3: Anti-wind-up.

Step Response 1.8,--..,---,-----.----;.--'---,,--,--,---,----,

-. - Without anti·wind-up 1.6

---- With anti·wind·up 1.4

1.2

~ 1 -c. ~ 0.8

0.6

0.4

0.2

0. 18

Time (s)

Fig. 4: PLL step response with anti-wind-up (blue) and without (red).

The anti-wind-up performance is observed in Fig. 4. The reduction in overshoot at 35% enables the use of closed-loop frequency higher when applied the anti-wind-up.

The relation between the integral time constant associated with the controller design of the PLL (6), the positive feed­back gain and the detection time is shown in Fig.5 .

2( r=­

Wn (6)

It is noted that for PF gains higher the influence of closed­loop frequency is minimal, moreover, for lower gains the contribution in detection time is high. The reduction of PF gain means reducing injection disturbances in the current reference control of the DO, since positive feedback is direct­ly proportional to its corresponding method gain.

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0.30 .... ............................................................................................. ............. .... ..................... 62

) V r~ 3: " E

1= c 0

'!j il C

0.25

0.20

0.15

0.10

0.05

0.00

_ KFPF= IO

_ KFPF=3

+ KFPF=0.3

, • , , , 0.075013 0.056260 0.037507 0.0261 85 0.01 8753

Integra l time constant (s)

Fig.5: Detection time for different integral time constant.

IV. SIMULATIONS RESULTS

In the frequency PF the washout filter and the low pass filter were set at 5Hz-10Hz in order to reduce the oscillation at higher frequency and characterize a suitable signal for islanding detection.

0,2s HFPF(s) = kFPF (1 + 0,2s)(1 + O,ls) (7)

In the simulation results, the DG is disconnected to the grid in 3 s. The RLC load consumes the total power produced by the DG source with resonant frequency equal to 60 Hz. The RLC load used is presented in Table I.

Table I RLC load earameters

Qt RL LL CL fr 1 2,904 (Q) 7,7 m(H) 913,4 J.L (F) 60 (Hz)

2,5 5,186 (Q) 5,5 m(H) 1,27 m (F) 60 (Hz)

With unity quality factor (Qf ), only the unity PF gain de­tected within the standards established in [1, 16]. Increasing the quality factor to 2.5, the unity PF gain detected with a higher time as expected. Fig.6 and Fig.7 show the result.

Designing the PLL algorithm with anti-wind-up and in­creasing the closed-loop frequency from 25.14 radls to 54.0 radls is reduced the AI time detection with PF gains of 1 and 0.3 . To the PF gain of 0.3 the time detection was reduced in 87% and adequate to the standard [1, 16] for loads with quali­ty factor of2.5. Fig.8 shows the result.

To demonstrate the injection of disturbances in the control system of DG, it is performed load connections with three different load types: RLC, nonlinear and motor. These types of connections are common on the grid, and serve to demon­strate the behavior of the frequency PF methods when occur load connections. To demonstrate its effectiveness, it is measures the variation of the current reference and observed the variation of iq]ef changed by the action of the AI meth­od. The nonlinear load, RLC and motor are connected in 2 s, 3 sand 4 s respectively.

Figs. 9 show the variation in the quadrature-axis current of the DG. The highest injection disturbance is with RLC load.

- kFPF=1 ------. relay k FPF = I - kFPF=O.3 I ~ - kFPF=0.03 t= 46.1m! L ~

t= 266ms \ fi

t= S9S.1m s

1\ \ 2.2 2.4 2 .6 2.8 3 3.2 3.4 3.6

Time (s)

Fig.6: Frequency at PCC with frequency PF, Qf= 1 and (f)n= 25.14 rad/s.

62 - kFPF= I If II -----relay k FPF = 1 - kFPF=0 .3 Ib II - kFPF-0.03 t=5 2.1ms ". &AI,

t=!i 92ms II

t=7 09m s

~ 1\ \ 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

Time (s)

Fig.7: Frequency at PCC with frequency PF, Qf= 2.5 and (f)n = 25.14 rad/s.

62 - kFPF=1 -----. relay k FPF = I - kFPF=0.3 - kFPF=0.03

~ =\ '--

t=26.1ms fIN ~ f'\ ~

\. t=73.1ms \ t=24S.1m s

2.9 3 3.1 3 .2 3.3 Time (s)

Fig.8: Frequency at PCC with frequency PF, Qf= 2.5 and (f)n = 54.0 rad/s.

Q ~ ..s'1,5%

~ 1%

8 0,5% til 0%

~ -0,5%

~ -1%

.§ -1,5% tl §

- kFPF= 1 - kFPF=0.3 - kFPF=0.03

IA

Y'

R ctifier

1.5 2

..... I ...

11 ".

V Motor

RLC

2.5 3 3.5 4 4.5 Time (s)

5

Fig. 9: Injection disturbances on the quadrature-axis current reference using frequency PF method.

V. EXPERIMENTAL RESULTS

The impact ofPLL algorithms in the performance of active AI methods based on frequency PF was experimen­tally tested in laboratory. The AI method, PLL and the controller was implemented in a digital signal processor TMS320F28335 from Texas Instruments. Fig. 10 shows the block diagram of the experimental setup implemented.

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Distributed Generation

( PWM )

ia ib ie

(a~qO Bpl/ Connected Mode

Vq Vd iq id Uq ~+ Vq ref

Connected ~ ~ '----------I -0-- ~_ +

0-/').+ lq ref eu rren t i "-'IJf--t---'-=---''-

Vgrid ~ Ud Vd ref Island ~ +

dqO Regu lator - + idJef

It-~=---.O...---j (dq) II-----{

"-' -

. L iq. cvPll.Leon v ld·CVPlI· eO l1 v

Island Mode

+ +

Fundamentai)-(60Hz) r~

Fig. 10: Block diagram of the experimental setup implemented.

The DG and the grid were tested under the following con­ditions:

Table II Experimental setup parameters

Parameters

Nominalline-to-line grid voltage Frequency

DC supply Voltage

Switching frequency

Transformer ratio

Inverter filter inductance (Lconv)

Inverter filter capacitance (Cf)

Capacitance resistance (Rf)

Grid filter inductance (Lgrid)

Output capacity

Value

110 (Vrms)

60 (Hz)

300 (V)

10000 (Hz)

2:1

2m (H)

lOll (F)

10 (0)

0,5m(H)

2000 (W)

For all experimental results the DG is started up in the is­landing operation mode and after synchronized and then connected to the grid. As in the simulation the load consumes the total power produced by the DG source.

For the results of the Fig.II the closed-loop frequency of the PLL controller is 25.14 radls and the PF gain is 0.5. The detection time is about 5.5 cycles as shown the transition from connected to island operation mode in Fig.II (b).

Decreasing the PF gain to 0.05 with the same closed-loop frequency (25.14 radls) becomes impracticable the islanding detection. Fig.12 (a) shows the voltage and currents at the PCC before and after grid connection and Fig.12 (b) show the transition from connected to island mode for this condition.

Increasing the closed-loop frequency of the PLL controller to 54.0 radls and using a PF gain of 0.05 the detection time is about 6.5 cycles. Fig.13 (a) shows the voltage and currents at the PCC before and after grid connection and Fig. 13 (b) shows the transition from connected to island operation mode.

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Island !MD IIW.H.OM

UID"w<JI..DM

'Ma " .. d~UIII

'MO 'w:11l.DII

Connected

I

(a)

kFPF= 0.5 Wn = 25.14 rad/s

Connected I

IJIIIOII,.,H .... _ ,o..Il 'MO\(M.IM _ '14

IMDII"rH'"

11110\(:11."

(b)

Fig.ll: Voltage and currents at the PCC before and after grid connection (a) and transition from connected to island operation mode (b) for ron = 25 .14 radls and kFPF = 0.5. Green: voltage at PCC (40Vldiv); Red: DO current (IONdiv); Blue: grid current (5Ndiv); Brown: relay (20V/div).

' 1II0'-'2U"

I"D~t .. 1110 ... 10 ....

' MO \oQe.. ....

Connected

(a)

kFPF = 0.05 Wn = 25.14 rad/s

(b) Fig.12 : Voltage and currents at the PCC before and after grid connection (a) and transition from connected to island operation mode (b) for ron = 25.14 radls and kFPF = 0.05 . Green: voltage at PCC (40V/div); Red: DO current (lONdiv); Blue: grid current (5Ndiv); Brown: relay (20V/div).

Island IIID~""

'MO ........ lMO \0:1'1 .... IMO \0:11_'"

T I

kFPF= 0.05 Wn = 54.0 rad/s

Connected

(a)

IL!!:""-<-/_'_""_-,,,,,,,,,,--,II = -­'-c:- _K,,:ftU

'MolI"r.n .. .. UIIO \t.lU . 'MO \(.1t .. .. IJIIIO IIw:H _''''

_ 10.." _ UII

Island

, .. .. 1 .. ..

(b)

Fig. 13 : Voltage and currents at the PCC before and after grid connection (a) and transition from connected to island operation mode (b) for ron = 54.0 radls and kFPF = 0.05. Green: voltage at PCC (40V/div); Red: DO current (IONdiv); Blue: grid current (5Ndiv); Brown: relay (20V/div).

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VI. CONCLUSION

This paper presented the impact of PLL algorithm in the performance of active AI method based on frequency PF. In the frequency PF method, to obtain an adequate time required for detection is necessary high positive feedback gains and consequently injection disturbances on the DG. As shown in the results, increasing the closed-loop frequency and using anti-wind-up in the PLL controller is reduced in 87% the PF gains without degrading the performance of the AI method and consequently low injection disturbances in the current reference control of the DG.

ACKNOWLEDGMENT

The authors would like to acknowledge F APESP (2011115334-6) for supporting this project.

REFERENCIAS

[1] IEEE Recommended Practice for Utility Interface of Photovoltaic (PY) Systems, IEEE Std 929-2000, 2000.

[2] H. Yahedi, R. Noroozian, A. Jalilvand and G. B. Gharehpetian, "A New Method for Islanding Detection of Inverter-Based Distributed Generation Using DC-Link Voltage Control," IEEE Transactions on Power Delivery, vol. 26, no. 2, pp. 1176-1186, April 2011.

[3] H. H. Zeineldin and 1. L. Kirtley, "A simple technique for Islanding detection with negligible nondetection wne," IEEE Transactions on Power Delivery, vol. 24, no. 2, p. 779-786, April 2009.

[4] S. K. Kim, 1. H. Jeon, H. K. Choi and J. Y. Kim, "Yoltage Shift Acceleration Control for Anti-Islanding of Distributed Generation Inverters," IEEE Transactions on Power Delivery, vol. 26, no. 4, pp. 2223-2234, October 2011.

[5] E. J. Estebanez, Y. M. Moreno, A. Pigazo, M. Liserre and A. Dell'Aquila, "Performance Evaluation of Active Islanding-Detection Algorithms in Systems: Two Inverters Case," IEEE Transactions on Industrial Electronics, vol. 58, no. 4, pp. 1185-1193, April 2011.

[6] S. K. Kim, J. H. Jeon, 1. B. Ahn, B. Lee and S. H. Kwon, "Frequency­Shift Acceleration Control for Anti-Islanding of a Distributed­Generation Inverter," IEEE Transactions on Industrial Electronics, vol. 57, no. 2, pp. 494 - 504, February 2010.

[7] P. Du, E. E. Aponte and J. K. Nelson, "Performance analysis of positive-feedback-based active anti-islanding schemes for inverter­based distributed generators," IEEE PES Transmission and Distribution Conference and Exposition, pp. 1 - 9, April 2010.

[8] Z. Ye, R. Walling, L. Garces, R. Zhou, L. Li and T. Wang, "Study and Development of Anti-Islanding Control for Grid-Connected Inverters," National Renewable Energy Laboratory - NREUSR-560-36243, Niskayuna, New York, 2004.

[9] Z. Ye, "Study and Development of Anti-Islanding Control for Synchronous Machine-Based Distributed Generators," National Renewable Energy Laboratory - NREUSR-560-38018, Niskayuna, New York, 2004.

[10] Z. Ye, "A new family of active anti-islanding schemes based on DQ implementation for grid-connected inverters," In proceeding of Power Electronics Specialists Conference, vol. 1, p. 235-241, June 2004.

[11] P. Du, Z. Ye, E. E. Aponte, K. Nelson and L. Fan, "Positive-Feedback­Based Active Anti-Islanding Schemes for Inverter-Based Distributed Generators: Basic Principle, Design Guideline and Performance Analysis," IEEE Transactions on Power Electronics, vol. 25, no. 12, pp. 2941 - 2948, December 2010.

[12] Z. Ye, M. Dame and B. Kroposki , "Grid-Connected Inverter Anti­Islanding Test Results for General Electric Inverter-Based Interconnection Technology," National Renewable Energy Laboratory-

NRELffP-560-37200, 2005.

[13] F. Biaabjerg, R. Teodorescu, M. Liserre and A. Y. Timbus, "Overview of Control and Grid Synchronization for Distributed Power Generation Systems," IEEE Transactions on Industrial Electronics, vol. 53 , no. 5, pp. 1398-1409, October 2006.

[14] M. S. Padua, M. S. Deckmann, S. G. Sperandio, F. P. Marafiio and D. Colon, "Comparative analysis of Synchronization Algorithms based on PLL, RDFT and Kalman Filter," IEEE International Symposium on Industrial Electronics, pp. 964-970, June 2007.

[15] S. Buso and P. Mattavelli, Digital Control in Power Electronics, 1 ed., Morgan & Claypool, 2006.

[16] IEEE Standard Conformance Test Procedures for Equipment Interconnecting Distributed Resources with Electric Power Systems, IEEE Std 1547.1-2005,2005.

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