IEEE ICECS 2010

SysPy: Using Python for processor-centric SoC

design

Evangelos Logaras Elias S. Manolakos

{evlog, eliasm@di.uoa.gr}

Department of Informatics and Telecommunications

University of Athens, Greece

IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2010, Athens, Greece

IEEE ICECS 2010

Processor – centric design

SoCs are largely structured with a microprocessor-centric view.

Software plays a key role in modern SoC systems hardware/software co-design.

Processors are available as Intellectual Property (IP) cores in netlist or HDL formats.

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Processor – centric design

Single chip processor

Processor as an IP core

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Why Python for SoC design? Python is a high level

programming language which supports structured and object-oriented programming.

Python combines remarkable power with very clean and simple syntax.

The language adopts dynamic typing and has a large variety of supported data types.

C/C++ functions can be imported and used.

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High – level abstraction Our objective is to create a tool which can

handle both the hardware and the software aspects of a SoCs design flow.

SysPy can be used to describe hardware components (IP cores) as well as the software assigned to run in a soft processor of the SoC.

Innovation: Python is used to describe SoC elements and glue them in a system.

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State of the art – Python based CADSystem Python

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State of the art PyCells are parameterized cells for ASIC design

(analog design) described in Python.

PyHDL uses Python just for structural descriptions, using predefined blocks.

MyHDL can be used instead of a classical HDL to describe a hardware module.

SysPy covers the features of MyHDL, and in addition supports a complete MPSoC design flow by incorporating also the use of programmable processor soft-cores.

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SysPy features

1. Python – to – VHDL conversion (Python as an HDL) - completed

2. Integration into a design of different components, expressed in Python, VHDL, netlists - completed

3. Hw/Sw co-design of SoCs using Python - progress

4. System-level simulation – in planning phase

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Fig. Design flow with SysPy.

SysPy Design flow

top-leveldesign

3rd partyVHDL

componente.g. Unisim

VHDLnetlist

componente.g. CoreLib

Pythonmodules

SysPy

gcc compiler

Processor’s core

Processor’scode

(C file)

ProcessorIP core

binaryfile

+

program memory

(initializeBRAM)

netlisttranslated

VHDL

Xilinx Synthesizer

(EDIF)

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Python – to – VHDL conversion

Baseline: convert Python component descriptions to equivalent synthesizable VHDL descriptions.

Guarantee that VHDL code is correct (syntax, signal assignment and declaration-wise etc.).

The conversion is optimized for the Xilinx XST synthesizer.

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Modular design with different components

Components that SysPy can integrate into a SoC:

Python-described components (SysPy translates them to VHDL components).

Already existing VHDL components supplied by the designer.

Components from 3rd party VHDL libraries (e.g. Xilinx Unisim).

Pre-synthesized netlist components (e.g. Xilinx CoreLib).

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Hw/Sw co-design of SoCs Embedded softcore processor modules can be connected

to custom IP components at the top level Python description of the SoC.

The softcore processor’s code should be expressed in C.

SysPy automatically calls gcc, compiles the C code and creates a VHDL component, that corresponds to a Block RAM – based memory structure, initialized with the executable code.

SysPy currently supports an AVR microcontroller open IP core.

Plans to target OpenRisc and LEON 32-bit processor IP cores are under the way.

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SoC design example We have used SysPy to design a processor-centric

SoC system that applies Sobel edge detection to grayscale images.

Sobel’s algorithm functions have been partitioned to: an AVR core, which handles all memory management

and data manipulation and, to an application application specific accelerator

described as a Finite State Machine (FSM).

A Virtex-5 FPGA device has been used for the implementation.

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SoC design example

Fig. Implementation of Sobel edge detection using SysPy.

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SoC design example

Device utilization for the Xilinx Virtex-5 LX110T FPGA device:

CLBs BRAMs DSP48

367 (6%) 48 (32%) 8 (12%)

The design can be clocked as high as > 300MHz.

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Future work Support for 32-bit softcore processors (LEON, OpenRisc).

Processors supported by the gcc tools will be preferred.

Performing system-level design exploration in Python by expressing also the processors code in Python syntax (popular with the Bioinformatics community).

Tools for Python – to – C conversion will be investigated.

Mapping complex arithmetic functions to special structural blocks (DSP algorithmic descriptions).

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Future work A simulation mechanism will be developed for co-

simulation of the Python descriptions.

Simulated code will be synthesizable without any modifications.

Test the design with more elaborate applications, e.g. image/video processing applications, bioinformatics applications etc.

Supporting ASIC design and producing VHDL code compatible with Synopsys standard-cell design tools.

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Thank you!

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Backup slides

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Why Python for system-level design?

At least three projects have already used Python for hardware design.

Most of them (PyHDL based on PAM-Blox) use Python just for structural descriptions, using component libraries.

MyHDL supports the three basic hardware description methods, e.g. behavioral, dataflow and structural. It can perform a behavioral simulation of a module.

However, MyHDL lacks the ability to embed ready-to-use components from commercial or user-defined component libraries.

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Why Python for system-level design?

Furthermore, MyHDL does not take into account the software aspects of a SoC since it does not have any provision for handling processor IP cores.

SysPy supports all three basic HDL description styles, and in addition supports predefined blocks and programmable processor softcores.

SysPy not only support incremental module-level design for synthesis but goes all the way to support hw/sw co-design and simulation of modular embedded MPSoCs.

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SysPy coding example (bridge component)

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SysPy coding example (cont.)