IN-PROCESS CONTROL OF STRUCTURAL DEFECTS IN SEMICONDUCTOR MANUFACTURING*

G. H. SchwuttkeIBM, East Fishkill LaboratoryHopewell Junction, New York

Summary

Crystallographic defects cannot be avoided in manu-facturing semiconductor devices. Even if dislocation-free starting material is used, dislocations and otherdefects can be introduced through the manufacturingprocess. The influence of such defects upon deviceproperties is reviewed. The scanning oscillator (SOT)approach to achieve the control of structural defects insemiconductor device fabrication is discussed. Criticalfabrication steps are pinpointed through SOT charts.Such charts are obtained through correlation of SOTtopographs and final yield maps. Typical examples arepresented.

Introduction

Of the many developments in modern electronics,none has been more dramatic than the rapid emergenceof microelectronics. This is best appreciated by look-ing at a few numbers. In 1955 the Bureau of Minesbegan separating the production figures of semiconduc-tor grade silicon from lesser pure forms and gave thetotal U.S. usage for the year as 35, 000 pounds. Theestimated number of silicon transistors produced thatyear was about 93, 000. In 1964, when silicon produc-tion had only increased to about 90, 000 pounds, approxi-mately 400 million silicon devices were manufactured.In 1966, the production of silicon reached 350, 000pounds and the number of silicon devices produced waswell over 1, 000 million. The projected figures till1970 look even more spectacular.

If one deals with such numbers, the importance ofadequate materials characterization and of being ableto produce materials within the tolerance limits forcertain applications is self evident. Adequate mate-rials characterization requires a good understanding ofdefects in materials. Today it is generally acceptedthat imperfections in crystalline materials are theconditio sine qua non for a better understanding of theproperties of the materials.

The impact of imperfections on the properties ofstructural materials has been shown to be very spec-tacular. Here it is recognized that optimum properties

*Work partly sponsored under Air Force Contract AF19(628)-5059, AFCRL, Bedford, Massachusetts.

often depend on the presence of high concentrations ofdislocations and various kinds of area defects. Incritical applications, many serious difficulties canarise from the complex interactions between point de-fects, dislocations, stacking faults, and other inter-faces. Unfortunately, it has rarely been possible toidentify the interaction or series of interactions that are

responsible for a particular aspect of the behavior be-cause the characterization of materials in terms ofdefects is exceedingly difficult. Therefore, a largepart of the total research effort in physical metallurgyand ceramics today is aimed at identifying the factorsthat affect phenomena such as kinetics of recrystalliza-tion, fatigue, brittle fracture, yield strength, etc.

If we turn our attention now to the so-called"icommunication" materials - those which participateactively in semiconductor devices - we face similardifficulties when we ask about the influence of defectson device properties. We know that the presence ofdefects, for example, can introduce various kinds ofenergy levels within the forbidden gap. These, in turn,can have a profound influence upon electrical proper-ties, including minority carrier lifetime. We acceptalso that, in principle, defects affect the long-timeoperating stability of a device by facilitating diffusion ofdopant materials away from the junctions or contactregions. This effect has recently become very import-ant under operating conditions of exposure to high-energy radiation.

Most semiconductor devices depend for their op-eration on the existence of well-controlled internalelectric fields which are produced by sharp gradientsof impurity concentration. They are, therefore, highlynon-equilibrium structures, in which any relaxationtowards equilibrium is potentially ruinous to the device.This tendency to relaxation can be either promoted orhindered by the presence of appropriate defect struc-tures.

It is generally believed that the impact of defectson material properties is much more complex andimportant in structural materials than in semiconductormaterials. However, it could also be argued that in thecase of semiconductor materials, the device engineerin general is not so aware of this evidence. But doesthis mean it does not exist ?

-80-

m

In this paper I shall try to answer this question insome detail. To do this, first, I shall review the influ-ence of dislocation on device performance and then Ishall expose and pinpoint critical semiconductor fabri-cation steps that may result in catastrophic devicefailure due to crystallographic defects.

Defects and Semiconductor JunctionPerformance

The original pulled crystal is never completelyperfect. Most of the time crystals contain dislocations,variations in dopant concentrations and, many times,precipitates. Today's crystal-growing,techniques areso refined that one can get dislocation-free material,An x-ray topograph of such a crystal 2 inches indiameter is shown in Fig. 1. The topograph reveals nodislocations and only slight variations in dopant concen-tration.

It is surprising that device production is not basedupon such highly perfect crystals. Empirical testsconducted some time ago indicated that dislocation-free material does not yield more transistors or diodesthan silicon with moderate dislocation densities. Thisproblem was analyzed in 1960 by a panel of experts atthe AIME meeting in Boston.1 Dislocations in semicon-ductors were found to be surprisingly harmless; theireffects seemed to be much smaller than those of pro-duction techniques, as yet uncontrolled.

In the meantime, more information has been ob-tained which throws additional light on these problems.The question why dislocation-free material did notyield more good devices than silicon of lower qualityis now easily answered: simply because the materialwas no longer free of dislocations and other defectsafter the device was made.

This raises the following questions: What isactually the influence of a dislocation on a device, andalso under what circumstances is a dislocation harmfulin a device ?

To answer these questions it is convenient to dif-ferentiate between "direct" and "indirect" effectscaused by a dislocation. Direct electrical effects of adislocation are expected if the "dangling" bond modelis correct. Shockley has pointed out that the assump-tion of "dangling" bonds at dislocations in the diamondstructure has one immediate consequence. These un-saturated bonds should act like acceptor atoms, tryingto capture an electron. The dislocations should pro-vide extra conductivity. This would be undesirable ina reverse biased p-n junction, where one wants to re-duce the reverse current to a value as low as possible.Dislocations with dangling bonds should definitely in-crease reverse currents in diodes. This has neverbeen observed. Therefore, such direct effects ofsingle dislocations - if they exist - must be very weak.

But, other direct electrical effects of high concentra-tions of dislocations are established; this includestheir influence on carrier lifetime recombination, onbreakdown phenomena and reduction in lifetime ofminority carriers. However, it is interesting to notethat it has never been possible to give an unambiguousnumerical description of this effect, since it dependsnot only on the dislocation itself, but also upon the im-purities surrounding the dislocation.

Cottrell2 has shown that edge dislocations attractforeign atoms and surround themselves with an"atmosphere" of these impurities. The attraction ofimpurities toward dislocations can be understood if oneconsiders that an oversized impurity fits much betterinto the dilatation region of the dislocation. A smallerimpurity is easier to accommodate in the compressionregion than in the undisturbed lattice. This attractionmechanism is responsible for the indirect effects whichcan lead to damage of the electrical performance ofsemiconductors. Two of these major effects are theenhancement of dopant diffusion, and the precipitationof impurities along dislocations.

It has been shown by Queisser, Hubner, andShockley3 that foreign atoms, including donors and ac-ceptors, diffuse faster along edge dislocations than inundisturbed mattrial. According to Queisser there arethree reasons for this. First, there is the attraction ofimpurities, which leads to an increase in the concen-tration of the diffusant. Secondly, there may be asimilar enhancement of vacant lattice sites around thedislocation. This would enhance any diffusion with avacancy mechanism. Finally, the activation energy forthe jump process may be lowered at the dislocationsbecause of the altered environment. These explanationshave also been offered by Queisser et al. to describethe diffusion along dislocations of small-angle grainboundaries in silicon.

The most striking example of enhanced diffusionalong dislocation was given by Queisser. Using agrain boundary, he obtained a spike-shaped diffusionfront. Isolated dislocations should, in principle, givesimilar effects, may be less pronounced than seen atthe grain boundary. The phosphorus "emitter-diffusion-brake" through the diffused p-layer, creatinga short circuit between the emitter and collector re-gions (the pipe problem), for instance, can be the re-sult of enhanced diffusion along a single dislocationline, but even slight non-uniformity in doping, a resultof localized dislocations, may create rather seriousfailures in devices. High-frequency transistors havebase layers thinner than 1 micron. It is clear thatsuch a structure is very sensitive to a non-uniformpenetrating diffusion front.

Aside from the doping non-uniformity which arisesfrom dislocations, there are the other serious conse-quences of the impurity atmospheres. Contaminants,

-81-

"r-.-

especially heavy metals, are frequently present insemiconductor devices, If these metals are in solidsolution they may be comparatively harmless. If,how-ever, metal precipitates are formed in the p-njunctions,a drastic failure results. The reverse currents ofthese junctions are raised, often to such a degree as tomake the device unusable. This phenomenon is called"softness." It has been shown by Goetzberger andShockley4 that softness can indeed be correlated withmetal precipitates. Precipitation requires nucleationcenters. Dislocations provide such centers. There-fore, softness is more probable for higher dislocationdensities in a device. This statement was proven to becorrect by Queisser. 5 He made experiments on grainboundary diodes and also on twin boundaries. Second-order twin boundaries in silicon provide favorable nu-cleation sites for precipitates; diodes with suchboundaries were found to be predominantly soft, whilediodes on good material within the same slice showedthe desirable "hard"t reverse current-voltage charac-teristic.

In-Process Control of SemiconductorManufacturing though SOT -M

This section describes a new approach used to-achieve in-process control in semiconductor manufac-turing. It is based on diagnostic x-ray charts. Suchcharts are obtained through correlation of SOT topo-graphs and final device yield maps. SOT topographs ofcrystal wafers are recorded through use of the scanningoscillator technique (SOT) of x-ray diffraction micro-scopy. 6 Such topographs represent imperfection mapsof the entire silicon wafers and can be obtained, non-destructively, after each processing step. Consequently,they reveal where and when in semiconductor manufac-turing defects are introduced which are detrimental tothe device. 7 A few representative examples are dis-cussed in the following.

1. Influence of Inhomogeneities

2. Influence of Dislocations

The influence of a single dislocation on device per-formance is shown in the next example. Dislocationsare easily introduced into silicon through improperhandling of slices before heat treatment. Dislocationsnucleated at scratches are seen in Fig. 5.

If a wafer is mechanically damaged around theperiphery, dislocations are nucleated at the chips. Thehigh density of dislocations found after repeated heatcycles is seen in Fig. 6.

Fairfield and Schwuttke9 have shown that these dis-locations significantly degrade the hardness of thediodereverse characteristics. Diodes in undamaged areasyielded 90% as reasonably hard; whereas, thosediodesin the areas of dislocations yielded about 20% as hard.A typical wafer map obtained by us is shown in Fig. 7.The true avalanche breakdown varied between 60 and110 volts and reflected the background doping of thematerial. With only a few exceptions, all diodes withdislocations in their active areas are soft.

The reverse currents of the soft diodes appear toobey a Vn type of relation (n > 2) rather than a linearrelation with specific points of discontinuity (as, forexample, a double break characteristic). Goetzbergerand Shockley4 have shown, as discussed before, thatsuch softness can be due to metallic precipitation in theactive region of the diode. The microplasma structureof many soft diodes indicates that the high leakage cur-rents occur at specific points along the dislocations;this is illustrated in Figs. 8 and 9. Thus, it appearsquite reasonable that metallic precipitates nucleate atspecific points along the dislocations and cause the ex-cessive leakage currents at sub-avalanche voltages, inthe manner discussed by Goetzberger and Shockley.

3. Diagnostic X-Ray Charts for SemiconductorManufacturing

The original pulled crystal is never completely uni-formly doped. Variations in dopant concentration maygive rise to local stresses and precipitation effects.Figure 2 represents a topograph of a silicon slice pre-pared from a cross-section cut of a boron-doped crys-tal. What we see are spiral-like modes of impurityflow. As shown by Goetzberger, 8 diodes prepared fromsuch crystals show striated light emission. This isseen in Fig. 3, which represents one of Goetzberger'sdiodes photographed in its own light. Glowing areas areclosely related to areas of low breakdown voltage.Goetzberger correlated the striations from all diodeson a single slice by mapping the directions of thestriations. Figure 4 is the picture he obtained; we seethat the striations in the diodes repeat the spiral-likepattern of impurity flow.

In the preceding section it was shown that disloca-tions are instrumental in causing semiconductor junc-tion failure. Consequences of these findings and theirimpact on the manufacturing process of modern inte-grated devices are discussed in this section. Elementalprocesses in planar device manufacturing are cuttingand shaping operations of crystals, oxidation, epitaxy,diffusion, and metallization processes. Of special im-portance are shaping procedures and high-temperatureprocesses. We have followed the production of planarintegrated devices through all manufacturing steps.Before and after each processing step, SOT topographsof the wafers were recorded; thus it was possible topinpoint the procedures and the defects that are re-sponsible for device failure. This was done by compar-ing and correlating SOT topographs obtained after the

-82-

processing step with the final yield map of the proc-essed wafer. The tesults presented here are (a) for astarting wafer of zero dislocation density and @) for astarting wafer containing approximately 4000 disloca-tions per cm2.

SOT topographs were recorded after each process-ing step; however, only the important ones are pre-sented: (a) after the initial oxidation at 11000C, (b) aftersubcollector reoxidation at 12000C and (c) after thefinal emitter diffusion step at 1000°C. Final circuityield maps of the entire wafer were computer plottedusing the emitter-base junction breakdown (punchthrough) voltage. Out of each single circuit a group of12 transistors was measured simultaneously. For thefailure of one transistor only the circuit was plotted asbad.

3.1 Dislocation-Free Wafer. According to our exper-ience, manufacturing lines identify single wafers byscribing information on their backs. The wafer of in-terest to us carries the number SG3-1. Figure 10ashows the SOT topograph of this wafer recorded afterinitial oxidation. Evidently, the wafer is of highestperfection - zero dislocation density. The scribe markSG3-1 is seen at the bottom and also at the top of thewafer. As expected, these marks act as dislocationsources. Otherwise, the wafer is still in good shape.A dramatic event is the subcollector reoxidation pro-cedure. This follows from the SOT topograph shown inFig. 10b. Large amounts of dislocations have beengenerated in the scribed areas. In addition mechanicaldamage around the periphery of the wafer, especiallyin the area of the "flat" and 'notch" has caused disloca-tion bands. This situation is aggravated through eachfollowing high-temperature cycle. The final situationis seen in the SOT topograph shown in Fig. 10c, whichwas recorded after the emitter diffusion process. Arelatively high density of dislocations propagating alongthe slip directions around the circumference of thewafer is now present. The circuit yield map superim-posed on the topograph of Fig. 10c is shown in Fig.10d. The bad devices are indicated as rectangles. Thedevices outside the stepped line along the rim of thewafer are not considered. The correlation betweenprocess-induced dislocations and circuit failure is verystriking. Practically every integrated circuit hit by adislocation band fails. This result has been substan-tiated for many wafers processed under similar andalso different conditions.

3.2 Wafer Containin Dislocation. The results ob-tained for a wafer containing about 4000/cm2 grown-indislocation (processed under identical conditions as thewafer SG3-1) are presented in the SOT topographsshown in Fig. 11. The topograph obtained after theinitial oxidation is the one in Fig. lla, and the topo-graph of Fig. hlb was recorded after the subcollectorreoxidation. The process-induced dislocations areeasily recognized in Fig. lib and the background

dislocation density is apparent from Fig. lla. Correla-tion of yield map and SOT topographs reveals practicallyno yield in the area of process-induced dislocations buthigh yield in the rest of the crystal. The results aresimilar to the ones obtained for the wafer free of grown-in dislocations. It should be noted that grown-in dis-locations - originally present in the wafer - have noapparent effect on the device yield. This is in agree-ment with the conclusions of the Boston conference andhas given rise to many misunderstandings about theinfluence of dislocations in devices.

If process-induced dislocations are understood,they can be eliminated through improvements in processtechnology. Evidence of an SOT-controlled manufac-turing process is given in the topograph of Fig. 12. Theperfection of this 2-inch wafer was maintained throughall processing steps.

Discussion

In the beginning of this paper the question wasraised, why and when are dislocations harmful to adevice ? Subsequently, available evidence on this sub-ject was reviewed,and based on the evidence the conclu-sion was reached that indirect effects of dislocationsare important and are caused through precipitation ef-fects along dislocations. Results obtained in themanufacturing lines and presented in section 3 of thispaper are consistent with previous findings. Additionalevidence to further substantiate these findings will bepresented in the following. But first several questionsmust be answered.

The first question is: Why are single grown-indislocations practically harmless in a device and whycan the presence of process-induced dislocations leadto a device catastrophe? Grown-in dislocations arenormally saturated with impurities. These impuritiesare known to form the Cottrell cloud. Consequently,these dislocations are inert against those impuritiesthat are introduced as a result of the different process-ing steps. For instance, it is well known that copperdecoration of grown-in dislocations in silicon dependson the purity of the crystal and that decoration isactually impossible in the presence of high impurityconcentrations, for instance oxygen. 10 On the otherhand, dislocations resulting from plastic deformationare easily decorated.

Process-induced dislocations have no Cottrellcloud. Consequently, they are very active in accumu-lating impurities. Precipitates form easily aroundprocess-induced dislocations. Such dislocations exerta strong internal gettering effect.

The second question that must be answered is:Why is it that not every process-induced dislocation isharmful? A detrimental dislocation must fulfill twoconditions: (a) it must contain (metal) precipitates and

-83-

(b) at least one precipitate must be close to the junctionor must be positioned in the active area of the junction.A precipitate close to the junction renders the junctionsoft. A precipitate located in the junction results inbreakdown.

The third and last question to be answered is:Where do the impurities come from? We think thatthey are mainly introduced during the high-temperaturecycles typical in device processing, specifically, oxida-tion, epitaxy, and diffusion.

Finally, we would like to present some additionalevidence supporting the model that process-induced dis-locations nucleate precipitates if trace impurities arepresent.

Figure 13 shows part of an SOT topograph of awafer after base diffusion. The device indicated atposition A contains a process-induced dislocation band.

The photomicrograph presented in Fig. 14 is ascanning electron micrograph (SEM) of the device atposition A. This picture displays clearly a string ofprecipitates decorating the dislocation band. The SEMtechnique used displays all the precipitates inside thediffused area; it does not identify the one that is detri-mental to the junction and actually causes the failure.However, it is direct evidence of precipitation alongprocess-induced dislocations.

Outlook

Although modern semiconductor technology isbased on processes through which the materials ofintegrated electronics are altered, be it in bulk orlocally, not enough is known about how these processosalter the material. To produce microelectronics, wechange the material on a microscale; and this is theparadox: We still describe these changes on a macro-scale. The yardstick used to measure these changes isthe technology applied: oxidation, epitaxy or diffusion.We overlook that although the material is changedthrough these processes, in general we have littleknowledge about what is changed.

Our next technology is large-scale integration.Presently, it seems that this technology is becomingmaterials-limited. Therefore, the question arises,what are the difficulties of concern?

As illustrated in this paper, micro-defects suchas precipitates or impurity aggregates associated withcrystallographic defects can seriously affect the prop-erties of devices.

From the standpoint of future technological growth,complete defect characterization of thin surface layersmust be the primary object of research. Therefore, itis imperative to have a better understanding of such de-fects, specifically in shallow surface layers, such asthose resulting from oxidation, epitaxy, from changesassociated with diffusion-doped surfaces, and changesresulting from thermal gradients and work damage.

Most of the extended crystallographic defects andalso gross impurity defects in crystals can be elimina-ted. Process-induced defects in crystals are now alsounderstood and can be eliminated through improvementsin process technology. However, micro-defects remainthe last and major barrier to further and final improve-ment of silicon p-n junction devices.

Acknowledgments

The author is greatly indebted to Mr. K. Brack forrecording the SOT topographs of wafers processed undermanufacturing line conditions, to Mr. S. Greer forrecording the yield maps and to Mr. K. Brandis for thescanning electron microscopy work.

References

1. W.E. Taylor, W.C. Dash, B.E. Miller, and C.W.Mueller in "Properties of Elemental and CompoundSemiconductors, "t edited by H. C. Gatos, Inter-science Publishers, New York, p. 377 (1960).

2. A.H. Cottrell in "Dislocations and Plastic Flow inCrystals," Oxford University Press, London (1953).

3. H.J. Queisser, K. Hubner, and W. Shockley, Phys.Rev. 123, 1245 (1960).

4. A. Goetzberger and W. Shockley, J. Appl. Phys.3%, 1821 (1960).

5. H.J. Queisser, J. Electrochem. Soc. 110, 52(1963).

6. G.H. Schwuttke, J. Appl. Phys. 36, 2712 (1965).7. G.H. Schwuttke, Proc. of the Symposium on Manu-

facturing In-Process Control and Measuring Tech-niques for Semiconductors, "Vol. I, p. 12-1,Phoenix, Ariz. (1966); also in Proc. of the Sym-posium on Test Methods and Measurements ofSemiconductor Devices, Budapest (1961).

8. A. Goetzberger, B. McDonald, R. Haito, and R,M.Scarlett, J. Appl. Phys. 34, 1591 (1963).

9. J.M. Fairfield and G.H. Schwuttke, J. Electro-chem. Soc. 113, 1229 (1966).

10. G.H. Schwuttke, J. Electrochem. Soc. 108, 163(1961).

At present, such defects probably are more influ-ential in determining device yield, device performance,and device reliability than the material propertiesnormally specified.

-84-

m

cb

q-l

i

4-I3

0

b~

-85-

P4S

C9o

p

0

bra

c)

AC)

04

4

4j

'e

0

Go

c)*0

0;

o0

004

Co

9.NNP-MPP-

-' \~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-

9 0\ ¢0

bfa

C)

4101,~~~~~~~~~~~~~~~~~

I M @ eo@ @ * * 9 o X X @ O @! > M~~~~9Ss9s@@@se@@@@81°v~~~~~~~~~~~~~~~~~~~~~~~~~~C

\@@@@ @ @ ¢ § e @ e Z e / s~~~~X@@@@ $ @ 0 e e Z 0 +0

g@@e@ @ e @ s s 0 Z Z g~~~~~~~~~~~~~~~~~~0~0C~bf\e @@@@ e e s @ 0 0e~~~~~~~~~~~~~~~0Stoe@@ X ¢ 0 0 0/~~~~~~~~

_ ffa, _ e,~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~c)

-86-

Fig. 5. SOT topograph of silicon wafer showing dislocations nucleated at scratches.

Fig. 6. SOT topograph of silicon wafer showing dislocations around periphery of

wafer. These dislocations result from mechanical damage and occur

after heat cycles.

-87-

uaW~t

bf

41~~~~~~~~~~~~~~~

e~~~~ 4

/*** ** \ Q

8 /* ** ** * 7 s 4 4 *140 / ~~~~~* 4 7 4 9 1:'- e**vi;@. e @* * 0

,~~~* 4 __ / er*************_Te1

0 :@ Q? w 0 *

a,,. *\70

9^.s,

A4,, e

U,.....

-88-

Fig. 8. SOT topograph showing soft diode at position A. Fig. 9. Microplasma structure of diode marked A in Fig. 8.

ff ..-

-9 0-

,0

r44

Cd

bI

g

lx

C)C)

0C.),0C)

-0a1)

ltf

CQ

rn

0

.-j

IA

0

C)

0

19C)

IL,

'e

0

c;0

0

t_

N

0

'H

C.ri4

SOT topograph of wafer shown in (a) after emitter diffusion.

Fig. 10c.

Circuit yield map of wafer shown in (a) superimposed on 10c.

Fig. 10d.

-1

1O

10

.0

-92-

0.,-I

0'0

CDU)0

c;

C)

U)

0

U-)

0

m

b1

0d0-

b*l

Cl0

C)

cl)

c)

Cl)

0

100

.-

r.I

9b'

-9 3-

CD

*_I

a)

a1)

a)4fl,¢

Poai)

00

a)

045

a)$L

v04

.,qC)

04

Co

bQ*_

a1)

z

0Cd

C.)

Co

a)

Co

p0

04

Co

004

0

.U

Co

a1)

0

Co

a)

S

a)

a)41

0

Co

C,

._d,

04

040

HCo

04Q)

b4J0

S

.,-I

C)Cd

a)

a)

0r

0

p4

a)a)

04

Illr--

Fig. 14. Scanning electron microscope picture of the device at position indicated

by arrow in Fig. 13. Note precipitates decorating dislocation bands.

-94-

Ir

I'm