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3D Stacked Packages With Bumpless Interconnect Technology

Charles W. C. Lin, Ph.D., Sam C. L. Chiang and T. K. Andrew Yang Bridge Semiconductor Corporation

3F, 157 Li-Te Road, Peitou District, Taipei, Taiwan, ROC. Email: charleslini~~bridcesemiconductor.com Tel: +886-2-2896-9568 Fax: +886-2-2896-9567

Abslract Novel 3D stacked packages fabricated with bumpless

interconnect technology are presented. The single stacking unit can contain bare chips, packaged devices or passive components. An array of compliant terminals, or a series of copper pillars along the chip periphery are used as z-axis interconnects.

To keep each single stacking unit thin, bumpless interconnect methods such as electro-chemical plating (ECP) or ball bonding are applied to connect the traces lo the die pads directly. No wire bonding, lead-bond, solder bumps, substrate or vacuum sputtering films are involved. The traces route the pad to the z-axis interconnects (e.g., copper pillar, compliant terminal) which are orthogonal to the trace for 3D stacking assembly.

Single stacking units are positioned in a vertical stack with their pillars andor terminals aligned to one another. A single reflow operation simultaneously bonds all unit assemblies together to form the 3D stacked package. The compliant and deformable nature of solder paste and the routing traces provide flexible vertical interconnections that accommodate chips and packages with a wide range of thicknesses and sizes. The traces, pillars and/or compliant terminals serve as the interconnect matrix between the chips and packages, which may be functionally similar or different from one another, thereby increasing packaging density and functionality.

Details of the design concepts, processing and the underlying bumpless interconnect technology are discussed along with key advantages and applications of these novel 3D stacked packages.

Introduction In the field of electronic systems, there is a continuous

need to increase performance or functionality, reduce size and lower costs. This is largely achieved by improved semiconductor wafer manufacturing for higher levels of integration and advanced packaging technologies.

Wafer manufacturing has continuously strived to reduce feature size of integrated circuits (IC) in order to increase circuit density and enhance functionality. This has been quite successful in the past and continuous development in this area is expected in the future.

However, controlling defect densities during wafer processing, overcoming the resolution limits of optical photolithography systems and the ensuring the ready availability of various materials and equipment present significant obstacles to further reductions in feature sizes.

Attention in the electronics industry has therefore shifted increasingly towards semiconductor packaging as one of the means to fulfill the relentless demands for enhanced system performance and functionality, smaller size and lower costs.

IC Packaging For Higher Density And Functionality Single Chip Packages. As chip speeds increase or as final

product or system dimensions become constraints, it becomes increasingly critical to position the chips as close together as possible for better signal integrity and compactness. Technologies such as wafer-level packages (WLP) and chip- scale packages (CSP) have been developed in recent years to address these issues. While these packages provide certain improvements and advantages, further size reduction and performance enhancement have been difficult to achieve consistently due to the many physical and manufacturing- related constraints.

Multi-Chip Modules (MCM). These hybrid packages that combine multiple chips on a common platform or within a package are an alternative to single chip packages. MCMs aim to achieve bigher packaging densities (i.e. lower volume and mass per chip) and better signal integrity at reasonable manufacturing costs. However, these packages are often two- dimensional structures in the x-y direction with multiple chips connected to a planar interconnection substrate.

30 Stacked Packages. In order to achieve higher packaging densities, further reduction of footprint and reduced signal transmission distances, three-dimensional (3D) packages with multiple vertically stacked chips are rapidly emerging. These packages exploit the z-direction to effectively increase packaging densities and add more functionality to the package through integration.

The major drivers of this approach include electronic systems that operate at high switching speeds (or frequencies) and/or deliver high data handling capacity within a limited space such large cache memory devices. These include compact SDRAM memory, flashiSRAM memory packages and high-performance mixed-signal radio frequency (RF) & wireless packages.

In general, 3D stacked packages fall into two distinct approaches. One approach is to package chips first and then vertically stacked these packages together using solder balls or bended leads to provide the primary vertical interconnections. 3D packages using this approach include stacked thin small outline packages (TSOP), ball grid array (BGA) and tape chip packages (TCP). The chip connections within each single chip package include wire bonding, lead bonding, tape automated bonding (TAB), and flip-chip (FC) bonding.

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232 Another approach is to stack bare chips on top of each

other first and then use wire-bonding, lead-bonding, solder bumps or thin film routing to subsequently provide the vertical interconnections to the interposer supporting and interconnecting the chip stack.

Both approaches have certain advantages and disadvantages but they lack the flexibility to accommodate the wide range of chip dimensional and thickness variations within the stacked packages. They also face numerous technical challenges including known good die testing, pad location constraints, poor horizontal routing capability, and inability to rework among others.

Furthermore, these 3D stacked packages are often manufactured by complicated processes that are difficult to develop or costly to scale up for volume production.

Novel Bumpless Inierconneei Technology Bridge Semiconductor has developed a novel bumpless

interconnect technology for Bumpless Flip Chip Packages (BFCP) that has been reported elsewhere. [ I ]

However, unlike most new packaging technologies, this technology builds on conventional and widely available printed circuit board (PCB), lead-frame, and IC package back-end assembly processes, equipment, materials, parts, and services.

We now report the extension of this technology for single- chip to novel 3D stacked packages. Key interconnect technologies and process steps that are utilized to fabricate 3D stacked packages are highlighted below.

Thin Film Re-disfribution. The formation of re- distribution fine line traces has been simplified from sputtering-plating-etching steps to plating-etching steps by the use of copper or copper-laminate panels as the starting camer material. With additive processes such as electrochemical plating or subtractive processes, the patteming of fine-line circuit traces down to 50-pm lineispace resolution can be achieved.

Figure 1 below shows the fine line Ni/Cu traces plated on the copper carrier with 50-pm minimal lineispace design rule.

Figure I : Fine line Ni/Cu traces on copper carrier

Flip Chip Attachment. Relying on the dimensional stability of the starting copper-based carrier material, excellent placement accuracy can be achieved with flip chip attachment of dies to this rigid, homogeneous substrate using conventional non-conductive die attach adhesives. Once the chip is attached lo the nickellcopper re-routing pattern on the

copper plate, the entire chip and any circuit traces that “fan out” from the chip may be protected with molding compound via encapsulation by conventional transfer molding process or dam-and-fill process.

Figure 2 below shows the proximity of the trace to the die pad that can be achieved.

Figure 2: Fine line Ni/Cu traces at close proximiry to pads

Selective Copper Removal. The selective removal of bulk (or camer) copper from the opposite side of the substrate follows flip chip attachment and encapsulation. By choosing an etching solution that differentiates copper from nickel (e.g. an ammonia system), the fine line circuitry with a nickel overcoat will remain un-etched while the bulk copper is completely removed. The re-routing circuit traces that are mechanically coupled to chip are thus exposed and precisely aligned with respect to their corresponding die pads. For packages with fan-out circuitry, the molding compound or epoxy material provides the critical mechanical support and protection during the etching process. At this stage, the re- routing circuitry has been transfened to the chip surface but is not electrically connected yet as a thin-layer of non- conducting die-attach adhesive still separates them.

Figure helow 3 shows the 50-pm copper traces precisely aligned to the pads after copper base removal.

Figure 3: Exposedfine line NiKu traces aligned to pa&

Novel First Level Interconnects. Electrochemically plated interconnect is a very low-cost yet highly reliable connection method. Instead of using solder bumps, an electrochemical plating process is used to complete the first level interconnect.

This method builds on the fact that the fine-line circuitry has been precisely placed in close proximity to the bonding pads of the die such that a conventional blind via metallization process may be used to make the plating joint.

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The first step is to create a via hole between trace and its corresponding die pad so that the latter can he accessed. This is achieved by laser drilling to selectively ablate away the cured die attach adhesive layer that separates them.

Figure 4 below shows a series of via holes opened by laser drilling to allow access to the die pad to create the

Figure 4: Vias opened to expose die pa&

Now that the material on each of the die pads is exposed, it is ready to he plated on. Using the electrochemical plating process, the conductive trace over each pad is electrically connected. When submerged in the plating solution, the trace will grow in the via and make contact with the die pad. Once the growing trace touches the die pad, it will initiate the electrochemical plating process on the latter and both trace and pad will grow at the same time. The plated material will eventually serve as the intrinsic conductive material between die pad and trace without the need for wire-bonds or solder re-flow.

With this novel approach, the connection mode for first level interconnects shifts from mechanical coupling to metallurgical coupling to ensure sufficient metallurgical bond strength. Furthermore, as the conductive traces are mechanically coupled to the chip surface without wire bonding, TAB, flip-chip bonding, polishing, or solder joints, packaged die field reliability is expected to increase and overall package height is reduced.

Figure 5 below shows a completed trace to pad interconnect by electroplating process.

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Figure 5: Trace topad interconnect

Novel Second Level Interconnects. Novel second-level interconnects of compliant terminals in a grid array format may be specially designed to form part of the thin film routing circuitry plated directly on the copper panel. To achieve this, the electroplated conductive trace is designed to include a bumped terminal that was originally a recess (or dimple) in

the copper plate. Etching or dnlling is used to form the array of recesses in the copper base. This is followed by electroplating the conductive traces onto the copper panel such that each conductive trace includes the terminal in the recess as well as the routing line that runs outside the recess to the die pad.

Each conductive trace thus becomes a single continuous low-profile metal segment from the die pad end to the package terminal end. After flip chip die attach and encapsulation, the cured die attach adhesive, mold compound, or epoxy material that intentionally fills each recess becomes part of the resin-filled hump when copper substrate is removed by etching. The elastic properties of the resin permits each humped terminal to provide a compressible compliant contact terminal thereby ensuring excellent hoard level reliability.

Figure 6 below shows a completed resin-filled compliant terminal for second-level interconnects.

Figure 6: Resin-filled compliant terminal

Memory-on-3D Packages A novel Memory-on-3D package with the bumpless

interconnect technology is described below. Single Stacking Unit Assembly. The process begins with

the fabrication of single stacking units that each contain a bare chip flipped on an array of pre-fabricated planar routing traces and a series of pillars along the chip's periphery for z- axis stacking. To keep the single stacking unit ultra-thin, bumpless methods such as electrochemical plating or ball bonding are applied to connect the traces to the die pads of the flipped chip directly. The traces route the pad to one or more pillars that all extend uniformly and orthogonally from the trace and may be pre-coated with solder paste for stacking assembly.

Figure 7 illustrates the cross-section of a single stacking unit that shows the die pads of the chip connected to the pillars at the periphery.

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Figure 7: Cross-section ofa single stacking unit

Verticol Stacking Assembly. The single stacking units that are required for the 3D stacked package are subsequently positioned in a vertical stack with their pillars aligned precisely to one another. A single solder reflow operation

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234 simultaneously bonds all unit assemblies together to form the Memory-on-3D package. Altematively, the single stacking units may be stacked and sequentially bonded together.

The compliant and deformable nature of the solder paste and the routing traces provide flexible vertical interconnections that accommodate chips with a wide range of thicknesses and sizes.

Figure 8 below illustrates the cross-section of a 4-chip Memory-on-3D package and Figure 9 that follows shows a completed ultra-thin Memory-onJD package.

Figure 8: Cross-section of a 4-chip Memory-on-3D packqge

Figure 9: Ultra-thin 4-chip Memo y-on-3D package

The flexibility of this package accommodates multiple chips of the same size and function in the same orientation or multiple chips with different functions, geometries, orientations, and die pad layouts. In addition, it also meets the ultra-thin and mixed-function requirements of many 3D stacked packages today when used in combination with thin dies of 150 pm or less.

Hybrid-on-3D Packages A novel Hybrid-onJD package with bumpless

interconnect technology is described below. Single Stacking Unit Assembly. The process begins with

the fabrication of single slacking units that resemble the processes steps for Bumpless Flip Chip Packages (BFCP). However, instead of resin, compliant terminals beyond the shadow of the die are tilled with solder paste and reflowed. For single stacking units that contain packaged devices, passives or other components for integration with bare chips, such devices are surface mounted on a copper panel with pre- formed re-routing circuitry and compliant terminals and encapsulated.

Through-Package Terminals. To facilitate interconnect in the z-direction, via boles are made by laser drilling through the molding compound or cured epoxy material to access the compliant terminals tilled with solder. These via holes are subsequently filled with solder paste to form through-package

terminals for second-level interconnects to other single stacking units or the printed circuit board.

Vertical Stacking Assembly. The single stacking units that are required for the 3D stacked package are subsequently positioned in a vertical stack with their compliant and through-package terminals aligned precisely to one another. A single reflow operation simultaneously bonds all unit assemblies together to form the Hybrid-on-3D package. Altematively, the single stacking units may be stacked and sequentially bonded together.

Figure I O illustrates the cross-section of a 2-chip Hybrid- 011-33 package with a copper heat spreader for thermal management. Figure 11 illustrates the cross-section of B 3- chip Hybrid-on-3D package that integrates bare dies, packaged devices and passive components. Figure 12 shows a completed 3-chip Hybrid-on-3D package.

*er Heat Spreader

Figure I O : Cross-section of a 2-chip Hybrid-on-3D package

Passive , Packaged device

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Figure I I : Cross-section of a 3-chip Hybrid-an-3D packoge

Figure 12: Completed 3-chip Hybrid-on-3Dpackqge

Key Considerations For Density/Functionalitj Densiry. As a 3D stacked package with bumpless

interconnect technology requires no wire-bonding, lead- bonding, solder bumps, substrate or vacuum sputtered films in its final structure, the final package density may be determined by a few key variables.

These variables include the thickness of the starting copper carrier material (which corresponds to the height of the pillars and compliant terminals) on which the unit stacking assemblies are fabricated, the thickness of the chips

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to be stacked and the thickness of the dielectric materials that isolate the traces and the chips from one another. With careful design and material choices, the final Memory-on-3D or Hybrid-on-3D package can potentially achieve ultra-thin package heights in various package formats.

Peformance. The use of flip chip technology to attach chips on planar routing traces ensures short transmission distances between the chip pads to the vertical interconnects and to each other for better signal integrity and lower noise operation. From a thermal performance point of view, the pillars and through-package terminals serve not only as providers of vertical electrical interconnects between chips but effective heat dissipation channels as well.

Functionality. The Memory-on-3D and Hybrid-on-3D packages can accommodate different single stacking units with varying chip sizes and thicknesses. Multiple combinations of devices and architectures can be designed to meet specific density or functionality requirements. This is because the series of pillars or through-package terminals at the periphery of each chip and compliant terminals between chips provide the common interconnecting matrix between various chips within the package and to the board.

Thus, the chips within the Memory-on-3D stacked package can have identical functionality, such as SDRAM or flash memory chips, or different functionality, such as flash plus SRAM or microprocessor plus memory combinations. The chips in the Hybrid-onJD packages may be stacked in various orientations (e.g. front-to-front or front-to-hack) and integrated with packaged devices, passives and other components.

The variety of options and the freedom to combine devices in various ways with fewer limitations offers application designers a wide range of die choices and flexibility to meet their data-flow and application needs. Applications for Memory-on-3D include various mobile phone memory, portable flash cards and smart cards. Applications for Hybrid-on-3D include mobile and wireless devices such as digital cameras, wireless local area network (WLAN) cards and global positioning system (GPS) units.

Manufactwing. From a manufacturing point of view, Memory-on-3D and Hybrid-on-3D packages can be manufactured using well-known processes in PCB substrate or lead-frame manufacturing and conventional hack-end package assemblers. The need for expensive new capital equipment is largely avoided while manufacturing capacity can be easily scaled up for volume production and lower cost.

During vertical stacking assembly, even if multiple chips have identical surface areas hut slight differences in thicknesses due to prior wafer processing, the malleability of the routing traces outside the periphery of the chips and the solder bonds between the pillars or terminals can provide suitably sized gaps to accommodate such thickness variations. This increases the margin for error and increases assembly yield. Chips or packaged devices from different suppliers can also he integrated without concem for procuring the chips in wafer format. It also allows standard bum-in processes (with different ones for each device) to he used before they are

stacked. For Memory-on-3D, the final package will he only slightly larger than the largest device integrated; while in Hybrid-on-3D, the final package greatly reduces the footprint of various devices on the board.

Testing And Rework. Memory-on-3D and Hybrid-on-3D packages with bumpless interconnect technology are also well suited for testing and rework. After the single stacking units have been stacked and bonded together, the package may be tested to assure that the stacking has not damaged the assemblies. If a defective single unit assembly is detected and re-workable conductive bonds (such as solder bonds) are used, the package cab be disassembled by re-applying beat, the defective unit assembly replaced with a working one and the 3D package re-assembled and re-tested. Cost savings may be achieved as only the defective unit assembly rather than the entire package is discarded.

The ability to test the chips at the end of each single stacking unit stage before stacking them eliminates the drawbacks of either hare die testing or compound yield loss from untested chips.

Package Formats. Memory-on-3D and Hybrid-on-3D packages may be designed to have a CSP, BGA or other packaging format that is required by the next level assembly. This feature provides designers with a high degree of flexibility and a wide range of package choices to achieve their specific targets of greater package density and better functionality in 3D stacked packages.

Conclusions The 3D packages with bumpless interconnect technology

presented bere represents a novel way to increase package densities and/or functionality to achieve higher levels of integration. This approach uses a flexible, robust, low-cost and simplified way to manufacture Memory-on-3D and Hybrid-on-3D packages in volume to achieve increased performance or functionality, reduced size and lower overall system cost.

References I . Lin, Charles W. C, Chiang, Sam C. L., Yang, T. K.

Andrew, “Bumpless Flip Chip Packages For Costmerformance Driven Devices,” Proc Electronic Components and Technology Conference (ECTC). New Orleans, U , May 2003.

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