ieee 2014- 2015 vlsi project titles part 1

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IEEE 2014 - 2015 VLSI PROJECT TITLES LOW-COMPLEXITY RECONFIGURABLE FAST FILTER BANK FOR MULTI- STANDARDWIRELESS RECEIVERS A SYNERGETIC USE OF BLOOM FILTERS FOR ERROR DETECTION AND CORRECTION AN ACCURACY-ADJUSTMENT FIXED-WIDTH BOOTH MULTIPLIER BASED ON MULTILEVEL CONDITIONAL PROBABILITY EVALUATION AND FPGA IMPLEMENTATION OF SPARSE LINEAR SOLVERS FOR VIDEO PROCESSING APPLICATIONS FPGA-BASED BIT ERROR RATE PERFORMANCE MEASUREMENT OF WIRELESS SYSTEMS HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS HIGH-THROUGHPUT AND LOW-COMPLEXITY BCH DECODING ARCHITECTURE FOR SOLID-STATE DRIVES

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PG Embedded Systems www.pgembeddedsystems.com #197 B, Surandai Road Pavoorchatram,Tenkasi Tirunelveli Tamil Nadu India 627 808 Tel:04633-251200 Mob:+91-98658-62045, +91-7598462045. General Information and Enquiries: [email protected]

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Page 1: IEEE 2014- 2015 VLSI PROJECT TITLES PART 1

IEEE 2014 - 2015 VLSI PROJECT TITLES

LOW-COMPLEXITY RECONFIGURABLE FAST FILTER BANK FOR MULTI-

STANDARDWIRELESS RECEIVERS

A SYNERGETIC USE OF BLOOM FILTERS FOR ERROR DETECTION AND

CORRECTION

AN ACCURACY-ADJUSTMENT FIXED-WIDTH BOOTH MULTIPLIER BASED ON

MULTILEVEL CONDITIONAL PROBABILITY

EVALUATION AND FPGA IMPLEMENTATION OF SPARSE LINEAR SOLVERS

FOR VIDEO PROCESSING APPLICATIONS

FPGA-BASED BIT ERROR RATE PERFORMANCE MEASUREMENT OF

WIRELESS SYSTEMS

HARDWARE EFFICIENT MIXED RADIX-25/16/9 FFT FOR LTE SYSTEMS

HIGH-THROUGHPUT AND LOW-COMPLEXITY BCH DECODING

ARCHITECTURE FOR SOLID-STATE DRIVES

A REAL-TIME MOTION-FEATURE-EXTRACTION VLSI EMPLOYING

DIGITAL-PIXEL-SENSOR-BASED PARALLEL ARCHITECTURE

Page 2: IEEE 2014- 2015 VLSI PROJECT TITLES PART 1

LOW-COMPLEXITY HARDWARE DESIGN FOR FAST SOLVING LSPS WITH

COORDINATED POLYNOMIAL SOLUTION

LOW-ENERGY TWO-STAGE ALGORITHM FOR HIGH EFFICACY EPILEPTIC

SEIZURE DETECTION