Capacitive coupling interference phenomena between three conductors on the surface of PCB

Dumitru (Radu) Alina Elena, Rosca (Ionita) Roxana,

Mihai Octavian Popescu Department of Measurement, Electrical Devices and Static Converters

Politehnica University of Bucharest Bucharest, Romania

office@alinadumitru.com, roxana.rosca84@gmail.com, mo_popescu@rectorat.pub.ro

Abstract— Capacitive coupling occurs in the presence of the electric field on any metal conductor. The purpose of this paper is to emphasize the capacitive coupling which appears between three conductors placed in a metallic box if the voltages difference between circuits is large. C1, C2 and C3 are three different potential conductors located on a wiring of Pertinax. With the Electrostatics model from Comsol Multiphysics it was studied capacitive coupling at the surface of a PCB in various cases.

Keywords— Coupling circuits, Crosstalk, Electromagnetic compatibility, Electromagnetic coupling, Electromagnetic propagation, Electromagnetic interference, Electromagnetic shielding, Electrostatics, Printed circuits, Interference.

I. INTRODUCTION

Capacitive coupling occurs at low frequencies (when the wavelength is large compared with the characteristic length of perturbation source) and the electromagnetic interferences are propagated mainly by conduction.

Capacitive coupling becomes large when two circuits are close together, the voltage difference of two circuits is large and signals from the external circuits are rapidly varying in time and possess large frequency content.

The study of capacitive coupling is important because the parasitic voltages that appear on the inactive conductors may cause serious problems at low frequencies.

In the real world, rarely coupling is pure conductive, capacitive or inductive it usually occurs by all ways, including by radiation.

II. CAPACITIVE COUPLING AND METHODS TO REDUCE IT Capacitive coupling occurs between conductors, circuits

located at different potentials, and among them there are ways of closing the currents produced by the potential difference.

Fig.1. Capacitive coupling a) field model, b) equivalent circuit [1]

Measures to neutralize the interference due to capacitive

coupling are shown in the figure 2. CI can be decreased by reducing parallel paths length

between conductors of both circuits, increase the distance between conductors and shielding the line two, decrease of RII by using low input resistance circuits.

Fig. 2. Reducing capacitive coupling through shielding [2]

The electric field lines produced by circuit I closes through

the shielding screen that is connected to ground [2]. In some rough EMC environments a metallic tube may be

used as a screen, and sometimes, if the EMC requirements are high, even the shielded cable may be inserted into a metallic tube.

Some technical solutions are recommended to reduce capacitive coupling. For example, in equipment that involves intense currents, the interference due to parasitic capacitance is neutralized by forming a capacitive voltage divider with

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capacitance far beyond parasitic (about two orders of magnitude).

Anti-perturbation measures should be taken only on the

perturbed system. Capacitive coupling plays important roles for receivers with high input impedance (such as: oscilloscopes and transient recorders, microphone amplifiers, etc.).

There are ways of reducing the noise induced by capacitive

coupling. Among them are: shielding of the instrument signal wires with low resistance materials or separation from the source of the noise. This is done by ensuring that power cables and instrument signal wires don’t pass through the same duct or cable tray.

A method to reduce capacitive coupling is positioning tracks as far apart as possible on a PCB [3].

Fig. 3. Separate tracks to reduce capacitance

A ground plane used to minimize mutual capacitance. If one

of the conductors are connect to ground, the values of electric potential on the conductor placed in the proximity of the grounded conductor are much smaller.

Printed circuit boards (PCBs) are by far the most common

method of assembling modern electronic circuits [4]. Comprised of a mixt of one or more insulating layers and one or more copper layers which contain the signal traces and the powers and grounds, the design of the layout of printed circuit

boards can be as demanding as the design of the electrical circuit.

When two conductors are not galvanic connected together, or totally screened from each other by a conducting (Faraday)

screen, a capacitance will be formed between them [5]. So, on any PCB, there will be a large number of capacitors associated with any circuit. Where high frequency performance matters it

is very important to consider the effects of this stray capacitance.

Most common PCB type uses 1,5mm glass-fiber epoxy material, for example Pertinax or FR4, with a relative permitivity εr=4.7. There are many sources in the tehnical literature that place the capacitance of a PCB trace over ground plane in the range of 2-3 pF/cm.

III. CAPACITIVE COUPLING INTERFERENCE PHENOMENA BETWEEN THREE CONDUCTORS ON THE SURFACE OF A PCB

Capacitive coupling occurs between conductors that are at

different potential. Therefore the potential difference occurs between the conductors an electric field is modeled in equivalent schemes by stray capacitance.

C1, C2 and C3 are three different potential conductors located on a wiring of Pertinax.

Fig. 4 Model geometry

The figure 4 presents the PCB arragment, the PCB is made by Pertinax, the C3 is the conductor that is perturbation source, the electric potential of C3, U3 is 100V, the conductors C2 and C1 have free potential. The distance between C1 and C2 is a2=3mm, and a1 distance is: 2mm, 3mm, 5mm, 10mm and 15mm . The PCB is placed in a metallic box.

IV. FEM MODELING OF ELECTROSTATIC FIELD PROBLEM The capacitive effect between the conductors is studied by

using the Finite Element Method (FEM) with the help of the software package COMSOL Multiphysics.

An electrostatic problem, defined by the Poisson equation (1), is solved for different layouts of the copper trails on the PCB.

∇ ⋅ ε0εr∇U( )= 0 (1) Where U [V] is the electrostatic potential, εr is the relative

permittivity for different elements of the computational domain (PCB, copper conductors, air), and ε0 = 10-9/(4π×9) [F/m] is the permittivity of free space. For the copper trails and air the relative permittivity is εr = 1 and for the PCB, made of Pertinax, the relative permittivity. The boundary conditions that close the domain are: Zero charge /Symmetry ( 0=⋅Dn , where ED rεε0= ).

V. NUMERICAL SIMULATION RESULTS Below are numerical simulations performed for the

distances of : 2mm, 3mm, 5mm, 10mm and 15mm.

The C3 conductors have the electric potential of 100V and the C1 and C2 conductors have free potential. The purpose of this study is to highlight the capacitive coupling that appears

when the conductors that have free potential are too close to the conductor that is active.

This situation can be seen to the electrostatic filters for air purification or to the electrostatic copy

machines

Fig. 5 Electric potential (color map) and stream lines of electric field when a1 is 2mm

Figure 5 presents the electric potential and stream lines of electric field in the case when the distance a1 is 2mm, and we can observe that the strean lines of electric field are starting from the C3 conductor and metallic box decreases the lines.

Fig. 6 Electric potential (color map) and stream lines of electric field when a1 is 3m

Fig. 7 Electric potential (color map) and stream lines of electric field when a1 is 5mm

Figure 7 present the electric potential and stream lines of electric field in the case when the distance a1 is 5mm. We can

observe that in this case the electric potential on the conductors that have free potential drops to half.

Fig. 8 Electric potential (color map) and stream lines of electric field when a1 is 10mm

We can see that in the case when the distance increases by 50%, the electric potential on the conductors that have free potential significantly decreases.

Fig. 9 Electric potential (color map) and stream lines of electric field when a1 is 15mm

In the table below we have the values of electric potential of the inactive conductors C1 and C2.

TABLE I ELECTRIC POTENTIAL ON INACTIVE CONDUCTORS

Distance a1[mm] Electric potential of C1 [V] Electric potential of C2 [V]

2 9,224 11,797

3 7,2295 7,280

5 4,4033 4,6018

10 2,6232 2,623

15 1,724 1,7242

As we can see in the table 1 and in the figure 9 if the distance between conductors is small the capacitive coupling is significant, the values of the electric potential decrees with the distance a1. The C2 conductor has values of electric potential bigger the C1 conductor because the C2 conductor is closer to

the conductor that is perturbation source, closer to C1 conductor. Increasing the distances between conductors is a method to reduce capacitive coupling.

Fig. 10 Electric potential of C1 and C2 in function of distance

IV. CONCLUSIONS

1. Capacitive coupling at the surface of a PCB is produce by the existence of electric field and can affect all the circuits when is a potential difference between conductors.

2. Capacitive coupling phenomenon can be decrees by increasing distance, avoiding overlapping circuits or certain connections to ground.

3. Can been seen that electric potential of C2, the nearest perturbation source circuit, is greater than the electric potential of conductor C1.

4. In this paper it was studied three methods of reducing capacitive coupling that are: increasing the distance between conductors that is an efficient method of reducing the parasitic potential but it cannot be applied if the size of devices is small, connection to ground of the conductor that is close to the perturbation source and placing the PCB in a metallic box.

5. These methods offer a reduction with 9% or less of a perturbation depending of the distance.

ACKNOWLEDGMENT

The work has been funded by the Sectorial Operational Program Human Resources Development 2007-2013 of the Romanian Ministry of Labor, Family and Social Protection through the Financial Agreement POSDRU/107/1.5/S/76903

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