Towards Fabrication of Low Cost High Efficiency c-Si Solar Cells:

Progress and Optimization Using TCAD Simulation Study

Karthick Murukesan1,2, Narasimha Rao Mavilla1,2 INational Centre for Photovoltaic Research and Education, lIT Bombay, Mumbai 400 076, India

2Department of Electrical Engineering, lIT Bombay, Mumbai 400 076, India Email: karthick31388@gmail.com.mnraomnrao@iitb.ac.in

Abstract-Progress of experimental and simulation work, in optimizing baseline processes for low cost, high efficiency c­Si solar cells is presented. Phosphorous diffusion at 890°C for 15 minutes was optimized to a obtain sheet resistance of 30 n/D for selective emitter region. Active area of the cell, excluding areas of front metal contact grid, was selectively etched back to obtain emitter sheet resistance of 90 n/D for lightly doped emitter. Optimization of Boron diffusion for N-type solar cells was attempted. Particularly, the material properties of boron rich layer are being explored to arrive at low cost means of removing this dead layer rather than the conventional low temperature furnace processing. An initial cell (without texturing), incorporating some of these process steps resulted in 13.1% efficiency. To understand various losses and improve the efficiency further, Sentaurus TCAD simulation study was initiated.

Index Terms-c-Si solar cells, Boron diffusion, Phosphorus diffusion, TCAD simulation

I. INTRODUCTION

Increasing energy demands and climate change are the major problems humanity is facing nowadays. Renewable energy sources are considered to be a potential solution to this problem. Solar PV is one among them and has a huge potential in comparison to other renewable sources. However, to reach grid parity, performance of solar cells has to be improved further while still implementing low cost means. The aim of our research is to study and develop low cost unit process steps for c-Si solar cell technology thereby pushing solar photovoltaics towards grid parity.

II. OPTIMIZATION OF UNIT PROCESS STEPS

Low cost high efficiency solar cells are the need of hour and are being investigated intensively to enable Solar PV reach grid-parity. In view of this, we are working on developing low cost, unit processes steps.

A. Diffusion for formation of emitter and BSF Diffusion of boron and phosphorous into silicon is a clas­

sical process for the formation of junctions for a wide variety of device applications. Diffusion is the process by which we introduce controlled amount of chemical impurities for the formation of emitters and back surface field in the solar cells. Diffusion can be done using solid, liquid or vapor sources, either as a single predeposition cycle or two step diffusion with an additional drive-in step. We have optimized solid source phosphorous and boron diffusion for the formation of emitter and back surface fields respectively in a p-type solar cell.

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'7 E u

-!II E 0 ftj '0 �

-800e,10mins 1E20 - -840C. 20min

-825C.10mins 890e.15mins

1E19 - 850C. 15 min

1E18

1E17

1E16

1E15 �������������� o 100 200 300 400 500 600 700 800 900 100011001200

Depth from the surface (nm)

Fig. 1. SIMS profile of Phosphorus diffusion for various process conditions.

This process step was carried out in a three zone atmospheric pressure quartz tube furnace at N2 ambient conditions. The controlling parameters in the case of diffusion are temperature and time. Different values of time and temperature were selected to get the range of sheet resistance values. Fig. 1 shows Secondary Ion Mass Spectroscopy (SIMS) profile of Phosphorous diffusion corresponding to various process temperatures and times done on 1-4 [l-cm, < 100> oriented CZ-Si wafers. SIMS does not give the active concentration of the dopants, on the other hand, it represents the total count of the dopant atoms present in the background Si lattice, and this also includes the inactive dopant atoms that may be present in the interstitial sites. The optimized process parameters corresponding to sheet resistance values of 30 [lID were estimated to be 890°C and 15 minutes.

Third group elements, generally AI and B are used for the formation of back surface field in the P-type solar cells. With N-type CZ-Si showing superior tolerance to the common impurities like Fe [2] and absence of life time degrading boron-oxygen complexes [3] has made it a prospective starting material for fabricating solar cells. So B diffusion is an essential process step for the formation of emitter in N type solar cell. B diffusion forms a layer of silicon boride just above the diffused region which is undesirable as it is associated with the degradation of the carrier lifetime, acts as a source of dopant during further processing [4] as well as interferes with patterning of the device since it is impervious to etchants like HF. We used a low temperature oxidation (LTO) step to convert the boride into oxide, which can be easily removed

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... - 1023 E �------��--------------; � 1 022 -----------� Atomic density of Si E B 1021 !!!. c:: 102• :8 � 10" C � 10'· c:: <3 1017 c:: o o

III

200

- B diffusion, 975C. 45 minutes -After LTO, 700C, 30 minutes

400 600 800 1000 1200 Distance from front (nm)

Fig. 2. Boron dopant profile before and after LTO process step.

in dilute HF (l0 parts of DI water + 1 part of 49% HF). Fig. 2 shows the boron dopant profile having a peak doping greater than the atomic density of Si and also crossing the solid solubility limit corresponding to the process temperature (975 0c). This implies the formation of a compound phase SiBx in the top 20 nm surface layer. This layer is instrumental in degradation of the minority carrier life time. During the LTO step the silicon boride phase has been removed which is quite evident from figure. We have made some attempts to optimize this LTO time and temperature by performing Atomic Force Microscopy (AFM) analysis and the surface roughness has been observed when the layer was not removed completely.

B. Dead layer removal

The region near the surface after the P diffusion, typically 150 nm (depends on dose), has a high concentration of dopants which are not electrically active i.e after diffusion they occupy interstitial sites rather than the substitutional sites. Since the dopants are not substitutional in position they reduce the minority carrier lifetime. This layer, so called dead layer, has to be removed by chemical means HF+HN03, dry etching or by a drive in step after predeposition step.

C. Selective emitter formation Selectively doping the emitter region below the contacts is

common for high efficiency solar cells and advantageous in reducing the series resistance and improving the performance of the solar cell. We etched back the non grid portion of the cell selectively, using PPR as a mask on the contact grid, using reactive ion etching (RIE) so that the active area of the cell has a sheet resistance of 90 njo and region below the contacts has a sheet resistance of 30 njO. This step is a self aligning [5] step so that the dead layer is getting removed along with the formation of selective emitters thereby eliminating the requirement for two separate diffusion steps for the formation of selective emitters. RIE has been optimized to have etch rate of 35- 40 nm/minute using CF 4/02 as process gases. The etch times and the corresponding changes in the sheet resistance value is shown in Fig. 3.

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� '" :J C' !!!. E .s:: .2-'" o c: J!! .. 'iii � OJ '" .s:: (/)

20L-������������-L�� 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Time in minutes

Fig. 3. R1E Etch time optimization for obtaining the desired sheet resistance.

1E20 ,

1E19

�E � 1E18

� 1E17

200

Phosphorous diffusion

400

875C, 20m ins

-Afterdrivein

950C, 20 mins, wet oxygen

600 800 1000 1200 Distance from front (nm)

Fig. 4. Drive-in in wet oxygen ambient to remove the dead layer formed during Phosphorus diffusion.

We have also optimized the drive-in technique to remove the dead layer during P diffusion. Drive-in was performed in a wet oxygen ambient so that high rates of oxidation would aid back-etching of the material (dead layer near the surface) and alter the initial profile junction depth to a small extent as it would require relatively less time compared to dry oxygen ambient. The dead layer being completely driven in is evident from Fig. 4. In the case of B diffusion, the dead layer though present, is not as thick as P diffusion case and is dominated by a thin silicon boride layer which can be removed completely by the LTO and dilute HF dip as evident from Fig. 2.

III. SOLAR CELL FABRICATION

Schematic of the device and process steps are summarized in Fig. 5. After standard RCA cleaning procedures, rear side BSF was made by solid source B diffusion at 940°C for 20 minutes. Front emitters were then formed by the solid source P diffusion to obtain a sheet resistance 30 njO. This was followed by removal of dead layer by etching. Etching was further done to define active area. For this, the heavily doped emitter regions, excluding the selective emitter region was etched back (rv 150 nm). This sheds off the more defective emitter region. The single stack SiN (70nm) used for the earlier

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Ag (200lUn)

Pd (50lUn)

(N+)-30 Olun/square

N)after back etclullg-90 Olun/square.

..... �----> P? 275 1I thick- 8E15atoms/cm3

P+ Back Snrface Field by SSBD

AI back cOlltacl(150 lUn)

Fig. 5. Device schematic and fabrication steps.

devices was replaced by a 2 stack Si02(lO run)/SiN(60 nm) and this increased the efficiency from 11.2% to 13.1 %. In addition, RIE was done 2 minutes less than previous run (3.5 min) followed by a oxidation step to cure any surface damage that might have resulted by RIE. Ti/PdlAg contact was made for front emitter contact and annealed in forming gas. One of the cells made with these process steps resulted in 13.1% as shown in Fig. 6.

IV. TCAD SIMULATION STUDY

Numerical semiconductor device simulations have been his­torically used to improve performance and reduce fabrication costs. Semiconductor device simulation, in brief, is study of behavior of a 'virtual device' (approximate real device) in a 'virtual operating conditions' (physical models) in order to predict the real device behavior. The simulations basically include numerically solving set of coupled differential equa­tions (Poisson and continuity) in drift-diffusion approximation. PCID simulation package has been extensively used for solar cell simulations due to its simplicity and zero cost. However, PCID has certain limitations like adaptation of Boltzmann statistics, which is not accurate for heavily doped regions like emitter and back surface field. Also I-D analysis is not suitable for exploring novel architectures like emitter-wrap through solar cell and nanowire solar cell. Owing to this, we use Sentaurus TCAD device simulation software package [ 1] in order to arrive at optimum solar cell parameters and improve efficiency value further.

A. Calibration of physical models TCAD semiconductor device simulations are usually carried

out using irreducible "symmetry element" to minimize the computational effort. Such symmetry element contains all the features of actual device and represents the actual device when connected in certain fashion. The symmetry element chosen for the simulation is shown in Fig. 7.

To obtain realistic predictions of performance of solar cells, an ad-hoc calibration of physical models and parameters is

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35 .. -------------------------. _ 30 N

5 25 � ..s 20 � 'iii 15 !: � 10 -!: � 5 .... :::I

• Experimental -- Simulation

Jsc= 32.5 mA/cm2

Voc= 551 mV FF = 73.5 % 11 = 13.1%

(,) 01-+------------+---1 0.0 0.1 0.2 0.3 0.4 0.5

Voltage (V) 0.6

Fig. 6. 13.1% efficiency solar cell JV characteristics (closed diamond symbols). Also shown is a TCAD simulated JV curve (solid line) after calibration of physical model.

Metal Contact

Emitter

Metal........., Contact

P-typeBase

P+ BSF

Fig. 7. Schematic of symmetric element used for simulation study. The colored graphics represent Gaussian doping.

necessary. We attempted calibration of the physical models and parameters to simulate experimentally observed I-V char­acteristics shown in Fig. 6. A rather low Vae (551 m V) is assumed to be related to contact voltage loss and similar results were also reported in [6]. This effect is modeled as a barrier of 74 mV at emitter contact. Such a barrier was observed to be necessary as any realistic parameter combination could not reproduce the observed Vae. This was also observed by PCID simulation. Various other models and parameters used in simulation are summarized in Table 1. This resulted in good match of simulation I-V with that of experimental as shown in Fig. 6.

B. Parameter variation To study the effect of parameter variation the same device

structure as shown in Fig. 7 and same model parameters as shown in Table 1 were used. However, the barrier assumed in earlier simulation was ignored. The effect of peak emitter doping variation is shown in Fig. 8. J se decreases with

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TABLE 1

SUMMARY OF PHYSICAL MODELS AND DEVICE PARAMETERS USED FOR SIMULATION.

Device parameters P-type. 274 J.Lm thick, B doped, NA = 8xlO15 cm-3 Base

BSF Selective emitter (N++) Lightly doped emitter (N+) after back-etch ARC

Gaussian, B doped, Peak N A = 1 X 1020 cm-3, Thickness = 0.9 J.Lm Gaussian, P doped, N D = 1.1 X 1020 cm-3, Thickness = 0.8 J.Lm , 30 0/0 Gaussian, ND = 4x 1019 cm-3, Thickness = 0.6 J.Lm, 90 0/0 SiNx, 70 nm thick

Front contact grid Rear contact

H grid, Finger width = 70 J.Lm, Finger spacing = 586 J.Lm 300 nm, AI

Optical simulation AM1.5G Illumination spectrum

Optical simulation Complex refractive index , Transfer Matrix Method [1] Electrical simulation

Equations numerically solved Carrier statistics

Poisson and continuity equations with drift-diffusion approximation Fermi-Dirac

Bandgap Narrowing Schenk model Intrinsic carrier concentration Temperature

ni = 9.65x 109 cm-3 300 oK

SRH bulk lifetime Auger recombination Surface recombination

Front metal I N++ Si surface Rear metal I N++ Si surface N+ Si I SiNx surface

70 J.Ls Default model [I]

So = 1 X 105 cm/s So = 1 X 105 cm/s So = 400 cm/s

increase in doping as higher doping results in higher surface recombination and lower lifetimes. Vae depends on J se and Jo according to the relations,

0.74 ....---------------.

kT (Jsc ) Vae = q In To + 1

2 ( Dn Dp ) Jo = qni LnNA + LpND

(1)

(2)

Vae increases with peak emitter doping due to decrease in reverse saturation current with increase in doping. FF depends both on Vae and J se and increases with doping as shown in Fig. 8. Efficiency increases with emitter doping till N D = 1 x 102ocm-3 due to increase in Vae and FF and decreases after this point due to decrease in J se.

0.72 0.70

u. 0.68

u. _ 0.66 � 0.64

(J

>°0.62 0.60 0.58 0.56

1017 1018 1019 1020 1021 1022 Selective emitter peak doping (cm-3)

45 42 'f

(.) 39 <

E -36 (J II) ...,

33 -�

30 � M

x

27 !='

The effect of substrate doping variation is as shown in Fig. 9. Jse decreases with increase in doping at slower rate till NA=1 x 1018 cm-3 and beyond this point, Jse decreases rapidly due to degraded minority carrier lifetime. Vae in­creases rapidly till N A = 1 X 1017 cm -3 due to decrease in reverse saturation current according to the (2). Beyond this point Vae decreases rapidly due to decrease in J se according to (1). Efficiency increases with doping till NA=8x 1016 cm-3 due to increase in both Vae and FF and beyond this point efficiency decreases due to decrease in J se due to degraded lifetime.

Fig. 8. Effect of peak selective emitter doping variation on performance of

Bulk life time is an important parameter which depends on the concentration of impurities present in the stating wafer. FZ wafers have relatively higher lifetime but are more costly. CZ wafers have lower lifetimes but are economical compared to the FZ wafers. Multi crystalline wafers are even more economical compared to either FZ or CZ wafers. The effect of bulk life time is shown in Fig. 10. Lower lifetimes result in higher recombination and degrade all the performance factors

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solar cell.

of solar cell as shown in Fig. 10. However, given that low cost starting substrates give lower lifetimes, an efficient design of the solar cell with built in fields and 3D architectures can result in reasonable efficiencies.

V. CONCLUSION

Individual unit process steps were being optimized and an attempt was made to incorporate these steps in solar cells. Phosphorous diffusion at 890 °c for 15 minutes was optimized to a obtain sheet resistance of 30 SliD for selective emitter. RIE etching time was optimized to obtain a emitter sheet resistance of 90 SliD for lightly doped emitter. This enabled us to improve fabricated cell efficiencies from 5.8%, through 11.3% to 13.1 %. TCAD simulation tool is being used to under-

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0.75 45 42

0.72 39� u. 36 .5::! u. ct � 0.69 33 E

-30 0 III 0 ..., 0 27 > 0.66 24 � � 21 M

0.63 x 18 �

15 1016 1017 1018 1019

Base doping (cm-3)

Fig. 9. Effect of base doping variation on performance of solar cell.

0.72 r;:=:=;:;:;::+�=tt�1l 46 0.70 44",-

It 0.68 42 5 40 � � 0.66 _ Voc 38 � } 0.64 � __ -I1-",,""'-11 ..., 36 _

0.62 J 34 ;;:::_0 sc_ M 0.60 .&..-....... ---"'.-----..���� ........ 132 �

0.58 L.=...o...-....L..... ......... .....L..---'-----L_"---.L-....o...-....LJ 30 o 50 100 150 200 250

Life time (Jls)

Fig. 10. Effect of base bulk life time on performance of solar cell.

stand the effect of various device parameters on the efficiency. We further plan for modifications including surface texturing, optimizing front contact and reducing surface recombination by effective passivation for improving efficiencies upto 18%.

ACKNOWLEDGMENT

We acknowledge Ministry of New and Renewable Energy (MNRE) of the Government of India for funding the National Centre for Photovoltaic Research and Education (NCPRE) at lIT Bombay, as a part of the Jawaharlal Nehru National Solar Mission. We thank Prof. B. M. Arora for guidance and Dr. A. K. Kapoor and colleagues of Solid State Physics Laboratory, Delhi for SIMS measurements.

REFERENCES

[1] Sentaurus Device User GUide, March 2010 ed. Synopsys, 2010. [2] D. Macdonald and L. J. Geerligs, "Recombination activity of interstitial

iron and other transition metal point defects in p- and n-type crystalline silicon," Applied Physics Lellers, vol. 85, no. 18, pp. 4061--4063, 2004.

[3] K. Bothe, R. Sinton, and 1. Schmidt, "Fundamental boron-oxygen-related carrier lifetime limit in mono-and multicrystalline silicon," Progress in photovoltaics: Research and Applications, vol. 13, no. 4, pp. 287-296, 2005.

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[4] M. A. Kessler, T. Ohrdes, B. Wolpensinger, R. Bock, and N. P. Harder, "Characterisation and implications of the boron rich layer resulting from open-tube liquid source BBR3 boron diffusion processes," in Photovoltaic Specialists Conference (PVSC), 2009 34th IEEE, 2009, pp. 1556-1561.

[5] D. Ruby, C. Fleddermann, M. Roy, and S. Narayanan, "Self-aligned selective-emitter plasma-etch back and passivation process for screen­printed silicon solar cells," Solar energy materials and solar cells, vol. 48, no. 1-4, pp. 255-260, 1997.

[6] M. Y. Fan and Zhiyong, "Simulation study of open circuit voltage loss at Schottky top contact in ultra-shallow junction silicon solar cells," in 2011 3rd Asia Symposium on Quality Electronic Design (ASQED). IEEE, Jul. 2011, pp. 217-220.

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