New Method To Compensate Three-Stage Amplifiers Based On Pole And Zero Cancellation Technique

Ali Jalali,Hassan Rekabi Bana,hossain elahi Faculty of Electrical and Computer Engineering

Shahid Beheshti University Tehran, Iran

a_jalali@sbu.ac.ir,rekabi_h@yahoo.com,h.elahi88@gmail.com

Abstract—in this paper, a new method to compensate three stage amplifier is proposed, second non-dominant pole cancellation of multi-path nested Miller compensation (MNMC) are paid. Using the feed forward signal and changing the location of the second zero, second non-dominant pole is removed and behavior of system is approached to the first order system. To verify the method, one practical example is presented in 0.18um CMOS technology. The simulation results confirm effectiveness of proposed method to compensate three-stage amplifier.

Keywords-component; Multipath Nested Miller Compensation; Pole and Zero Cancellation Technique ; Three Stage Amplifier

I. INTRODUCTION Today, in most analogue applications, the requirement of

high gain, wide bandwidth and low power consumption is felt strongly. With technological progress (submicron) work on lower voltages (below 1 V) has been provided. Low voltage circuit design to achieve high gain, is not possible to cascade stages, therefore, multi-stage topology in a low voltage applications is necessary. Stability in multi-stage amplifiers due to the low-frequency poles and zeros is the most important subject challenging designers, unfortunately obtaining a phase margin to ensure stability as the most important criteria often conflict the other design parameters such as speed and power consumption. For compensation of three stage amplifiers, nested miller compensation was introduced. In this method, using nested capacitance loops are determined. This method ensures good stability, but the bandwidth is restricted severely. To overcome the limitations of NMC some other compensation procedures have been reported, MNMC [2], RNMC [2], AFFC [3], DFCFC [4], NGCC[6] each of these methods to some extent have increased the bandwidth, But this advantage is obtained by increasing power consumption.

In this paper we will review MNMC method and then propose a method based on Double Pole-Zero Cancellation Compensation (DPZCC), so, the Bandwidth of the amplifier effectively improved compared to MNMC. In section IV, simulation results with H-spice software is shown and it will compare with MNMC. In the last section conclusion is intended.

II. MULTI PATH NESTED MILLER COMPENSATION The MNMC topology is shown in Fig 1. As can be seen,

one direct path to the NMC method was added until the left half plane zero is produced at low frequencies, the zero eliminates the first non-dominant pole, and so, bandwidth of amplifier increases [1].

Figure 1. Topology of multipath nested miller compensation

Open-loop transfer function of MNMC is given by

m1 mf0

m3 m1v(M NM C)

2m2 L m2

-3dB m2 m3 m2

C gA (1+s )g gA (s)=C C Cs1+ 1+s +s

P g g g⎛ ⎞ ⎛ ⎞⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠ (1)

Dc gain and dominant and non-dominant poles are given by (2) to (4) respectively.

Loommm RrrgggA 21321= (2)

( )1 2 3 1 21/do m m m o o Lp C g g r r R= − (3)

3 3 22,3

3 2

4 .( ) 1 ( )2 2 .

m m m L

L L m m

g g g CpC C g C

= − ± − (4)

Obviously, with gmf in transfer function, left half plan zero is controlled and it can be moved to low frequencies. The LHP zero is shown in equation (5). if LHP zero and first

2011 International Conference on Communication Systems and Network Technologies

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DOI 10.1109/CSNT.2011.103

479

non-dominant poles are coincident, second non-dominant pole will be eliminated.

( )3 1 1LHP m m m mfZ g g C g= (5)

After removal of zero and pole, bandwidth of amplifier is limited by the second non-dominant pole. Therefore it is important that the second non-dominant pole be transferred to higher frequencies, to ensure it, (6) is necessary.

2 2 310m m L mC g C g= (6)

The internal capacitors compensation (Cm2) in MNMC is much larger than its value in the NMC. The large compensation capacitor decreases Slew Rate and chip surface will be larger. In [1], Emitter degeneration is used to reduce transconductance of second stage. Considering α=gm2 ×CL / (gm3× Cm2) =0.1 the second and third poles are given by (7) – (8) respectively. To have phase margin more than 60 degrees, third pole should be placed twice further than the GBW.

2 3 L0.89 mP g C= − × (7)

2 3 L0.11 mP g C= − × (8)

And GBW is obtained as following:

1 m1 30.445MNMC m m LGBW g C g C= = × (9)

Comparing the bandwidth of NMC and MNMC, it can be concluded that the bandwidth has improved 78%. And using (10), internal compensation capacitor is calculated as following:

m1 1 32.25 /m L mC g C g= × (10)

Using the condition ZLHP=P2, feedforward transconductance can be calculated as below:

mf 14.45 mg g= × (11)

After cancellation of zero and pole, this amplifier will have two poles. By considering P3=2GBW, it can be expected the phase margin is about 63 degrees but due to the right zero, phase margin is reduced somewhat. Analysis was conducted based on gm3 >> gm1,gm2 condition and if this condition is not correct, zero and pole cancellation won't be properly performed.

In the next section, we introduce a way to move RHP zero from right half plan to left half plan and use it to remove second non-dominant pole.

III. DOUBLE POLE ZERO CANCELLATION COMPENSATION METHOD

A. topology Proposed method is shown in Fig 2. gmi is

transconductance of ith stage,the output resistance is roi and Coi is parasitic capacitor of each stages.

Feed forward transconductance gmf1 and gmf2 are created LHP zeros and they will eliminate non-dominant poles.

Cm1 and Cm2 are compensation capacitors and they are located between output nodes, first and third stages output nodes respectively.

Figure 2. Block diagram of proposed method

B. Transfer Function Some approximations are used to simplify the transfer

function • gm3 >> gm2,gm1 • gmi roi>>1 • CL> Cmi >>Coi

After simplification the open loop transfer function is extracted as below:

1 2 2 1 1 22 2 1

1 2 3 1 2 3 2

22 2

2 2 3

( )(1 ( ) ( ))

( )(1 )(1 )

m mf m m mf mf m m

m m m m m m mv

m L m

do m m m

C g C C g g C CA s sg g g g g g gA s C C Cs s s

p g g g

−+ + −

=+ + +

(12)

If coefficients s and s2 on the numerator and denominator are equals, open-loop zeros will be coincident upon the non-dominant poles and behavior of amplifier is approached to the single-pole.

Equation (4) exhibits non-dominant poles and if MNMC method is used to compensate, α is equal to 0.1 but in proposed method the poles are not required to become real.

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The internal compensation capacitor can be smaller and transconductance of second stage can be larger. Small transconductance of second stage is one of the disadvantages of low power amplifier that our method will also solve this problem.

With equal coefficients for numerator and denominator of transfer function, Cm1,Cm2 and gmf2 will be extracted as following:

2 11

1 2 (1 )mf mfm

m m L

g ggGBWC C C β

= = =+ (13)

22 1

1

mmf m

m

Cg gC

= (14)

2 22

3 2 3

4 . 3 .8. 3 2

m L m Lm

m m m

g C g CCg C g

= → = (15)

1 2m m

L

C CC

β += (16)

In Fig. 3 and Fig. 4 , we can suppose gmf1 equal to gm3, therefore adding one more stage and having larger power consumption is prevented.

If β<1.247, the bandwidth product of proposed method is increased in comparison with MNMC. ( (9) and (14))

Other features of this method allow designer to design amplifier with smaller gmf2, Cm2 and Cm1 while MNMC method requires larger values. MNMC method does not remove second non-dominant pole, so, the bandwidth is restricted, but in this method the zeroes are located near the poles and they are placed in the transition band, therefore, bandwidth is not restrictive.

Schematics of MNMC and DPZCC are shown in Fig 3 and Fig 4 respectively. In both topologies m1 and m2 are input transistors. gm2 is implemented by m20 and gm3 is implemented by m30. Internal feedforward stages included Mf11, and Mf12 transistors, they are connected directly to inputs.

Difference between proposed topology with previous method is External feed forward network that transistor M50 is responsible for implementation feedforward transconductance, and M40 and M41 transistors act as reverse signals. They are applied to prevent additional differential pair and save power and reduce input offset. M3 is implemented in such a way that gain of input to node A is close to the unity. But with increasing the gain from input to node A , external feedforward transconductance (gmf1) can increase virtually. In our design, we supposed that

Figure 3. Schematic of multipath nested miller compensation

Figure 4. Schematic of proposed method

VA/Vi =1.667. Compensation capacitors values and transconductance of each stage are listed in Table I.

TABLE I. DESIGN PARAMETERS

DPZCCMNMC 308 308 gm1(µA/V) 76 76 gm2(µA/V)

1000 1100 gm3(µA/V) 1670 338 gmf1(µA/V) 308 - gmf2(µA/V) 20 63 Cm1(pF) 20 69 Cm2(pF)

100 100 CL(pF)

C. Simulation results Simulation results are presented in Table II. Load

capacitor is 100pf. gain amplifiers are more than 100dB. Proposed Amplifier has suitable improvement in bandwidth and time response in comparison with pervious method. Comparing (8) with (16) and assuming β=0.4, the GBW increased as is confirmed by simulation results. Frequency response and step response are shown in Fig 5 and Fig 6 respectively. Simulation results, Phase Margin are equal to

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83 degree, which represents the behavior of single-pole system.

To compare amplifiers, two figures of merit are defined that FOML is behavior of large signal [4] and FOMS is for small signal [5]. Larger FOM indicates that amplifier has higher efficiency and the values also are listed in Table II.

IV. CONCLUSION In this paper a new method to remove non-dominant pole

in MNMC amplifier was presented. Also, without significant increase in power consumption, step response and bandwidth are increased compared to the previous methods. Simulation results show that the PM reaches about 83 degrees, and it can be concluded that two zeros and two poles of system have been removed.

TABLE II. SIMULATION RESUALTS

MNMC DPZCC(this work)Gain(dB) >100 GBW(MHz) 0.6 2.5 PM(degree) 55 83 GM(dB) 12 23 SR+/SR-(V/µs) 0.44/0.48 1.72/1.6 TS+/TS-(µs) 4.3/5.2 1.1/1.3 Power(mW) 0.45 0.45 Power Supply ±0.75 FOMS= MHz·pF/mW 133 555 FOML= V/µs ·pF/mW 100 368 Technology (HSPICE) 0.18µm

Figure 5. Frequency responses of privous and proposed methods

Figure 6. Transient responses of privous and proposed methods

REFERENCES

[1] R. G. H. Eschauzier, L. P. T. Kerklaan, and J. H. Huijsing, “A 100-MHz 100-dB Operational Amplifier with Multipath Nested Miller Compensation structure,” IEEE J. Solid-State Circuits, vol. 27, pp. 1709–1717, Dec. 1992.

[2] R. G. H. Eschauzier and J. H. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers. Boston, MA: Kluwer, 1995.

[3] H. Lee and P. K. T. Mok, “Active-feedback frequency compensation technique for low power multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 511–520, Mar. 2003.

[4] K. N. Leung, P. K. T. Mok, W.-H. Ki, and J. K. O. Sin, “Three stage large capacitive load amplifier with damping-factor control frequency compensation,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 221–230, Feb. 2000.

[5] H. T. Ng, R. M. Ziazadeh, and D. J. Allstot, “A multistage amplifier technique with embedded frequency compensation,’’ IEEE J. Solid-State Circuits, vol. 34, pp. 339---347, Mar. 1999.

[6] F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, “Multistage amplifier topologies with nested gm-C compensation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2000–2011, Dec. 1997

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