The Impact of Common Mode Currents on Signal Integrity and EMI in High-Speed Differential Data

LinksSamuel Connor

IBM Corp. Research Triangle Park, NC, USA

Bruce Archambeault IBM Corp.

Research Triangle Park, NC, USA

Mosin Mondal University of Washington

Seattle, WA, USA

Abstract— The high-speed, differential signals in today's multi-board systems often carry significant amounts of common mode current. Neglecting the common mode currents can produce unrealistic signal integrity and electromagnetic simulation results. A couple cases will be shown that illustrate the impact of common mode currents and mode conversion on the signal integrity of a link path. Effective and accurate methods for quantifying the amount of common mode current, the amount of inductance in the common mode current return path, and the impact of the common mode noise on the differential signal are proposed to ensure better design practices.

Keywords—Printed circuits, data buses, electromagnetic interference, common mode, eye diagram

I. INTRODUCTION The high-speed link paths in today’s computer systems

frequently span across multiple circuit boards. These signal paths on multiple boards are connected through connectors and cables, which often introduce impedance discontinuities. The challenges presented by multi-board signaling have been addressed in most high-speed interfaces by using differential signaling, which is less severely impacted by connector discontinuities. However, one pitfall of differential signaling is that there is a tendency to ignore the accompanying common mode signal and mode conversion effects. In the past, this was a safe assumption because the intentional differential signal was much higher in amplitude than the common mode signal and the receivers have good common mode rejection ratios (CMRR). But there has been a steady decrease in the signal voltages in most electronic systems to the point where many links now have peak-to-peak voltage swings of only 800 mV. At this level, the common mode signal amplitude is often on the same order as the intentional differential signal and cannot be neglected.

When signal integrity (SI) simulations include only the differential-to-differential parameters (SDD11 and SDD21) and ignore the mode conversion S-parameters, or when they assume that the reference plane in each circuit board is tied

perfectly to a common “ground”, or when they do not include an accurate amount of common mode current from the driver, the results fail to capture the common mode effects on the differential eye diagram. As demonstrated in this paper, these effects are real and will show up as data errors and electromagnetic interference (EMI) problems.

II. SOURCES OF COMMON MODE CURRENT The differential links in today’s computer systems are

typically not driven with true differential drivers. The two mated lines are driven complementary to each other, but there is a certain amount of imbalance that creates common mode currents on the differential pair. The receivers in most integrated circuits have good common mode rejection, which leads to a temptation to ignore the common mode currents on the link path. This is a risky practice, since the common mode currents can cause SI and EMI problems. In this section, we will describe several sources of common mode currents in multi-board link paths and ways to quantify them.

A. Skew and Rise/Fall Time Mismatch The input/output (I/O) drivers themselves generate some of

the common mode currents. Even well-matched complementary drivers will have a certain amount of mismatch in the rise and fall times due to differences in NMOS and PMOS transistor performance and will have a certain amount of skew due to mismatch in path lengths in the integrated circuit (IC) and IC package. In previous work [1], it has been shown how small amounts of driver rise/fall time mismatch, driver skew, and driver amplitude mismatch can create a common mode signal with amplitude on the same order as the intentional signal. Further skew can be introduced by the printed circuit board (PCB) due to trace length mismatch and due to inconsistency in the dielectric material which causes the two differential lines to experience slight differences in permittivity and therefore propagation velocity [2]. If the total rise/fall time mismatch and skew can be estimated from the IC and PCB designs, the amount of

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common mode signal can be calculated by adding together the time domain waveforms of the differential pair.

For cases where the design skew is not known, the common mode voltage can also be measured with an oscilloscope by measuring each leg of the differential pair individually and by adding the two measured waveforms. We performed these measurements at two places in a sample link path, at the output of the coaxial cables from a parallel bit error rate tester (parBERT) and at the inter-board connector near the driver. The common mode voltage measurement for the parBERT output is shown in Fig. 1. The measurement showed that a significant amount of common mode signal (about 160 mV) is being injected into our link path during the eye diagram measurement. The parBERT’s outputs are better matched than this, so the likely cause of this high amount of common mode signal is mismatch in the coaxial cables. For this reason, care should be taken to ensure that matched cables are used when making eye diagram and bit error rate measurements with the parBERT.

Figure 1. Common mode voltage measurement at the output of the coaxial

cables attached to the parBERT.

B. Mode Conversion Another source of common mode currents is mode

conversion in the PCB discontinuities (e.g. vias) and/or inter-board connectors. The SCD21 term indicates how much of the differential signal is converted to common mode signal when a differential pair passes through the connector. The SDC21 term indicates how much of the common mode signal is converted to differential mode signal. The SDC21 term is also a measure of the differential pair’s susceptibility to interference from other signals, radiated fields, and electrostatic discharge (ESD) events, which are all common mode sources.

The amplitudes of the mode conversion terms often seem small in comparison to the “through” terms (SCC21 and SDD21), but even 1/10 of the incident signal (-20 dB) could make the difference between a robust design and intermittent

failures if the design margins are small. Certainly, if a simulator does not account for these mode conversion terms, it potentially yields incorrect results.

III. SIGNAL INTEGRITY CASE STUDIES In this section, we describe two real-world examples where

the common mode signal has a detrimental effect on the signal integrity results.

A. Blade-Type Server System In this case of a blade-type server system with a backplane

and multiple plug-in boards, we simulated a multi-board link path with HSPICE, using an s-parameter block from a vector network analyzer (VNA) measurement, and compared the results with a direct time domain measurement of the same link path. Fig. 2 shows an eye diagram obtained from a parBERT measurement when a 800 mV peak-peak differential signal is transmitted through the device under test (DUT) at 2.125Gbps using a PRBS7 bit pattern. The DUT includes a driver test card connected to a back plane through an AirMax VS1 connector onto which a receiver test card is connected through a GbX2 connector. The total path length is approximately 18 inches in the three PCBs plus the length of the two connectors. SMA cables from the parBERT generator are connected to the driver test card SMA connectors. The SMA connectors on the receiver test card feed into a sampling scope for capturing the eye waveform. It can be seen from Fig. 2 that the eye height is approximately 440mV. Fig. 3 shows the eye diagram obtained from an HSPICE simulation of the link path, and the eye is too optimistic, with an eye height of 510 mV.

This difference of 15% is too high if designers are relying on the HSPICE simulation to determine link path performance and to make design decisions. In our investigation, we discovered that the difference in eye diagram height almost can be eliminated by including the common mode signals in the analysis. In this example, we used a measured s-parameter block, which included the mode conversion effects of the inter-board connectors, so when we added the common mode signal (the amount of common mode signal produced by the parBERT and the coaxial cables) to the drivers, we got an improved answer. The new eye diagram, shown in Fig. 4, has a 450 mV eye height that almost matches the measured value of 440 mV. The error is now 2%, significantly better than the 15% error achieved when the common mode signal was not included in the source.

1 AirMax VS is a registered trademark of FCI SA. 2 GbX is a registered trademark of Amphenol Corp.

Figure 2. Eye diagram measured with parBERT equipment.

Figure 3. Eye diagram simulated with HSPICE, using an ideal differential

source.

Figure 4. Eye diagram predicted by HSPICE simulation of the entire channel

when the drivers’ common mode signal is included in the model.

B. Serial Advanced Technology Attachment (SATA) Backplane

In this case, we investigated a hard drive backplane with a SATA data bus that experienced intermittent data bit errors.

The initial analysis with an oscilloscope and a differential probe showed that the differential signal was clean and passed an eye diagram mask test. Further analysis was performed with single-ended probes, though, and this clearly showed that a common mode glitch was occurring regularly. To confirm whether the common mode glitch was the root cause of the data bit errors, a logic analyzer was used to trigger the scope whenever it detected a bit error event. Knowledge of the test pattern was used to time correlate between the instruments, and it was determined that the common mode glitch was the cause of the bit error. Fig. 5 below shows the single-ended measurement of the differential mates along with the common mode signal (half of the sum of the differential mates).

In this case, the receiver in the SATA drive was not designed to reject a common mode pulse of that frequency and amplitude. In the end, this problem was addressed by changing receivers, but if it were identified sooner (i.e. during the design simulation work), sources of the common mode noise could have been reduced or eliminated. This illustrates how important it is for the integrated circuit (IC) designers to quantify and specify limits on common mode noise and for link path designers to evaluate the common mode performance of their channels and not just the differential mode. Some standards, such as the IEEE Draft P802.3ap/Draft 3.3 amendment to the IEEE Std 802.3TM-2005 standard covering Ethernet operation over electrical backplanes, specify common mode voltage limits (e.g. -0.4 to 1.9 V). These limits are often DC limits, however, which does not account for glitch-type common mode events.

Figure 5. Signle-ended measurement of a SATA differential pair (yellow and

green traces) along with the common mode signal (pink trace)

IV. ELECTROMAGNETIC INTERFERENCE EXAMPLE To quantify the EMI impact of common mode noise on a

differential pair, we ran some full-wave simulations of two boards connected by a right-angle connector, similar to the configuration in our blade-type server system (see Fig. 6). The voltage created between ground planes in a multi-board system is directly related to the inductance between them and the rate of change of the common mode current (which

increases with

Figure 6. CAD model of two PCBs attached with a right-angle connector.

shorter rise and fall times). The inductance between the boards is basically the loop inductance contributed by the connector, which depends on the actual current return paths [4]. Since the common mode current flowing through the signal pin returns through the ground pins, the separation of the signal pin from the ground pins and their relative positioning plays an important role in determining the loop inductance. Finding the pin configuration that minimizes inductance is very important for SI and EMI in PCBs. In a previous work, [3], we employed the Partial Element Equivalent Circuit (PEEC) method [5] and magnetic energy conservation method [6] to calculate the inductance quickly. Once the inductance (L) and the common mode current (i) are known, the voltage (V) between the boards can be calculated by

V = L ∗ di/dt. (1)

When driven by this voltage, the two ground planes can act as an efficient dipole antenna and cause electromagnetic compatibility (EMC) problems for systems. Using a Method of Moments (MoM)-based full wave solver, we analyzed the field strength at a distance of 3 meters for a couple of ground pin configurations which correspond to different inductances. As expected, the trends in Fig. 7 (calculated by a moving average of the data to smooth out resonance effects which are very dependent on the specific board geometry) show that the inter-board connection with higher inductance causes higher radiation levels. Therefore, minimizing the loop inductance of the inter-board connectors is beneficial for EMC as well as signal integrity, and this fact needs to be considered when designing the pinout of inter-board connectors.

Figure 7. Electric field strength at 3m for different ground pin configurations

in the board-to-board connector.

V. CONCLUSIONS Even in the most careful PCB designs, the differential pairs

in high-speed data buses will be carrying some amount of common mode signal due to the rise/fall time mismatch in the driver and the skew from the manufacturing tolerances and dielectric material variation. Additionally, mode conversion in the vias, connectors, and other discontinuities will tend to increase the amount of common mode current. Finally, differential pairs can pickup common mode noise from power bus cavities, ESD events, and basic crosstalk from other nets. Ignoring the common mode signal in signal integrity analysis is no longer advisable, as we showed, because the common mode amplitude is on the same order as the differential mode amplitude and through mode conversion, the common mode noise degrades the eye diagram at the receiver.

Differential receivers also have limits to the amount of common mode voltage they can tolerate. In the case of the SATA backplane, we showed that a pulse of only 140 mV was able to cause data bit errors. Link path designers need to get common mode voltage limits from the IC suppliers so they will have a design target to meet before finding failures in the lab.

Common mode currents through inter-board cables and connectors pose a big problem for EMC engineers. As the data rates have increased, the rise and fall times have decreased which increases the di/dt of the common mode signal as well. This means the inductance of the inter-board cables and connectors needs to be kept as low as possible to minimize the voltage difference between the ground planes in two PCBs. The cables and connectors will need to keep the signal-to-ground spacing as small as possible to minimize the loop area and therefore the inductance.

REFERENCES [1] B. Archambeault, S. Connor, J. Diepenbrock, “EMI Emissions from

Mismatches in High-Speed Differential Signal Traces and Cables,” in Proceedings of DesignCon 2007.

[2] J. Loyer, R. Kunze, X. Ye, “Fiber-Weave Effect: Practical Impact Analysis and Mitigation Strategies,” in Proceedings of DesignCon 2007.

[3] S. Connor, B. Mutnury, M. Mondal, P. Patel, J. Diepenbrock, M. Cases, B. Archambeault, “The Impact of Common Mode Currents and Interconnect Inductance on the Signal Quality of Differential Signals in Multi-Board PCB Systems,” Proceedings of DesignCon 2008, in press.

[4] M. Beattie and L. Pileggi, “Inductance 101: Modeling and Extraction,” in Proceedings of Design Automation Conference, pp. 323–328, 2001.

[5] A. E. Ruehli, “Equivalent Circuit Models for Three Dimensional Multiconductor Systems,” IEEE Transactions on MTT, vol. 22, pp. 216–221, Mar. 1974.

[6] B. Krauter and S. Mehrotra, “Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis,” in Proceedings of Design Automation Conference, pp. 303–308, 1998.