Development of Functional Delay Tests

Eduardas Bareiša, Vacius Jusas, Kęstutis Motiejūnas, Rimantas Šeinauskas Software Engineering Department, Kaunas University of Technology

Studentų 50-406, LT-51368 Kaunas, Lithuania, kestutis.motiejunas@ktu.lt

Abstract With ever shrinking geometries, growing density and

increasing clock rate of chips, delay testing is gaining more and more industry attention to maintain test quality for speed-related failures. The aim of this paper is to explore how functional delay tests constructed at algorithmic level detect transition faults at gate-level. Main attention was paid to investigation of the possibilities to improve the transition fault coverage using n-detection functional delay fault tests. The proposed functional delay test construction approaches allowed achieving 99% transition fault coverage which is acceptable even for manufacturing test.

1. Introduction The main objective of traditional test development

has been the achievement of high stuck-at fault coverage. The increasing design complexity and reduced error margins in semiconductor manufacturing are forcing design and test engineers to take a new look at fault models. Rapidly shrinking feature sizes raise the spectrum of new types of defects, and increasing gate counts have increased the number of locations where such defects can occur. The presence of some random defects does not affect a circuit’s operation at slow speed while it may cause circuit malfunction at rated speed. This kind of defect is called the delay defect. With ever shrinking geometries, growing density and increasing clock rate of chips, delay testing is gaining more and more industry attention to maintain test quality for speed-related failures. The purpose of a delay test is to verify that the circuit operates correctly at a desired clock speed. Although application of stuck-at fault tests can detect some delay defects, it is no longer sufficient to test the circuit for the stuck-at faults alone. Therefore, delay testing is becoming a necessity for today’s integrated circuits.

Three classical fault models are developed to represent delay defects (transition fault, gate delay fault, path delay fault) [1]. Sometimes there is used the

fourth type of delay fault model – segment delay fault, which is intermediate to the gate delay and path delay faults. All these fault models have their advantages and weaknesses. The most different models among them are transition fault model and path delay model. On one hand, transition fault patterns are considered to be more effective for large size delay defects, which can happen randomly at any site of a circuit. On the other hand, path delay test patterns aim to detect small size delay defects on a selected set of long timing paths. It is then hoped that the combination of these two orthogonal strategies can capture most of the delay defects and ensure the circuit performance.

In the case when a gate-level description of the Circuit-Under-Test (CUT) is not available functional-level test generation must be performed. A test set generated at the functional level is independent of and effective for any implementation and, therefore, can be generated at early stages of the design process [2, 3]. Another advantage of functional ATPG for delay faults over structural ATPG is related to the number of targeted faults. For structural ATPG, the number of faults is proportional to the number of paths in the circuit, which very often is exponential in circuit size. In the case of functional ATPG, the number of targeted faults is only proportional to the product of the number of inputs and the number of outputs in the circuit [3]. Functional fault models are proposed in [4-8].

The size of a functional test is usually much larger than that of an implementation-dependent one to assure good fault coverage for many implementations. When the synthesis of a high level description into a particular implementation is completed, the minimization of the functional test according to the particular implementation can be provided in order to exclude the test patterns that do not detect the faults of the particular implementation. Next, the list of undetected faults can be formed, and the deterministic methods can be used to detect the faults from this list. The adaptation of the functional test according to the particular implementation is much simpler than a generation of the test from the scratch. The process of adaptation doesn’t require the long hours and it has a

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weak impact on the overall time of the design. If the high level description is resynthesized, the functional test remains the same. It has to be only adapted to the new implementation.

The possibilities of test quality enhancement using the n-detection test set are analyzed in [9, 10]. The n-detection test set is one where each fault f is detected by n different input patterns or by the maximum number of input patterns if f has fewer than n different input patterns that detect it. The paper [9] has proposed a reordering procedure to obtain n-detection test sets and variable n-detection test sets for transition faults. The paper [10] applies n-detection test sets to check path delay faults where n is a function of the number of paths through the check points.

The aim of this paper is to analyze how the delay fault tests generated at functional-level detect gate-level transition faults and to explore the possibilities of functional delay test quality improvement using n-detection tests. We consider combinational and fully enhanced-scanned sequential circuits.

The paper is organized as follows. We review the related work in Section 2. We present the pin pair faults test transformation rules in Section 3. We explore the properties of functional delay tests and present the experimental results in Section 4. We finish with conclusions in Section 5.

2. Related work

Under functional delay fault models proposed in [4-

6], a fault is a tuple (I, O, t I, t O), where I is a CUT input, O is a CUT output, t I is a rising or falling transition at I , and t O is a rising or falling transition at O. Thus, four functional delay faults are associated with every input/output (I/O) pair and the total number of faults is 4*n*m, where n is the number of inputs of the CUT and m is the number of outputs of the CUT. A test for the functional delay fault is a pair of input patterns <u, v> that propagates a transition from a primary input to a primary output of a circuit [3]. Under the model introduced in Underwood et al. [4], only one pair of test patterns must be generated per fault. This model was expanded in Pomeranz and Reddy [6] by considering Δ different test patterns per fault. Δ is a positive integer, usually in the low hundreds, and is given as an input parameter for each CUT. Pomeranz and Reddy [5] proposed that all possible patterns are generated for each fault. This model guarantees detection of all robustly testable path delay faults in any gate-level implementation. However, the resulting test set sizes, as well as the test generation times, are very large and make this model impractical, especially for large circuits [5, 6]. However, the studies in [6] showed that it is not

necessary to generate all possible test patterns for each fault in order to guarantee that actual path delays are covered in some gate-level implementation of the function. The validity of the model in Pomeranz and Reddy [6] is verified by applying the generated test sets to various gate-level implementations [3, 6].

Another fault model for functional ATPG based on input-output stuck-at faults testing and called pin pair (PP) fault model is suggested by Bareiša et al. in [7] and generalized in [8].

Now we provide a brief presentation of the main concepts of this model. The behavioral view or the “black-box” represents the system by defining the behavior of its outputs according to the values applied on its inputs without the knowledge of its internal organization. In this case, the input-output relationship can be determined only. Let the circuit have a set of inputs X = {x1, x2, ..., xi, ... ,xn} and a set of outputs Z = {z1, z2, ... ,zj, ... ,zm}. The pin fault model considers the stuck-at-0/1 faults occurring at the module boundary, and has a weak correlation with the circuit’s physical faults. We write xi

1 and xi0 for the input stuck-

at-1/0 faults, and zj1 and zj

0 for the output stuck-at-1/0 faults. There are 2*n+2*m possible pin faults. Input-output pin stuck-at fault pairs (xi

t, zjk), t=0,1, k=0,1 are

called pin pair faults (PP). The number of possible pin pair faults of the circuit is at most 4*n*m. Note that in general it is not possible to relate the PP fault with the defects of the module unambiguously, because the PP fault doesn’t fix exactly the signal propagation path in the circuit.

3. The PIN pair fault test transformation

rules The simple rules can be derived in order to get a

functional delay fault test from PP fault test. Rule 1. If the input pattern q detects the PP fault (xi

t, zj

k), t=0,1, k=0,1, then the pair of input patterns <p, q>, where the signal value of input xi in the pattern q is 1 (0) and the signal value of input xi in the pattern p is 0 (1) detects the functional delay fault (xi, zj, r(f) xi, tr zj), tr=r,f.

Rule 2. If the input pattern q detects the PP fault (xit,

zjk), t=0,1, k=0,1, then the pair of input patterns <q, p>,

where the signal value of input xi in the pattern q is 1 (0) and the signal value of input xi in the pattern p is 0 (1) detects the functional delay fault (xi, zj, f(r) xi, tr zj), tr=r,f.

Note that the test pattern pairs built according these rules detect symmetric functional delay faults.

For example, consider the circuit represented as black-box in Figure 1. Let’s say, that circuit reaction to input pattern <10011> is <01> and that this pattern

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detects the PP faults (X21,Z11), (X21,Z20), (X31,Z11) and (X50,Z11).

Figure 1. Example circuit The transformation of the pattern <10011>

according to Rule 1 results into the sequence of input patterns pairs (<11011, 10011>,<10111, 10011>,<10010, 10011>). This sequence detects the functional delay faults (X2, Z1, f X2, f Z1), (X2, Z2, f X2, r Z1), (X3, Z1, f X3, f Z1) and (X5, Z1, r X5, f Z1). Meanwhile after transformation of this pattern according to Rule 2 we get the following sequence of input patterns pairs (<10011, 11011>,<10011, 10111>,<10011, 10010>). And the later test sequence detects the symmetric functional delay faults (X2, Z1, r X2, r Z1), (X2, Z2, r X2, f Z1), (X3, Z1, r X3, r Z1) and (X5, Z1, f X5, r Z1).

Note that every of PP tests according to Rule 1 or Rule 2 composed test pair is single-input transition test [3] and, therefore, every test pair propagates the transition from a primary input to a primary output in a function robust manner [3]. Another observation is that the test generation for PP faults can be accomplished using various approaches: 1. One test is generated for each PP fault in the circuit; 2. All possible tests are generated for each PP fault in the circuit; 3. Δ tests are generated for each PP fault in the circuit. Thus the functional delay tests obtained from PP tests generated using approaches 1, 2 or 3 correspond to tests generated using models described in [4], [5] and [6], respectively.

Now we present the additional two rules. Rule3. If the input pattern q detects the PP faults (xi

t, zj

k), …, (xgt, zd

k),…, (xht, zf

k), t=0,1, k=0,1, then the pair of input patterns <p, q>, where the signal values of inputs xi, …, xg,…, xh in the pattern q are 1 (0) and the signal values of inputs xi, …, xg,…, xh in the pattern p are 0 (1) may detect the functional delay faults (xi, zj, r(f) xi, tr zj), …, (xg, zd, r(f) xg, tr zd),…, (xh, zf, r(f) xh, tr zf), tr=r,f.

Rule4. If the input pattern q detects the PP faults (xit,

zjk), …, (xg

t, zdk),…, (xh

t, zfk), t=0,1, k=0,1, then the

pair of input patterns <q, p>, where the signal values of inputs xi, …, xg,…, xh in the pattern q are 1 (0) and the signal values of inputs xi, …, xg,…, xh in the pattern p are 0 (1) may detect the functional delay faults (xi, zj, f(r) xi, tr zj), …, (xg, zd, f(r) xg, tr zd),…, (xh, zf, f(r) xh, tr zf), tr=r,f.

By applying Rule 3 or Rule 4 every input pattern that detects PP faults is transformed only into one input pattern pair in such a way that the signal value transition occurs on every input that is associated with PP fault detection on the considered test pattern. Consequently, if the test for PP faults consists of p input patterns the constructed functional delay test has p input pattern pairs too. The test pattern pairs constructed according to Rule 3 or Rule 4 possess the change of signal value on more than one input. Therefore, the constructed pattern pairs are multi-input transition (MIT) tests [3] and some of functional delay faults that are functional robustly detectable on SIT test may become functional nonrobustly detectable [3] or even worse not detectable on considered test pattern pair, because some activation conditions needed for signal transition propagation from particular input to particular output may be corrupted.

Let’s continue the analysis of our example. The transformation of the pattern <10011> according to Rule 3 results into one pair of input patterns <11110, 10011>. This pair may detect the functional delay faults (X2, Z1, f X2, f Z1), (X2, Z2, f X2, r Z1), (X3, Z1, f X3, f Z1) and (X5, Z1, r X5, f Z1). Whereas after transformation of this pattern according to Rule 4 we get the following pair of input patterns <10011,11110>. And the later test pattern pair may detect the symmetric functional delay faults (X2, Z1, r X2, r Z1), (X2, Z2, r X2, f Z1), (X3, Z1, r X3, r Z1) and (X5, Z1, f X5, r Z1).

4. Transition fault testing using n-detection

functional delay tests The non-redundant ISCAS’85 benchmark circuits

have been selected for experiments. The functional delay tests have been derived from PP fault tests according to the rules presented in Section 3. The test sets for PP faults were generated for the black-box model of the circuit [8] using a random search procedure. The black-box models were written in the programming language C.

Now we will analyze how the functional delay fault tests constructed using various test generation modes detect transition faults at gate-level. Main attention will be paid to investigation of the possibilities to improve the transition fault coverage using n-detection functional delay fault tests. First we will explore 1-detection functional delay tests. 1-detection tests were generated using 3 different modes.

Mode 1 (M1). In this mode, the PP tests are transformed into functional delay tests according to Rule 1. The constructed test pattern pairs possess the change of signal value only on one input. Therefore,

Black-box

X1 X2 X3 X4

X5

Z1

Z2

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they are single-input transition (SIT) tests and functional robust. Note that the obtained test detects 100% of targeted faults, i.e. functional delay faults.

Mode 2 (M2). In this mode, the PP tests are transformed into functional delay tests according to Rule 3. The test pattern pairs constructed in Mode 2 possess the change of signal value on more than one input. Therefore, the constructed pattern pairs are multi-input transition (MIT) tests and some of functional delay may be not detectable on considered test pattern pair, because some activation conditions needed for signal propagation from particular input to particular output may be corrupted. Thus, the obtained test may not detect 100% of targeted faults, i.e. functional delay faults.

Mode 3 (M3). The functional delay tests are constructed in the same way as in Mode 2. There is only one difference, namely, the patterns in the test pair are counter changed, i.e. if in Mode 2 for particular PP fault test pattern the test pattern pair <u, v> was constructed then in Mode 3 the corresponding test pattern pair is <v, u> (see Rule 4). The initial PP tests used in Modes 2 and 3 are the same as in Mode 1.

The experimental results of transition fault detection by 1-detection functional delay tests are presented in Table 1. The obtained test quality for every functional test generation mode is characterized by transition fault coverage and test size expressed as the number of test pattern pairs. The best transition fault coverages for particular circuit are in bold. The last two columns of Table 1 present the numbers of transition and testable functional delay faults. The numbers of testable functional delay faults were obtained analytically in [3].

Table 1. Transition fault detection by 1-detection functional delay tests

Circuit M1 M2 M3 Transi

tion faults

Func. delay (PP) faults

Cov. (%)

Test size

Cov. (%)

Test size

Cov. (%)

Test size

C432 95.56 348 87.28 117 52.98 117 1412 540

C499 94.40 5180 91.23 1077 94.29 1077 3430 5184

C880 98.91 1001 90.90 381 83.56 381 2396 1326

C1355 97.13 5162 92.36 1011 92.09 1011 3350 5184

C1908 95.24 2359 81.58 620 69.08 620 4848 3004

C2670 96.51 1820 90.44 448 67.50 448 5646 3320

C3540 83.08 1457 88.28 515 80.47 515 8960 2588

C5315 98.41 4950 97.94 1169 89.24 1169 13816 10540

C6288 99.75 1065 98.72 268 98.70 268 14422 3068

C7552 99.21 5801 94.21 2115 98.90 2115 19160 12188

Average 95.82 2914 91.29 772 82.68 772 7744 4694

If we examine the results of experiments presented in Table 1, we can see that the 1-detection functional robust SIT tests obtained in Mode 1 cover on average more than 95% of transition faults. Modes 2 and 3 used for MIT functional delay test generation produced much worse transition fault coverages, particularly Mode 3, using which the obtained transition fault coverages are on average roughly 13% worse than in Mode 1. The on average 3.8 shorter tests don’t overweight the 13% (Mode 3) or 5% (Mode 2) loss of transition fault coverage, thus in case of 1-detection functional delay test generation for transition fault detection the SIT tests must be preferred.

Now we will analyze n-detection functional delay tests. The tests were obtained using 6 different modes.

Mode 4 (M4). Two separate test generations for PP faults were performed. The obtained tests were transformed according to Rule 1 and merged into one 2-detection functional delay test. The test pattern pairs composed in Mode 4 are single-input transition tests and functional robust.

Mode 5 (M5). One PP fault corresponds to one appropriate functional delay fault. However if the test pair <u, v> is a SIT test and detects functional delay fault (I, O, t I, t O), where t I is rising (falling) transition on input I and t O is rising (falling) transition on output O, then the test pair <v, u> detects functional delay fault (I, O, t I’, t O’), where t I’ is falling (rising) transition on input I and t O is falling (rising) transition on output O. This property is used in Mode 5, i.e. both Rule 1 and Rule 2 were used for PP test transformation into functional delay test. Thus, if we have an input pattern w that detects q PP faults for detection of corresponding functional delay faults there were built maximum 2*q pairs of input patterns. The functional delay test constructed in Mode 5 is 2-detection test. The test pattern pairs composed in Mode 5 are single-input transition tests and functional robust.

Mode 6 (M6). Two separate test generations for PP faults were performed. The obtained tests were transformed according to Rule 3 and merged into one 2-detection functional delay test. The constructed in Mode 6 test pattern pairs are multi-input transition tests.

Mode 7 (M7). The tests obtained in Modes 2 and 3 are merged into one 2-detection functional delay test. The test pattern pairs composed in Mode 7 are multi-input transition tests.

Mode 8 (M8). The tests obtained in Modes 1, 2 and 3 are merged into one 3-detection functional delay test. One part of the test pattern pairs composed in Mode 8 are functional robust single-input transition tests and another part of the test pattern pairs are multi-input transition tests.

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Mode 9 (M9). The Mode 5 was applied for two separate generated tests of PP faults. The obtained 2-detection tests were merged into one 4-detection functional delay test. The test pattern pairs composed in Mode 9 are single-input transition tests and functional robust.

The experimental results of transition fault detection by n-detection functional delay tests are presented in Tables 2 and 3. The obtained test quality for every functional test generation mode is characterized by transition fault coverage and test size expressed as the number of test pattern pairs. The best transition fault coverages for particular circuit are in bold.

Table 2. Transition fault detection by n-detection functional delay tests. Fault coverages

Circuit M4 M5 M6 M7 M8 M9

Cov. (%)

Cov. (%)

Cov. (%)

Cov. (%)

Cov. (%)

Cov. (%)

C432 98.11 97.67 88.59 93.02 98.48 99.42

C499 94.40 94.40 91.6 99.83 99.83 94.40

C880 99.17 99.21 90.9 91.78 100.00 99.29

C1355 97.13 97.13 92.6 98.69 98.99 97.13

C1908 95.61 97.48 83.13 83.48 96.74 97.85

C2670 98.35 98.65 90.75 91.73 99.56 99.11

C3540 89.03 88.71 90.01 90.77 96.85 93.79

C5315 99.55 99.58 97.96 98.09 99.95 99.86

C6288 99.88 99.95 98.72 98.72 99.94 99.99

C7552 99.52 99.66 94.57 99.11 99.62 99.74

Average 97.08 97.24 91.88 94.52 99.00 98.06

Table 3. Transition fault detection by n-detection functional delay tests. Test sizes

Circuit M4 M5 M6 M7 M8 M9

Test sizeTest sizeTest sizeTest sizeTest sizeTest size

C432 697 696 247 234 582 1394 C499 10351 10360 2136 2154 7334 20702C880 1985 2002 791 762 1763 3970 C1355 10302 10324 2059 2022 7184 20604C1908 4656 4718 1231 1240 3599 9312 C2670 3716 3640 1272 896 2716 7432 C3540 2962 2914 1098 1030 2487 5924 C5315 9905 9900 2315 2338 7288 19810C6288 2219 2130 522 536 1601 4438 C7552 11744 11602 6273 4230 10031 23488Average 5854 5829 1794 1544 4459 11707

The best average transition fault coverage (95.82%) using 1-detection functional delay tests was achieved in Mode 1. Further we will use this coverage for comparison. Modes 4 and 5 allowed improving the average transition fault coverage more than 1%. Modes 6 and 7 produced worse results than in Mode 1. Remind that the tests generated in these modes are pure MIT tests.

Let’s more thoroughly analyze Modes 4 and 5. These modes produce SIT tests; the improvement of transition fault coverage in comparison with Mode 1 is similar: 1.26% (Mode 4) and 1.42% (Mode 5). More interesting is the fact that for the tests constructed in Mode 4 two independent test generations of initial 1-detection PP fault tests were used, whereas Mode 5 requires only one initial 1-detection PP fault test. Therefore, the construction of 2-detection functional delay tests takes twice less computing time than in Mode 4, because the computing time needed for functional delay test construction can be neglected in comparison with computing time needed for initial PP fault test generation.

The experimental results with 3 and 4-detection functional delay test are presented in the last 4 columns of Tables 2 and 3. The 4-detection functional delay tests constructed in Mode 9 are SIT tests and allow achieving 98.06% average transition fault coverage. Apparently the best average transition fault coverage (99%), which is acceptable even for manufacturing test, is achieved with 3-detection functional delay tests produced in Mode 8. The sizes of tests built in Mode 8 are comparable with sizes of 2-detection tests and ~2.6 times lesser than sizes of 4-detection tests. One part of the test pattern pairs composed in Mode 8 are 1-detection SIT tests and another part of the test pattern pairs are 2-detection MIT tests and this mode requires only one initial 1-detection PP fault test. At the end of analysis of all 9 functional delay fault test generation modes we can conclude that definitely the best is Mode 8.

In general, the test generation task at algorithmic level is more complicated than at gate-level because all possible realizations of design must be taken into account. Therefore, the tests are larger compared to tests for particular realization of the circuit. For comparison, the average test size of tests produced using commercial Synopsys test pattern generator for transition faults TetraMAX is only 265 test pattern pairs by 100% transition fault coverage. And this test size is ~17 times less than average test size of tests produced in Mode 8 (see Table 4). However, the test generation at algorithmic level can be done in parallel with the circuit synthesis process and the suitable test patterns for the synthesized gate-level implementation have to be selected on the base of the fault simulation.

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This possibility allows reducing the overall time of design process because either the stage of test design is not necessary at all or the time for this stage is quite short since the augmentation of test is required only for the undetected faults.

Table 4. Test sizes of Mode 8 and TetraMAX comparison

Circuit M8 TetraMAX

Test size

Test size selected

Test size forecast Test size

C432 582 123 144 142 C499 7334 333 339 223 C880 1763 201 201 137 C1355 7184 374 408 287 C1908 3599 374 532 316 C2670 2716 342 367 259 C3540 2487 464 746 403 C5315 7288 378 385 301 C6288 1601 185 193 122 C7552 10031 668 741 461 Average 4459 344 406 265

In order to obtain tests for particular implementation we have developed a simple automated test pattern selection tool. The test pattern selection experimental results for Mode 8 are presented in third column of Table 4. The test size reduction after selection is very high (on average the selected test sizes are ~13 times less than of initial test). The obtained after selection test sizes are comparable with the sizes of tests that generated TetraMax. They are on average only 1.3 times higher. Finally, if by test augmentation in order to obtain 100% transition fault coverage we will generate for each undetected fault one test pattern pair, we obtain worst case test size forecast which is presented in the fourth column of Table 4. The forecasted worst case test sizes are on average 1.5 times higher than of TetraMAX. Thus the test generation Mode 8 allows us to develop high quality functional delay tests suitable for gate-level implementation.

At the end of this section we analyze our experiments on application of SIT and MIT tests. The authors in [11] state that SIT test sequences are more effective than MIT sequences to obtain high robust delay fault coverage. That is probably true for path delay faults however misfit for transition fault detection using functional delay tests. Let‘s analyze the transition fault coverages of circuits C499 and C1355. We see that the transition fault coverages of SIT tests coincide and are 94.4% and 97.13% respectively, i.e. even the appliance of 4-detection SIT tests doesn‘t improve the fault coverage. We made for these two

circuits additional experiments. Namely, we generated for each circuit 10-detection SIT tests, which test sizes were above 70000 test pattern pairs, but and employment of 10-detection SIT tests didn‘t improve the transition fault coverages. However, the pure MIT tests constructed in Mode 7 let us to achieve better transition fault coverages 99.83% and 98.69% for circuits C499 and C1355 respectively. There is only one explanation of this fact, namely, that some circuits contain transition faults, which are hard-to-detect or not detectable with SIT tests constructed at algorithmic level. Another argument for application of MIT test is that definitely the best functional test generation Mode 8 produces the test set where one part of the test pattern pairs are 1-detection SIT tests and another part of the test pattern pairs are 2- detection MIT tests. Thus the MIT tests complement SIT tests or vice versa.

5. Conclusions

In this paper we have explored the properties of n-

detection functional delay fault tests. The functional delay fault tests were built using 9 different test generation modes and we have analyzed how tests generated at algorithmic level are suitable for detection of gate-level transition faults.

Our experimental results show that the test sets, which are generated according to the functional delay fault model, obtain high fault coverages of transition faults. The 1-detection SIT tests cover up to 95.8% of transition faults, whereas 1-detection MIT test exposed up to 13% worse coverage. Therefore, in case of 1-detection functional delay test generation for transition fault detection the SIT tests must be preferred. On other hand mixed SIT and MIT tests exposed the best results in case of n-detection functional delay test generation. The experiments with 2, 3 and 4-detection functional delay test generation modes demonstrated that definitely the best of all 9 considered modes is 3-detection functional delay test generation mode, using which the test is composed of 1-detection SIT test and of 2-detection MIT test. The achieved in this mode transition fault coverage of 99% is acceptable even for manufacturing test.

Some authors state that SIT test sequences are more effective than MIT sequences to obtain high robust delay fault coverage. That is probably true for path delay faults, however our experiment show that this statement misfits for transition fault detection using functional delay tests. There is only one explanation of this fact, namely, that some circuits contain transition faults, which are hard-to-detect or not detectable with SIT tests constructed at algorithmic level. Another argument for application of MIT test is that definitely the best considered functional test generation mode

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produces the test set where one part of the test pattern pairs are MIT tests. Therefore, it is necessarily to complement SIT tests with the MIT tests or vice versa. References

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