Gain and Cut-off Frequency Analysis of Multiple-Gated AlGaAs/InGaAs HEMTs

Mohd Nizam Osman1, Zaiki Awang2, Syamsuri Yaakob1, Mohamed Razman Yahya1 and Abdul Fatah Awang Mat1

1Microelectronic and Nano Technology Programme, TM Research & Development Sdn. Bhd.,

Idea Tower, Lebuh Silikon, 43400 Serdang, Malaysia. 2Faculty of Electrical Engineering, University Technology MARA (UiTM),

40000 Shah Alam, Malaysia. mohdnizam@tmrnd.com.my, zaiki437@salam.uitm.edu.m, syamsuri@tmrnd.com.my, razman@tmrnd.com.my, drfatah@tmrnd.com.my

Abstract – A small signal analysis was performed on a specific 0.2 μm HEMT device to study the impact of multiple-gated layout towards the gain and cut-off frequency performance. The characterization process was using on-wafer measurement technique to AlGaAs/InGaAs HEMT devices which consisted of three types of layouts of various gate finger numbers and widths. The devices were biased at the optimum basing voltage obtained from DC characterization performed previously. From the result, it was observed that the device with higher number of gates exhibited higher gain only at low frequency, while at higher frequency the gain dropped significantly. This significant drop in gain was due to the increase of the gate-source capacitance in the device, thus leading to a reduction of the device cut-off frequency. The experimental findings were strongly supported by simulation which was based on related theory on the layout dimension contribution. Keywords: HEMT Device, Multiple-gated layout, Gain, Cut-off Frequency.

1. Introduction For the past ten years, the HEMT device was

among the most effective candidate for higher frequency and low noise performance in advance analogue telecommunication applications. A lot of developments were done to continuously improve the performance of III-V material-based HEMT device including the effort to create a gate length as small as possible in order to achieve higher and higher operating frequency [1, 2]. However, the development of smaller gate lengths was not favored by fabrication process due to equipment limitation and stability. Besides, an improvement offered through structure layer design was also promising [3, 4]. Unlike other options, there is another approach where the design of device layout is applied during the fabrication process. Basically, the purpose is to improve the electrical performance of the device in terms of DC and RF

characteristics. Lately we have seen researches that focused on multiple-gate fingers for RF improvement of MOSFET, CMOS, FET and MESFET devices [5 - 8]. Some of them obtained a promising result for their devices. However, for the AlGaAs/InGaAs HEMT, as far as we are aware, there is not much literature which reported the impact of multiple-gate designs on RF performance. In fact, how much this layout contributes to the improvement is still unclear. This paper will attempt to illustrate the impact of multiple-gate layout on the RF characteristic of a HEMT device within a specific frequency range. The result will be useful for MMIC system designers that require specific RF criteria in their application.

2. Theory and Analysis

In principle, the physical geometry of a device will affect some of the RF criteria especially the network and noise performance. The most desired parameter for the transistor is the gain, which is given by S21 parameter in a network measurement. Normally, the gain of a device indicates how much amplification will be performed to the original signal, which is subsequently delivered to the output. The small signal gain depends on the transconductance gm at DC which is given by the expression:

gs

dsm V

Ig∂∂

= (2.1)

Based on this expression, the value of gm depends on how big the rate of change of output current is. As we have observed in [9], devices with higher gate finger numbers produced higher Ids and this led to an improvement of gm. This option may improve the small signal gain, but one should bear in mind that in the modulation efficiency theory [10], the increase of device size would significantly increase the capacitance due to the 2-DEG charge density, bound carrier density and free electron density at the gate area. The rate of change of this charge density over the

1-4244-1435-0/07/$25.00©2007 IEEE

gate voltage will create capacitance, Ctot, as given by expression 2.2:

)()( deg2

g

freeboundtot V

C∂

++∂=

ηηη (2.2)

The increase of the device size in multiple-gated layouts will create bigger Ctot and thus impacts the gate-source capacitance, Cgs at any gate length, Lg as given by expression 2.3:

(2.3) gtotgs LCC = For any given gm and Cgs, the cut-off frequency, fT of the device could be estimated from the relationship:

( )gdgs

mT CC

gf+

=π2

(2.4)

Based on 2.4, we should expect that multiple-gated devices will have lower fT’s if the Cgs and Cgd are more dominant compared to the gm. Nevertheless, this assumption will be only observed from measurements of real fabricated HEMT device.

3. Experimental Approach The study of the impact of multiple-gated layout

on rf performance was focused on the 0.2 µm AlGaAs/InGaAs HEMT device for the gain (G) and cut-off frequency (fT) parameters since these two parameters are key performance indicators for high frequency devices beside noise. The three layouts investigated in this study are 2 × 60 µm, 4 × 75 µm and 6 × 150 µm which are two-, four- and six-gate fingers at 60 µm, 75 µm and 150 µm device widths respectively. To observe the preliminary effects on gain and cut-off frequency, the device was simulated on ADS for each HEMT layout. The results were then plotted for comparison purpose. The device was fabricated using specific foundry process and then characterized using GSG air-coplanar RF probes. Small signal measurements were carried out on each device, the SOLT calibration process was implemented to minimize measurement uncertainty. The device was biased at specific DC biasing for optimum performance obtained from our study reported previously [9]. The RF signal was swept from 100 MHz to 40 GHz at –10 dBm with 201 measurement points. All measurements were carried out in a shielded box for noise reduction to minimize environment uncertainty. The data was stored and plotted for comparison analysis. The extrapolation on the current gain, |h21| was done for cut-off frequency parameter extraction. The results of the analysis were plotted accordingly. The block diagram of the

measurement setup performed in this study is shown in Figure 1:

Figure 1: Block diagram of the measurement setup

4. Results and Discussion

Using data from the previous experiment, the measured gm for all HEMT layouts are shown in Figure 2.

0.00E+00

1.00E-01

2.00E-01

3.00E-01

4.00E-01

5.00E-01

6.00E-01

7.00E-01

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

Gate Voltage, V

Tran

scon

duct

ance

, S

6 × 150

2 × 60 4 ×75

Figure 2: Measured gm for the various HEMT layouts

From the results shown, the 6 × 150 HEMT exhibited higher gm with values more than double compared to other layouts. The higher gm is due to increased Ids in a bigger device size as proved in [9]. This would affect the cut-off frequency performance of the device provided that Cgs and Cgd are not dominant. The simulated S21 values for all the HEMT layouts are shown in Figure 3.

5 10 15 20 25 30 350 40

0

5

10

15

20

25

-5

30

freq, GHz

dB(S

(2,1

))(

(,

))

Figure 3: Simulated S21 for the various HEMT layouts

The simulation portrayed in Fig. 3 suggests that the gain for devices with higher number of gate fingers is better at low frequencies from DC up to 3 GHz. The gain of the 6 × 150 layout at 1 GHz, for example, was 27 dB, about 12 dB and 6 dB higher than the 2 × 60 and 4 × 75 devices respectively. However, as the frequency increased, the gain of this device reduced significantly until, at certain frequencies, the gain was worse compared to others. The gain for the 6 × 150 layout dropped to 0 dB at about 28 GHz. The other devices, on the other hand, still exhibited some gain at this frequency. In summary, the simulations suggest that layouts employing bigger number of fingers would not suitable for high frequency applications.

On the other hand, the simulation result shows that the gain of 2 × 60 HEMT layout is quite stable. The gain dropped slightly throughout the frequency range, reaching 0 dB at frequencies higher than 60 GHz. Based on the simulation, the 2 × 60 HEMT would be better suited for broadband applications due to the gain stability. Besides that, the values of fT for all the layouts were computed by transforming the S-parameters to h-parameters and then extrapolated at -20dB/decade. The simulated fT for all the layouts is shown in Fig. 4.

0

5

10

15

20

25

30

35

40

1.0E+09 1.0E+10 1.0E+11

Frequency, Hz

Cur

rent

Gai

n, |h

21|,

dB

2x604x756x150

Figure 4: Extraction of fT from simulation

Based on the simulation results above, the fT for 6 × 150 and 2 × 60 designs are about the same value of around 70 GHz. However, the fT of 4 × 75 HEMT layout is lower compared to these two layouts. The simulation results imply that devices with higher gate fingers exhibit lower cut-off frequency if Cgs and Cds are more dominant compared to gm. For the case of 6 × 150 HEMT, the fT is higher because the gm is assumed very high and sufficient enough to eliminate the dominancy of Cgs and Cgd. However, all the assumptions obtained from simulation must be validated in real device measurement. Fig. 5 illustrates the measured gain responses of the fabricated devices.

6 × 150

4 × 75

2 × 60

-5

0

5

10

15

20

25

0 10 20 30 4

Frequency, GHz

S21,

dB

0

6 × 150

4 × 75

2 × 60

Figure 5: Measured S21 for the various HEMT layouts

Fig. 5 illustrates the measured gain of the various transistor gate layouts used. The response shows a trend similar to those obtained from simulation. Only the magnitude of the gain is slightly reduced due to the losses which were unaccounted for in the simulation. However, the most important point here is that the trend where the device with higher number of gates exhibited higher gain at low frequencies. At frequencies higher than 3 GHz, the gain started to drop significantly, in agreement with the simulation. This behavior can be explained by the relationships given by 2.2 and 2.3 where for bigger devices, Cgs and Cgd are more dominant compared to gm. Due to the dominancy of these two capacitance effects, the cut-off frequency as described in 2.4 also dropped significantly when the operating frequency increases. This effect is clearly illustrated in the extraction of fT from the measured S-parameter shown in Fig. 6.

0

5

10

15

20

25

30

35

40

1.0E+09 1.0E+10 1.0E+11Frequency, Hz

Cur

rent

Gai

n, |h

21|,

dB

2x604x756x150

Figure 6: Extraction of fT from the measurement As expected, the simulated fT for the 4 × 75 HEMT layout is lower than those for 2 × 60 designs. The fT of this layout was around 50 GHz. The slight difference of the frequency could be due to a variation in the capacitance values calculated from simulation and measurement. The 6 × 150 design however demonstrated a lower fT of around 28 GHz only, which was much less than the simulated value. This is expected due to the variation of Cgs and Cgd values found from measurement that affected fT. In addition parasitic capacitances, which can be considerable at high frequencies, may also contribute additional errors in the cut-off frequency. Nevertheless, both patterns exhibit similar behavior and show close agreement throughout most of the frequency range considered.

5. Conclusion

We have carried out a detailed study of the effect of multiple-gated HEMT layout on the gain-frequency response. Even though higher DC gain was obtained from bigger devices, this does not automatically imply better RF gain. The gain response needs to be monitored carefully since the dominancy of Cgs and Cgd for a bigger device is quite obvious. For high frequency applications, our findings seem to indicate that HEMTs with higher gate fingers are less preferred. In addition, the extra space taken up by bigger devices on a die is also one of the key points that need to be considered in a design. It is therefore essential that the final application is considered in the early stages of a design since this will dictate the number of gate fingers required.

Acknowledgment

The authors would like to thank TM Research and Development Sdn. Bhd. for providing the measurement facilities and to Microwave Technology

Centre, Faculty of Electrical Engineering, UiTM Shah Alam for providing technical support in this research.

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