ieee 12th international symposium on embedded …“an efficient parallel hardware scheme for...
TRANSCRIPT
IEEE 12TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP
Vietnam National University, Hanoi, VietnamSeptember 12-14, 2018
1
Program at a Glance
DAY 1 September 12, 2018 DAY 2 September 13, 2018 DAY 3 September 14, 2018
08:00-16:00 Registration 08:00-16:00 Registration 08:00-16:00 Registration
8:30-10:05
Opening
8:30-12:00
Tutorial 1: Learn to Capture the Body Motion with Inertial Sensing Method in 3 Hours Lei Jing (Univ. of Aizu, Japan)
8:00-10:35
Keynote 4 : Hans G. Kerkhoff (Univ. of Twente, Netherlands)
Keynote 1 : Chong-Min Kyung (KAIST, South Korea)
Session-7. Multicore/Manycore Interconnection Networks
10:05-10:20 Coffee Break 10:35-10:50 Coffee Break
10:20-12:00
Session-1. Multicore/Manycore SoCs Architectures and Programming
10:50-12:30
Session-8: Special Session on Scalable and Flexible Many-Core Mapping Techniques
12:00-13:00 Lunch 12:00-13:00 Lunch 12:30-13:30 Lunch
13:00-15:35
Keynote 2 : Ryuichi Oka (Univ. of Aizu, Japan)
13:00-14:45
Keynote 3 : Van Tam Nguyen (Telecom ParisTech, France & INTEK, Vietnam)
13:30-15:10 Session-9. Multicore/Manycore SoCs Applications
Session-2. Multicore/Manycore SoCs Design
Session-4: Special Session on Intelligent Systems and Learning Technologies: Models, Methods, and Applications
15:10:15:25 Coffee Break
15:25-17:30
Session-10. Algorithms and Hardware for Learning On-chip and Embedded Neuromorphic Computing Systems 14:45-16:00
Session-5. Embedded and Real-time Multicore/Manycore SoC Systems
15:35-15:50 Coffee Break 16:00-16:15 Coffee Break
17:30-17:50 Closing 15:50-17:30
Session-3: Special Session on Artificial Intelligent for Multimedia Communications
16:15-17:30
Session-6: Special Session on Auto-Tuning for Multicore and GPU (ATMG2018)
17:30-21:00 Gala Dinner
2
Time-table & Program
Wednesday, September 12, 2018
Session Time Duration Details
08:00-8:30 30 min Registration
Opening
8:30-9:10 40 min Opening
9:10-10:05 55 min
Keynote 1 : “Rolling up Asia Vision Through Intertwining Research and Business Development (R&BD) Around Smart Sensor Systems Technology” Chong-Min Kyung (KAIST, South Korea)
10:05-10:20 15 min Coffee Break
Session 1 10:20-12:00
100 min
Session-1: Multicore/Manycore SoCs Architectures and Programming Session Co-chairs: Toshiaki Miyazaki, (University of Aizu, Japan) and Xuan-Tu Tran (VNU-UET, Vietnam)
25 min
“Code Generation of Graph-Based Vision Processing for Multiple CUDA Cores SoC Jetson TX” Elyassaf Madar, Natan Danan and Elishai Ezra Tsur (Jerusalem College of Technology, Israel)
25 min “An FPGA Scalable Parallel Viterbi Decoder” Yosi Ben-Asher, Vladislav Tartakovsky, Katrina Portman, Orr Zilberman and Avishi Hadar (University of Haifa, Israel)
25 min
“An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem” Yuuma Azuma, Hayato Sakagami and Kenji Kise (Tokyo Institute of Technology, Japan)
25 min
“Architecture and Hardware Design of a Low-cost Spike-based PID Controller for Quadcopters” Shunsuke Mie, Yuichi Okuyama and Hiroaki Saito (University of Aizu, Japan)
12:00-13:00 Lunch
Session 2 13:00-15:35
155 min Session-2: Multicore/Manycore SoCs Design Session Co-chairs: Kenji Kise (Tokyo Institute of Technology, Japan) and Vu Hoang Gia (Le Quy Don Technical University, Vietnam)
55 min Keynote 2: “Field Computation Architecture of Algorithms for Intelligent and Smart Pattern Processing” Ryuichi Oka (University of Aizu, Japan)
25 min “Unifying Wire and Time Scheduling for Highlevel Synthesis” Yosi Ben-Asher (University of Haifa, Israel) and Irina Lipov (IBM HRL. Haifa, Israel)
25 min
“IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs” Khoa Pham, Edson Horta, Dirk Koch, Anuj Vaishnav (University of Manchester, United Kingdom (Great Britain)) and Thomas Kuhn (HTV GmbH, Germany)
25 min
“On-Chip Lifetime Prediction for Dependable Many-Processor SoCs based on Data Fusion” Ghazanfar Ali, Jerrin Pathrose (University of Twente / CTIT Research Institute, The Netherlands) and Hans Kerkhoff (University of Twente, The Netherlands)
3
25 min
“Design features of analog-to-digital solutions for the tracking detector readout electronics” Aleksandr Kostrov, Viktor R. Stempitsky (Belarusian State University of Informatics and Radioelectronics, Belarus), Artur Borovik (Belarusian State University of Informatics and Radioelectronics (BSUIR), Belarus) and Vladimir Tchekhovsky (Research Institute for Nuclear Problems of Belarusian State University, Belarus)
15:35-15:50 Coffee Break
Session 3 15:50-17:30
100 min Session-3: Special Session on Artificial Intelligent for Multimedia Communications Session Chair: Xiem Hoang (VNU-UET, Vietnam)
25 min “Bluetooth Low Energy based Indoor Positioning on iOS platform” Son Ngoc Duong, Anh Vu-Tuan Trinh and Thai-Mai Dinh (University of Engineering and Technology (VNU-UET), Vietnam)
25 min
“A Practical High Efficiency Video Coding Solution for Visual Sensor Network using Raspberry Pi Platform” Nguyen Thi Huong Thao, Huy Phi, Huu-Tien Vu (Post and Telecommunications Institute of Technology (PTIT), Vietnam) and Xiem Hoang (VNU-UET, Vietnam)
25 min “Adaptive Long-term Reference Selection for Efficient Scalable Surveillance Video Coding” Xiem Hoang, Le Dao Thi Hue and Giap Pham (VNU-UET, Vietnam)
25 min “Light Field Image Coding for Efficient Refocusing” Vinh Duong, Thuong Nguyen Canh and Byeungwoo Jeon (Sungkyunkwan University, Korea)
Thursday, September 13, 2018
Session Time Duration Details
Tutorial 8:30-12:00 210 min Tutorial 1: “Learn to Capture the Body Motion with Inertial Sensing Method in 3 Hours” Lei Jing (University of Aizu, Japan)
12:00-13:00 Lunch
Session 4 13:00-14:45
105 min
Session-4: Special Session on Intelligent Systems and Learning Technologies: Models, Methods, and Applications Session Chair: Van-Phuc Hoang (Le Quy Don Technical University, Vietnam)
55 min Keynote 3 : “Cognitive Computation and Communication: A Complement Solution to Cloud for IoT” Van Tam Nguyen (Telecom ParisTech, France & INTEK, Vietnam)
25 min
“Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-criteria Recommender System” Mohamed Hamada (University of Aizu, Japan), Latifat Ometere Abdulsalam (African University of Science and Technology, Nigeria) and Mohammed Hassan (Bayero University, Kano, Nigeria)
25 min
“A Fuzzy-based Approach for Modelling Preferences of Users in Multi-criteria Recommender System” Odu Nkiruka (African University of Science and Technology, Nigeria), Mohamed Hamada (University of Aizu, Japan) and Mohammed Hassan (Bayero University, Kano, Nigeria)
4
Session 5 14:45-16:00
75 min
Session-5. Embedded and Real-time Multicore/Manycore SoC Systems Session Chair: Duc-Hung Le (HCMUS, Vietnam) and Akram Ben Ahmed (Keio University, Japan)
25 min
“A Low-power ASIC Implementation of Multi-core OpenSPARC T1 Processor on 90nm CMOS Process” Phuc-Vinh Nguyen (Applied Micro Circuits Corporation Vietnam, Vietnam) and Duc-Hung Le (The University of Science Ho Chi Minh City, Vietnam)
25 min
“A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-time Scheduling” Duy Doan and Kiyofumi Tanaka (Japan Advanced Institute of Science and Technology, Japan)
25 min
“Multikernel Design and Implementation for Improving Responsiveness of Aperiodic Tasks” Hidehito Yabuuchi, Shinichi Awamoto, Hiroyuki Chishiro (The University of Tokyo, Japan) and Shinpei Kato (Nagoya University, Japan)
16:00-16:15 Coffee Break
Session 6 16:15-17:30
75 min
Session-6: Special Session on Auto-Tuning for Multicore and GPU (ATMG2018) Session Co-chairs: Kazuhiko Komatsu (Tohoku University, Japan); Nam-Khanh Dang (VNU-UET, Vietnam)
25 min
“Search Space Reduction for Parameter Tuning of a Tsunami Simulation on a Many-core Processor” Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato (Tohoku University, Japan), Akihiro Musa (Tohoku University / NEC Corporation, Japan) and Hiroaki Kobayashi (Tohoku University, Japan)
25 min
“Communication-Avoiding Tile QR Decomposition on CPU/GPU Heterogeneous Cluster System” Masatoshi Takayanagi and Tomohiro Suzuki (University of Yamanashi, Japan)
25 min
“Freeze-Safe IoT Hibernation using Power Profile Monitor based on Communication-Centric Auto-Tuning” Hyeon-Gyun Moonand and Daejin Park (Kyungpook National University, Korea)
Gala Dinner
17:30-21:00
Gala Dinner: - Introduction to Viettel IC Design Center - Announcement of MCSoC-2019 - Best paper award
Friday, September 14, 2018
Session Time Duration Details
Session 7 8:00-10:35
155 min Session-7: Multicore/Manycore Interconnection Networks Session Chair: Duy-Hieu Bui (VNU-UET, Vietnam) and Yuichi Okuyama (University of Aizu)
55 min Keynote 4 : “How to Guarantee High Dependability of Future Many-Core Systems-on-Chip” Hans G. Kerkhoff (Univ. of Twente, Netherlands)
5
25 min
“In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures” Leonard Masing (Karlsruhe Institute of Technology (KIT), Germany), Srivatsa Akshay (Technical University of Munich, Germany), Fabian Kress and Nidhi Anantharajaiah (KIT, Germany), Andreas Herkersdorf (Technical University of Munich, Germany) and Juergen Becker (KIT, Germany)
25 min
“Adaptive Body Bias Control Scheme for Ultra Low-power Network-on-Chip Systems” Akram Ben Ahmed, Hayate Okuhara and Hiroki Matsutani (Keio University, Japan), Michihiro Koibuchi (National Institute of Informatics, Japan)and Hideharu Amano (Keio University, Japan)
25 min “Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication” Khanh N. Dang and Xuan-Tu Tran (VNU-UET, Vietnam)
25 min “MARTE and IP-XACT based approach for run-time scalable NoC” Hiliwi Leake Kidane and El-Bay Bourennane (University of Burgundy, LE2i Laboratory, France)
10:35-10:50 15 min Coffee Break
Session 8 10:50-12:30
100 min
Session-8: Special Session on Scalable and Flexible Many-Core Mapping Techniques Session Chair: Jeronimo Castrillon (TU Dresden, Germany); Kiem-Hung Nguyen (VNU-UET, Vietnam)
25 min “Industrial Keynote: Computing Platform for Automotive Electronics System Architecture” Takashi Abe (DENSO Corporation, Japan)
25 min
“Scalable Dynamic Task Scheduling on Adaptive Many-Core” Vanchinathan Venkataramani (National University of Singapore (NUS), Singapore), Anuj Pathania (Karlsruhe Institute of Technology (KIT), Germany), Muhammad Shafique (Vienna University of Technology (TU Wien), Austria), Tulika Mitra (NUS Singapore, Singapore) and Jörg Henkel (KIT, Germany)
25 min
“On the Complexity of Mapping Feasibility in Many-Core Architectures” Tobias Schwarzer, Sascha Roloff (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany), Valentina Richthammer (Ulm University, Germany), Rami Khaldi, Stefan Wildermann (FAU, Germany), Michael Glass (Ulm University, Germany) and Jürgen Teich (FAU, Germany)
25 min “On the Representation of Mappings to Multicores” Andres Goens, Christian Menard and Jeronimo Castrillon (TU Dresden, Germany)
12:30-13:30 Lunch
Session 9 13:30-15:10
100 min Session-9: Multicore/Manycore SoCs Applications Session Chair: Duc-Minh Nguyen (HUST, Vietnam) and Incheon Paik (University of Aizu, Japan)
25 min
“Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-Core Processor” Moisés Urbina and Roman Obermaisser (University of Siegen, Germany)
6
25 min
“Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records” Elsayed A. Elsayed (Tokyo Institute of Technology, Japan and Aswan University, Egypt) and Kenji Kise (Tokyo Institute of Technology, Japan)
25 min
“On-line Cost-aware Workflow Allocation in Heterogeneous Computing Environments” Incheon Paik , Yuji Ishizuka, Quang Minh Do (University of Aizu, Japan) and Chen Wuhui (Sun Yat-sen university, P.R. China)
25 min
“FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT” Kenji Kanazawa (University of Tsukuba, Japan) and Shaowei Cai (Chinese Academy of Sciences, P.R. China)
15:10-15:25 Coffee Break
Session 10 15:25-17:30
125 min
Session-10: Algorithms and Hardware for Learning On-chip and Embedded Neuromorphic Computing Systems Session Chair: Cong-Kha Pham (UEC, Japan) and Trinh Quang Kien (Le Quy Don Technical University, Vietnam)
25 min “Industrial Keynote: Efficient Neural Network processing elements on Xilinx FPGA devices” James Lau (Avnet Asia, Singapore)
25 min
“VLSI Design of Floating-point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations” Trong-Thuc Hoang (University of Electro-Communications (UEC), Japan), Duc-Hung Le (The University of Science Ho Chi Minh City, Vietnam), and Cong-Kha Pham (University of Electro-Communications (UEC), Japan)
25 min
“An Efficient Hardware Implementation of Activation Functions Using Stochastic Computing for Deep Neural Networks” Van-Tinh Nguyen, Tieu-Khanh Luong, Han Le Duc and Van-Phuc Hoang (Le Quy Don Technical University, Vietnam)
25 min
“Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators” Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura and Shinya Takamaeda-Yamazaki (Hokkaido University, Japan)
25 min
“Designing Compact Convolutional Neural Network for Embedded Stereo Vision Systems” Mohammad Loni (Malardalen University, Sweden), Amin Majd (Abo Akademi, Finland), Masoud Daneshtalab (Mälardalen University, Sweden), Mikael Sjödin (MDH, Sweden) and Elena Troubitsyna (KTH, Finland)
Closing 17:30-17:50 20 min Closing ceremony