idesa cmos physics using mastar part 2of2x

8/13/2019 IDESA CMOS Physics Using MASTAR Part 2of2x

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Tutorial 11

For industrial feasibility evaluation

1


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DESCRIPTION

Simulating propagation delay in inverter chain loadedwith capacitive and resistive systems

Calculating the Static Noise Margin of 6T-SRAMcells

Using the randomization effects in order to evaluate

T. Skotnicki & F. Boeuf

electrical performance of circuits.

2


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Inverter Speed Evaluation, incl. RC Line

LG

lint

MX


3

Inverter 1 Inverter 2 Inverter N

Cload

Rline

Cload

Rline

Cload

Rline

Inverter 1 Inverter 2 Inverter N

Cload

Rline

Cload

Rline

Cload

Rline

Cload

Rline


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Ex-1 : Computing Inverter Delay

including interconnectionsInput here1- the number of stage2- timing information3 the period of the input signal

4 R and C values for the BEOL5 click compute

T. Skotnicki & F. Boeuf4

Inputsignal

Signal output at stage 2

Signal output at last stage (here 4)


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5

Delay at Vdd/2extraction


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Ex- 2 : Computing SRAM SNM

Click here to start theSRAM evaluation



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When boxes are uncheck,only 1 SNM is computed


Note : to bring the ComputeMenu, just right click here in

the graph windows


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Ex- 4 : Computing SRAM SNM

If none of the box arechecked 1 cellcalculation

Calculation precision


If at least one of the boxis checked severalcell calculation with random variation onselected parameters


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If Only halfcell calculation ischecked, computationtime will be divided by 2,but butterfly curve will

always be symetric


If Only halfcell calculation is notchecked, computation

time butterfly can beassymetric


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Check boxes to generatevariability

Choose the number ofgenerated SNM.


Check enable Symetrical

curve to compute only a halfcell, or uncheck to generatethe whole cell variability

After calculation, statisticaldata are available

Choose the data to display


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Tutorial 12

11


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Description

Objective : evaluate the inverters delay as a function oflayout of transistors, interconnection length, and processvariability

Content

Background Elements

Parasitic Capacitances of MOSFETs


Input and Output capacitance of an Inverter chain

Ex-1 : Influence of N/P Ratio on Inverters delay

Ex-2 : Optimal N/P ratio in the case of a boosted PMOS transistor

Ex-3 : Impact of process variability on the worst-case

inverters speed Ex-4 : Influence of interconnect wire length on speed

performance

12


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Bibliography

An Evaluation of the CMOS Technology Roadmap From the Point of View ofVariability, Interconnects, and Power Dissipation Boeuf, F.; Sellier, M.; Farcy, A.;Skotnicki, T.; Electron Devices, IEEE Transactions on Volume 55, Issue 6, June2008 Page(s):1433 1440 Digital Object Identifier 10.1109/TED.2008.921274

Predictive Delay Evaluation on Emerging CMOS Technologies: A SimulationFramework, Manuel SELLIER, Jean-Michel PORTAL, Bertrand BOROT, SteveCOLQUHOUN, Richard FERRANT, Frdric BOEUF, Alexis FARCY QualityElectronic Design, 2008. ISQED 2008. 9th International Symposium on 17-19 March2008 Page(s):492 497


Using MASTAR as a Pre-SPICE Model Generator for Early TechnologyAssessment and Circuit Simulation Frederic Boeuf, Manuel Sellier, Fabrice Payet,Bertrand Borot and Thomas Skotnicki , Jpn. J. Appl. Phys. 47 (2008) pp. 3384-3389

CMOS Technology Roadmap Projection Including Parasitic Effects, Lan Wei,Frdric Boeuf, Thomas Skotnicki, H.-S. Philip Wong*, VLSI-TSA 2009

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Capacitance definition

Cgc: on-state gate-to-channel cap Cgb_off: off-state gate to substrate cap.

Cov: overlap cap Cof: outer-fringe cap Cif: inner-fringe cap

Cgb


pcca: po y o con ac p ug cap. Cj: junction cap

Ccorner: corner cap, from thegate overlay to S/D

Ref.: Lan Wei, STMicroelectronics-STANFORD Univ. Collaboration pgm.& Lan Wei , VLSI TSA 2009


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Caps for a Single DeviceCd (on) Cg(on) Cg(off)

Cgc Gate-to-channel

Cgb_off Gate-to-sub

Cov Gate overlap

Cof Gate outerfringe

Cif Gate inner fringe

Cpcca Gate to plug


Cgb_off and Cif are shielded by the channel inon-state

Cgc is not seen by drain node in on-state, dueto pinch-off.

Ccorner Corner cap Cj Junction cap

Ref.: Lan Wei, STMicroelectronics-STANFORD Univ. Collaboration pgm.

& Lan Wei , VLSI TSA 2009


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P1

IN1

VDD

CGDP1

CGDN1

CJDP1

CJDN1

OUT1

P2

IN2

VDD

CGDP2

CGDN2

OUT2

INTERCO

CGBP2

CGSP2

1

4

3

2

65

34

5

76 1

7

6

1 2

2 43 5

OFF-ONON-ON

8

8

CGD1 xMILLER

CGD2 NOMILLER

Caps for an Inverter Chain


N1 N2CINTERCOCGBN2

CGSN2

( )

444444444444444444 3444444444444444444 21

4444444 34444444 21

2

2,2,222,2,22

interco

1

1111

75.025.075.025.0

2

stageinput

GSNONGBNOFFGBNGDNGDPONGBPOFFGBPGSP

stageoutput

jDNjDPMillerGDNGDPL

CCCCCCCC

CCCCCC

+++++++

+++++=

ON-ONON-OFF


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Capacitance for an Inverter Chain

( )_ _0.25 0.75tot

dg j g off g on interconnect

C

C Miller C C C FO C = + + + +

Cout (seen bydrain)

Cin(seen bygate)


( )

( )

0.25

0.75

ov of pcca corner j

gc ov of pcca corner

ov of pcca corner

interconnect

C C C C Miller C

C C C C C FO

C C C C C

= + + + +

+ + + + + + + + +

+


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With MASTAR5

MASTAR System Layout Function Calculate by full waveform calculation FO1, FO3 are estimated by

_ 1(3)

1(3) _ 11

inverter FO

FO adjusted fF

C

fF =


, inverter_FO1(3)

models Different design possibilities are analyzed Wn/Wp ratios, high driving-capable PMOS


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Ex-1 : N/P Ratio (1)1. Open the system profile basline.xsy2. Note the ratio between NMOSs Ion and PMOSs Ion : 727/396 = 1.833. Set Wp=720nm and Wn=360nm4. Peform the calculation of teh inverters delay.5. Write down the TpFO1 value

(1)

(3)

(4)


(2) (5)


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Ex-1 : N/P Ratio (2)

/

360 180 0.5

-Calculate the delay of a FO1 inverter for the following configurations- plot the delay as a function of WP/WN-Q : Explain the behavior


360 360 1

360 720 2

240 720 3

180 720 4


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Ex-1 : N/P Ratio - Answer

/ 1 () / ()

360 180 0.5 22.12 15.53 1.42

360 360 1 17.86 .7 1.71

360 720 2 17.21 6.8 2.53

240 720 3 1.43 8.5 2.2

180 720 4 21.87 10.11 2.164

23

24

25

)

C at optimum speed is2.53fF

Optimal Intrinsic delay is 6.8ps

= x


15

16

17

18

1

20

21

22

0 1 2 3 4

(

Min~1.8


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Ex-2 : Boosting the PMOS


-Calculate the delay of a FO1 inverter forthe following configurations- plot the delay as a function of WP/WN-Q : Explain the behavior


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Ex-2 : N/P Ratio with Boosted pMOS

/ 1 () / ()

360 180 0.5 14.2 .7 1.42

360 360 1 12.1 6.8 1.7

360 720 2 12.62 4. 2.53

240 720 3 14.72 6.44 2.2180 720 4 16.2 7.82 2.16

24

But C at optimum speed is now1.79fF

Intrinsic delay is still 6.8ps


10

12

14

16

18

20

22

0 1 2 3 4

(

)

Min~1.0


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Ex-3 : Delay and Variability

Objective : Study the impact of technology variability on deviceperformance / speed

Context

Every technology feature intrinsic variations due to process variation orstochastic variations

Transistor gate length , 3 = 12%*Lgate (ITRS)

Stochastic variation of electrode workfunction due to random dopant


uc ua ons n o y- con e ec ro e or me a c gra n or en a on uc ua on

(in metallic electrode), ~10mV Random Fluctuation of transistors channel doping [Mizuno et al. VLSI 93]

Junction depth variation

This will impact the Vth and the Idsat of transistors and therefore createa statistical distribution of inverters delay

24


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Ex-3 - Worst Case Process Simulation

(1)(2)



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Ex- 4 :Variability and Delay : A roadmap Analysis

Q :Use the following table to analyse the scaling of invertersdelay as well as the scaling of the worst case delay (i.e delay+ 3)


After F.Boeuf et al., T-ED 2008


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Ex-4 : Variability and Delay

Answer : as devices are scaled down, they are more and moresenstivite to variability sources. As a consequence, after 50nm half-pitch generation, the worst case delay is scaling slower (4%

faster/year) than the average delay (17% faster / year)


After F.Boeuf et al., T-ED 2008


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Ex- 5 Impact of Wire Length on Delay

(1)

L,R negligeable


(2)

8.72ps


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30

35

Assume R= 2.0 Ohm/m

Assume C= 200 aF/m

Ex- 5 Impact of Wire Length on DelayQ1 :Calculate the propagation delay after the stage 2 for L varying between 0 and 50m.What is the maximum wire length possible ?Q2 : How to go beyond this value ?

(corresponding to 2005 ITRS values)

Answer to Q1 :


0

5

10

15

20

25

0 5 10 15 20 25

()

() () ()

0 0 0 8.72

1 2 2.0016 .87

10 20 2.0015 20.28

20 40 4.0015 31.32

50 100 1.0014 /


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L=10m

L=1m

L=20m


(Signal starts to be deformed = Lmax)

Answer to Q1 (cont)


L=50m

(Signal cannot propagate correctly)


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Answer to Q2

Increase Wn and Wp toachieve highertransistors drivecurrent . E.g. multiplyWn and Wp by 2.0


L=20m L=40m

New Lmax is above 40m

E 6 I t D l d M t l Li R i t


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Ex- 6 : Inverters Delay and Metal Line Resistance accrosthe Roadmap

Q :Use the following table to analyse the scaling of invertersdelay across the ITRS roadmap, for a wire length scalingbetween 0.68x per year and 0.8x per year


Ex 6 : Inverters Delay and Metal Line


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Ex- 6 : Inverters Delay and Metal LineResistance accros the Roadmap

Answer

For 0.8x, delay is not scalingat all with the technology !


For 0.68x, delay is properly

scaling as inverter delay with aFO1 load


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Bibliography

Innovative Materials, Devices, and CMOS Technologies for Low-PowerMobile Multimedia Thomas Skotnicki, Claire Fenouillet-Beranger, ClaireGallon, Frederic Boeuf, Stephane Monfray, Fabrice Payet, Arnaud

Pouydebasque, Melanie Szczap, Alexis Farcy, Franck Arnaud, Sylvain

Clerc, Manuel Sellier, Augustin Cathignol, Jean-Pierre Schoellkopf, ErnestoPerea, Richard Ferrant, and Herv Mingam, Trans. On Elec. Dev. InvitedPaper, Volume: 55, Issue: 1, page(s): 96-130 (2008)

An Evaluation of the CMOS Technology Roadmap From the Point of


View of Variability, Interconnects, and Power Dissipation Boeuf, F.;Sellier, M.; Farcy, A.; Skotnicki, T.; Electron Devices, IEEE Transactions onVolume 55, Issue 6, June 2008 Page(s):1433 1440 Digital ObjectIdentifier 10.1109/TED.2008.921274

Is a Power Optimized Roadmap Realistic for High Performance

Applications? Frederic Boeuf and Thomas Skotnicki, In Extented Abstractsof SSDM 2007 (JSAP CAT AP071239), pp. 258-259

34


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Tutorial 13 :

35


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DESCRIPTION

Starting from a relatively old device profile, we will carryout a series of modifications to end up with a scaled-down up-to-date device. The following analysis and

modifications will be considered: Pocket implants

SCE and DIBL


Junction depth reduction

36


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Ex. 1:

STARTING DEVICE PROFILEAnalysis of problems


IDESA Start

37

St ti d i fil (IDESA St t)


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Starting device profile (IDESA Start)


38

St ti d i fil l i


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Note that the channel doping is constant (2e17 cm-2) The threshold voltage drops rapidly down

Already at Lgate=137nm, Vthsatoff reads at no more than

150mV that corresponds to Ioff=10nA/m For many applications this is already difficult to tolerate

Not to mension that such long Lgate would have a detrimental

Starting device profile analysis


effect on the density of integration

Remember that this IDESA Start profile corresponds(except for Lgate) to a LOP 65nm CMOS, where the gateshould read at 65nm or below

The first point we will analyse is thus how to make the gateshorter without lowering the Vthsatoff?

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Ex. 2USE OF POCKET IMPLANTS

%a commonly used technique enabling


40


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USE OF POCKET IMPLANTS


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USE OF POCKET IMPLANTS

Pocket im lantation conditions


42

Gain in Lgate minimum thanks to pockets

POCKETS analysis


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Note that instead of the same Vthsat, the Ioff (leakage is not the same aswithout pockets.

This is because of relaxation in the Subthreshold Slope

POCKETS analysis

SS SubthresholdSlope

Log(Id)

+

+++=

d

ds

el

dep

el

j

el

ox

ox

Si

ox

dep V

L

T

L

X

L

T

C

C

q

kTS 21

4

311)10ln(


The major source of this relaxation in SS comes from the Cdep/Cox term =[eps(Si)/eps(Ox)]x(Tox/Tdep) term

Pockets increase the doping that leads to a decrease in

( )SBdB

Sidep V

qNT +=

2

That leads to an increase in SS (68 without pockets and 91 with)


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Ex. 3HOW TO REDUCE Lgate,min FURTHER?

%REDUCTION OF SCE and DIBL

(note that in the last example with pockets,E= V D BL= V w

T. Skotnicki & F. Boeuf 44

before, i.e. without pockets they wereSCE=26mV and DIBL=40mV. This means thatapplication of pockets was not totally capable

of cancelling the relaxation in ElectrostaticIntegrity of the device that is caused by thereduction of the gate from 137 nm to 53 nm)

UNDERSTANDING SCE and DIBLUNDERSTANDING SCE and DIBL


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UNDERSTANDING SCE and DIBLUNDERSTANDING SCE and DIBL

-

Long channel

-short

SCE Short Channel EffectSCE

Bothe SCE and DIBLlower the barrier thatappears to the electronswishing to move fromsource to drain, andtherefore both lead tomore leaka e current Ioff


- SCE

DIBL

Vds

DIBL Drain Induced Barrier Lowering

channel

SCE DIBL & RSCE IMPACT ON Vth L


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RSCESCE0.3

0.4

VD=0.1V RSCESCE

0.3

0.4

RSCESCE0.3

0.4

VD=0.1V

DIBLSCERSCEVV Lthth += ,

SCE, DIBL & RSCE IMPACT ON Vth-L:

T. Skotnicki & F. Boeuf T.Skotnicki

DIBLVth

(V

0.1

0.2

010010 1000

L (nm)

th

VD=VDDDIBLVth

(V

0.1

0.2

010010 1000

L (nm)

th

DIBLVth

(V

0.1

0.2

010010 1000

L (nm)

th

VD=VDD

SCE & DIBL DEPEND ON RATIOS,


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RATHER THAN ON VALUES OF PARAMETERS :

DIBLSCEVV Lthth = ,

deelox TTX _2

EIL

SCE

DIBL

Vth,L

REF.: T. Skotnicki, invited paperESSDERC 2000, pp. 19-33, edit.Frontier Group


delelelox LLL 2.

=

DS

el

dep

el

elox

el

j

ox

Si VLT

LT

LXDIBL _

2

2

180.0

+=

B

DSidep

qNT

2=


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Ex. 4REDUCTION OF SCE and DIBL

%Via reduction of junction depth Xj


48

REDUCTION OF JUNCTION DEPTH


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REDUCTION OF JUNCTION DEPTH

Improved SCE and DIBL thanks to reduced Xj


49

Gain in Lgate minimumthanks to Xj reduction


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Tutorial 14 :Hi h-K /Metal Gate Stack

50

DESCRIPTION


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DESCRIPTION

Cancellation of polydepletion

Gate oxide reduction

Readjustment of pockets

New Lgate,minimum Gate leakage

In r i n f HK i l ri


51


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Ex. 1REDUCTION OF SCE and DIBL

%Via reduction of Oxide Thickness


52

(note that the effective gate dielectricthickness is a summ of the physical gatedielectric thickness, of the polydepletion

and of the so called Dark space - seenext slide)

POLYDEPLETION & DARK SPACE:


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SiO2

3D electrons

N+Poly-gate Si-P-substrate

3D electronsin the gate

SiO2

3D electrons

N+Poly-gate Si-P-substrate

3D electronsin the gate

spacedarkSi

SiOpolydep

Si

SiOphysoxelox TTTT ___ 22

++=


2D electronsin the channel

Darkspacein the channel

Polydepletion

Darkspacein the gate

2D electronsin the gate inaccumulation

2D electrons

in the gate indepletion

2D electronsin the channel

Darkspacein the channel

Polydepletion

Darkspacein the gate

2D electronsin the gate inaccumulation

2D electrons

in the gate indepletion

IMPLICATIONS OF Tox REDUCTION


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( ) ( )

ox

oxox

ox

SBdBSi

F

ox

ssSmth

TC

where

C

VqN

C

qNV

=

++++=

22,


54

Note thatreduction of Tox not only leads to reduced SCEand DIBL but also to a reduction in long-

channel thresholod voltage that therefore needsto be compensated by increased doping orreadjusted gate work function.


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IMPLICATIONS OF Tox REDUCTION


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56

Same Vth is maintained due to readjustmentof the gate workfunction

Reduced alsoleads to gate

leakage


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Ex. 2

READJUST POCKETS and TRADE ALLIMPROVEMENTS in SCE and DIBL


57

Lgate,minimum

NEW IMPROVED TECHNOLOGY !


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Ioff is back to


58

Pocket implantationconditions readjusted

But Lgate isX4 shorter !!!


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Ex. 3

PROBLEM OF Igate%


59

(note that once we have thinned Tox from 1.8nm to 1.2nm, theIgate leakage increased from 1.18e-1nA/m to 8.33e+2nA/m thusexceeding the channel leakage Ioff=1.02e+1nA/m. This situation

is not tolerable !)

MASTAR Igate MODEL (very good :


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1.E+031.E+05

1.E+07

A/cm2)

2.2 nm2 nm1.8 nm1.6 nm1.4 nm1.2 nm

Ig[A/cm2] =1.44e5*(Exp(-4.02*Ug[V]^2+13.05*Ug[V])*Exp(-1.17*Tox[])Sim. Data


1.E-07

1.E-051.E-031.E-01

.

0 0.2 0.4 0.6 0.8 1 1.2 1.4Ugate (V)

Ig

1 nm0.8 nm0.6 nm0.4 nmMASTAR

analytical model

Simulation data : Hauser, NCSU, UQUANT model


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Gate leakage must not exceed the channel leakage


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Huge reduction in Igoff, from 8.33e2 nA/m to1.96e0 nA/m thanks to HK


62

If EOT=constant is

selected, MASTARwill automaticallycalculate the reqiredTIF (Technology

ImprovementFactor=Igate,SiO2/Igate,H-K) from thesettings given by theuser

CONCLUSIONS (DEVICE SCALING & HK / Metal G)


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The final device profile we have achieved presentslargely shorter gate (reduced X4)

All other parameters (SCE, DIBL, SS, Ioff, Igate,off, etc)

are however at their maximal tolerable values This prevents further scaling down

Also Variability and Speed of the technology suffer from


these border-line values

Therefore other solutions, breakthrough like, will have tobe considered to pursue scaling

We will first explain Variability and Impact of DIBL on

performance, and next Consider more robust device structures enabling further

scaling


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Tutorial 15 :

64


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Ex. 1

Derivation of the threshold voltagefluctuation model


65

its discussion

Vth random dopant # fluctuations


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T. Skotnicki & F. BoeufT.

Skotnicki

After: T. Skotnicki et al. Innovativematerials, devices and CMOStechnologies for low-power mobilemultimedia, pp. 96-130, IEEETED, Jan. 2008

Vth random dopant # fluctuations


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20

30

deviation(mV

)with pockets

without pockets

0.12 m0.17 m0.25 m0.5 m

STRONG CHANNEL DOPING (e.g. POCKETS)

ENHANCES Vth FLUCTUATIONS

=> UNDOPED CHANNEL WITH MID-GAP GATE(ON THIN FILM SOI/SON) MAY BE A REMEDY


T.

Skotnicki

0 2 4 6 8

0

10

1 1/ ( / )WL m

VthStandard

REF.: T. Cochet, T. Skotnicki et al., ESSDERC99


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Fluctuations IMPACT ONLOGIC and on SRAM


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SNM w/o process spread

MicroelectronicsJournal 36 (2005)789800Huifang Qin

LWA

LWT

NqV vtox

ox

dcs

th

112

0

4 3

0

=


SNM with process spread

Courtesy Prof. A. Asenov


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The statistical distribution of Vt is narrow with Nominal MOSFETs


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39 mV

The statistical distribution of Vt is large with Scaled Down MOSFETs


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74 mV


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Tutorial 16 :

74


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Ex. 1

Analysis of SRAM SNM (Static NoiseMargine) in function of Vdd (supply


75

LP IS DIFFICULT


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VDD=1.1V1.0

1.2

VDD=1.1V1.0

1.2

VDD=0.9V1.0

1.2

VDD=0.9V1.0

1.2

VDD=0.7V1.0

1.2

VDD=0.7V1.0

1.2

The SNM (Static Noise Margine) vanishes when lowering the Vdd,Thus preventing correct voltage scaling ! As a result the Vdd hasbeen stagnating in LP technologies around 1.1V (see next slide).


0.0

0.2

0.4

0.6

.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vin (resp. Vout)

Vout(resp.

Vin)

0.0

0.2

0.4

0.6

.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vin (resp. Vout)

Vout(resp.

Vin)

0.0

0.2

0.4

0.6

.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vin (resp. Vout)

Vout(resp.

Vin)

0.0

0.2

0.4

0.6

.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vin (resp. Vout)

Vout(resp.

Vin)

0.0

0.2

0.4

0.6

.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vin (resp. Vout)

Vout(re

sp.

Vin)

0.0

0.2

0.4

0.6

.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vin (resp. Vout)

Vout(re

sp.

Vin)

After: T. Skotnicki et al. Innovative materials, devices and CMOS technologies for low-power mobile multimedia, pp. 96-130, IEEE TED, Jan. 2008

VARIABILITY IS BEHIND THE VDD CLUMSY SCALINGAND THUS BEHIND THE POWER CRISIS


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Evolution of VDD (LSTP)

3

3,5

44,5

5

5V plateau

10 years of constant-field scaling

from 5V to 1.2V (x 0.7 per node)


T.

Skotnicki

0

0,5

1

1,5

2

2,5

1980 1992 1995 1998 2000 2002 2004 2007 2010 2015

Year of production (ITRS)

Volt

1.2V plateau

120 90 65 32250350700 45

1.1V

500 180

~1V plateau ???

CALCULATING THE EFFECT OF VANISHING SNM WITH MASTAR (1)


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Ex. 2

Analysis of SRAM SNM (Static NoiseMargine) in function of the cell size


80


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Nominal

dimensions



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All

dimensionsScaled byX0.7



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All

dimensionsscaled againby X0.7

SOLUTION FOR ENABLING FURTHER SCALING


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LWA

LWT

NqV vtox

ox

dcs

th

112

0

4 3

0

=

If L and W are scaled X0.7 for

Vth CONST


each CMOS generation, theAvt has also to be improved

X0.7 in order to maintain the

voltage fluctuation constant

Avt ~ X0.7 or -30% per node

Avt reduction is very difficult with Bulk


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Conflict with electrostatics whenL shrink

Conflict when Area shrink

Conflict with cell-leakage


P. Stolk at al., T-ED 1998 (NXP)

Two solutions appear:

1) Tox conflict with cell leakage can be alleviated when using HK

dielectrics

2) N conflict with electrostatics can be removed when going to FDSOI

or FinFET


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Ex. 3

Analysis of Vmin (SRAM sustainingvoltage) comparison between doped


87

(FDSOI)

SRAM: Minimum Operating Voltage

SRAM: Minimum Operating Voltage


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2005 2007 2010 2013 2016 2019Tolerable Die Fail 0.0001 0.0001 0.0001 0.0001 0.0001 0.0001

Memory Size(Mbits) 8 16 32 64 128 256

Tolerable Bit Fail 1.25E-11 6.25E-12 3.13E-12 1.56E-12 7.81E-13 3.91E-13

Required SNM/SNM 6.8 6.85 6.95 7 7.15 7.25


Vmin reduction

Ref : Denis Flandre UCL Louvain La Neuve BE

LESS VARIABILITY W. SOI - EXPLANATION:


89/132

Ref.: Denis Flandre, UCL Louvain-La-Neuve, BE


Vt(SOI)/ Vt(Bulk)

=(NaSOI/NaBulk)1/4

=(1/100)1/4

1/3

X100 reduction in doping corresponds to X3 reduction in Vth or in Avt !!!

5

6

Variability and LP SRAM:


90/132

BULK

Avt ~ 3.3Vdd,nom=0.9V

0

1

2

3

4

0 1 2 3 4 5 6 7 8

(.)

()

World record by LETI !

O. Weber et al. IEDM 2008 (LETI)

Data : F. Buf


0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.

0.5

1

1 1.2 1.4 1.6 1.8 2

()

(.)

FDSOI

Vmin~0.6VBulk

Vmin~0.75V

FDSOI/UTBOXAvt ~ 1.4

Vdd,nom=0.9V

Bulk: Avt = 2FDSOI: Avt = 1.4

CONTINUITY OF SRAM SIZE SCALING:


91/132


F. Buf, 2009 VLSI SC


92/132

Tutorial 17 :

92

EffectiveEffective CurrentCurrent ((IeffIeff) as) as metricmetric of speedof speed(performance)(performance)SWITCHING TRAJECTORY WHEN CHARGING /DISCHARGING THE LOAD

I


93/132

VDD

4

3

2

5

2

0

34

5

1 2

2

0

IDN VGS=VDD2

Ion is NOT a speed indicator

ddload

eff

VC

Ispeedswitching


IN OUT

CL

7

Vdd

Ref.: M.H. Na et al., IEDM 2002, p.121.

VDSVDD/2

VGS=VDD/2

0

VDD

IeffIS A GOOD SPEED INDICATOR

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

==+

===

2;;

22

1 ddDddGddD

ddGeff

VVVVIVV

VVII

Example of CHARGING

HOW DOES DIBL IMPACT PERFORMANCE (Ieff)

Long channel


94/132

-

-

SCE Short Channel EffectSCE


- SCE

DIBL

Vds

DIBL Drain Induced Barrier Lowering

channel

same Ionsame I

PERFORMANCE (IEFF)PERFORMANCE (IEFF) dependsdepends on DIBLon DIBL NEW !!!NEW !!!

Vth


95/132

same Ionsame IoFF IDVddTechno w/o

DIBL

Techno w.DIBL

V /2

Vth

Vth-DIBL


VdVdd/2 Vdd

Ieff w.DIBL< Ieff w/o DIBL

Vd

Technow/o DIBL

Technow. DIBL

= dthgdD VVVVI

2

1


96/132

Ex. 1

Compare Ieff (speed) between twotechnologies having same Ion and Ioff



97/132


98/132

Tutorial 18 :- g mo y c anne s

98

DESCRIPTION

Better mobility and higher limiting velocity lead


99/132

Better mobility and higher limiting velocity leadto an increase in the transistor Ion current

However, lower density of states in the inversion

layer (larger Dark Space) leads to reducedinversion density, and realaxed SS, SCE and


Also the higher dielectric constant of III-Vmaterials lead to an increase in SS, SCE andDIBL

Only making a sum of these constructive anddestructive effects permits to assess the realinterest of III-V channel materials

99


100/132

How do & Dark Space impact

DIBL and SS in III Vs (1)


101/132

DIBL and SS in III-Vs (1)

DS

depinvjSi VL

T

L

T

L

XDIBL

+=

2

2

180.0

Tinv=Tox+DS.ox/s

B

DSidep

qNT

2=


eee

( )

+

+++=

d

DS

el

dep

el

j

el

inv

ox

Si

dep

inv

ox

Si V

L

T

L

X

L

T

T

T

q

kTSS 1

4

31110ln

How do & Dark Space impact

DIBL and SS in III Vs (2)


102/132

250

300

350

400

)

+3 (+25%)+6.5 (+5%) ()

11 0

12 0

13 0

)

(+%)

+.

DIBL and SS in III-Vs (2)


(b)0

50

100

150

200

10/ 100/ 2/

(

()

60

70

80

0

10 0

(

(+%

()

(b)


103/132

Ex. 1

Estimating impact of constructiveeffects on III-V MOSFET speed


103

Inspite of higher mobility, III-V may be slower !


104/132


X10 VsatX3

DIBLX2

SSX1.3

Readjust gateworkfunctionto same Ioff

X10

VsatX3

DIBLX2

SSX1.3

Readjust gateworkfunctionto same Ioff

NegativeImpact

on speed

PositiveImpact

on Ion

CONCLUSIONS At low Vdd the impact of bad electrostatics is particularly

strong


105/132

g

III-V materials present very good transport properties,but much relaxed electrostatics (DIBL and SS)

At nominal transistor length and low Vdd, the destructiveeffects, due to electrostatics, preveil over the


,

Consequently, the overall impact of the replacement ofSilicon by III-V materials may be negative in terms ofspeed

Still remains true, that lagging the transistor length one

node behind nominal permits higher speed than Bulk(see biblio, next slide), but leads to lower density ofintegration

105

Bibliography

How Can High Mobility Channel Materials Boost or DegradeP f i Ad d CMOS T Sk t i ki d F B f


106/132

Performance in Advanced CMOS T. Skotnicki and F. Boeuf,STMicroelectronics, France, Digest of Tech. Papers. Symposium onVLSI Technology 2010 (IEEE CAT No CFP**VTS-PRT), pp.TBD



107/132

Tutorial 19 :

-

107

DESCRIPTION

FDSOI especially with thin BOX shows much improvedSCE DIBL d SS


108/132

SCE, DIBL and SS

Such a FDSOI on thin BOX is also called UTBB (Ultra

Thin Body and BOX) SOI


and benchmark it against BULK using MASTAR

We will also show how to transform the Bulk transistorcurrent model into a model valid for UTBB SOI

Comparison of current and invertor speed (via Ieff) will becarried out with MASTAR for Bulk and UTBB SOI

108


109/132

Ex. 1

WHY DOES UTBB SOI BETTER THANBULK IN TERMS OF ELECTROSTATICS ?


109

FDSOIFDSOI devicesdevices on SOI Waferson SOI Wafers


110/132

K. Cheng et al., VLSI 2009 (IBM)

Krivokapic et al., IEDM2002(AMD)

M. Fujiwara et al., IEEE SOIConference 2005 ( Toshiba)

C. Fenouillet-Beranger


N.Sugii et al., IEDM 2008 (Hitachi)

SOTB

DST

R.Chau et al., IEDM 2001(Intel)

Hybrid FDSOI

C. Fenouillet-Beranger et al., IEDM 2009(ST/LETIl)

e a ., unpu s e(ST/LETIl)

0.

FDSOI BULK

TTX

2

WHY DOES THE PLANAR MOSFET FAIL ?(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N3, 1998)


111/132

DS

el

dep

el

ox

el

j

ox

Si VL

T

L

T

L

XDIBL

+=

2180.0


REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Gr

Tdep=1/2Lg

Xj=1/2Lg

mVV 14014

3

20

1

4

314.2

2

2

=

+

TTX

2

WHY DOES THE UTB SOI/SON DO BETTER ?(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N3, 1998)


112/132

DS

el

dep

el

ox

el

j

ox

Si VL

T

L

T

L

XDIBL

+=

2180.0

Xj=Tsi

Tdep=Tsi


REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group

mVV 7512

1

20

1

2

114.2

2

2

=

+

Xj=Tsi=1/3Lg

Tdep=Tsi=1/3Lg

BUT Tdep=1/3Lg is ONLY arough simplification. Inreality BOX thickness also

contributes to the effectiveTdep, see next slide =>

80

90NMOS FDSOI

Tox1nmVdd1V

ElectrostaticsElectrostatics of UTB SOIof UTB SOIT. Skotnicki et al. IEEE EDL, March88 & IEDM1994

XjTdep TTX

2

C.Fenouillet-Beranger, et al., SOI Conference 2003


113/132

20

30

40

50

60

70

80

DIBL

(mV)

Tox 1nm Vdd 1V

Tsi 5nm Lg 30nm

Lg 40nm

dep

Bulk

Sij TX

DS

el

dep

el

ox

el

j

ox

Si VL

T

L

T

L

XDIBL

+=

2

2

180.0


0

10

0 20 40 60 80 100 120 140 160Tbox(nm)

Open symbol: MASTAR

TBOX

SiboxSidep +

box

el

el

box

el

box

T

L

L

T

L

Ttgh

+

+= 09.01150.1121.0

UTB DS

el

boxSi

el

ox

el

Si

ox

Si VL

TT

L

T

L

TDIBL

+

+=

2

2

180.0

For Tbox in therange of 10-50nm, 0.3

COMPARE BULK LAST POINT (HK and pockets) WITH FDSOI


114/132

Bulk our last


114

Note huge DIBL !We will pass to FDSOI making thefollowing changes (next slide):

1) Replace Xj by Tsi (suppose 6nm)2) Replace Tdep by Tsi+0.3Tbox

(suppose Tbox=10nm)

optimized point(HK and pockets)

WE CAN MIMIC FDSOI MODIFYING BULK PARAMETERS:


115/132

Tsi is set to 6nm, thus


115

Note improvement in DIBL !

Tdep=9nm (=Tsi+Tbox

=6nm+0.3x10nm) is obtained byartificially increasing the doping Nbulkand readjusting Workfunction

USING BUTTON TECHNOLOGY FLAVORS !

For convenience of use, all these and other changes

i i t i i i th FDSOI b h i ith th B lk


116/132

aiming at mimicing the FDSOI behavior with the Bulk

models, are already programmed in MASTAR

The modifications are sligthly more complex (see next


116

s e an ca rate on exper menta ata

Nevertheless, pushing the button SOI gives results

similar to what we have obtained manipulating the Bulk

model manually

See next slide


117/132

FDSOI USING BUTTON TECHNOLOGY FLAVORS !


118/132


118

Bulk

FDSOIBy press button SOI

FDSOIBy manual parameter manipulation

E


119/132

Ex. 2

INVERTOR SPEED COMPARISON BULKAND FDSOI


119


120/132

E 3


121/132

Ex. 3

INVERTOR SPEED FDSOI with ForwardBody Bias


121

FinFETs INCOMPATIBILITY W. BODY-BIASwhereas FDSOI with thin BOX is !

FDSOI = 2D FinFET w.COMMON GATE

FinFET w.

SEPARATE GATESLOST ADVANTAGEIN DIBL !


122/132

ate

drain

Thin Silicon film

IN DIBL !

drain

Lg


source

Body-BiasAs on Bulk

Body-BiasSince

GATE=BACK-BODY

source

Lg

Body-Bias

SinceGate(N+1)=Body(N)

And NO ROOM for CONTACTS

Fin1 2 3 4

SPEED IMPROVEMENT WITH FDSOI and ForwardBody Bias !


123/132

FDSOI 340


123

FDSOI (directly afterpush button SOI and adjusting Tsi)

FDSOIAdjusted tosame Ioff as Bulk

BULK

+82% in Ieffmeans +82%

in speed

ddload

eff

VC

Ispeedswitching

FDSOIAdjusted tosame Ioff

FDSOIw. FBB

.

BULK


124/132

Tutorial 20 :

- n

124

DESCRIPTION

DG structures (eg FinFET) show much improved SCE,DIBL and SS


125/132

We will explain why DG/FinFET shows better

electrostatics


current model into a model valid for DG/FinFET

Comparison of current and invertor speed (via Ieff) will becarried out with MASTAR for Bulk and DG/FinFET

125

DOUBLE GATE DEVICES:

Gate

Gate

Gate


126/132

Source DrainSource DrainSource Drain

n+

SOURCE

GATE

DRAIN

n+ n+

SOURCE

GATE

DRAIN

n+

Tied gates(number of

channel > 2)

Tied Gates side-wallconduction: DELTA,


126

STISi-substrate STISi-substrateTRIGATE, ,

Tied gates planarconduction: DGSON

Independentlyswitched gates

planar conductionVertical

conduction

SOURCE

FinFET - STATE OF THE ART

FinFETDrain


127/132

Source


CPP FinPitchIBM Allience ,Albany 2010

FinFET structure in a dense array withCPP=80nm and Fin pitch = 50nm

DSdepoxjSi V

TTXDIBL

+=

2

1800

WHY DOES THE Double-Gate DO BETTER ?(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N3, 1998)


128/132

DS

elelelox

VLLL

DIBL

+=2

180.0

Xj=1/2Tsi


REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group

mVV 3214

1

20

1

12

314.2

2

2

=

+

Tdep=1/2Tsi

Xj=1/6Lg

Tdep=1/6Lg

TECHNOLOGY FLAVORS-TRANSLATION TO MASTAR:


129/132


Ex 1


130/132

Ex. 1

INVERTOR SPEED COMPARISON BULKAND DG/FinFET


130

SPEED IMPROVEMENT WITH FinFET !


131/132

275186.5


131

+47% in Ieff

means +47%in speed whenpassing from

BULK toFinET !!

ddload

eff

VC

Ispeedswitching

FinFET (directly after

push button DG )

FinFET

Adjusted tosame Ioff

FinFET

Adjusted tosameIoff

CONCLUSIONS (FDSOI & DG/FinFET)

FDSOI as well as DG structures (eg FinFET) show muchimproved SCE, DIBL and SS


132/132

These features lead to very strong performance

improvement, aspecially at low Vdd (Low Powerapplications)


132

Without Body Bias, FinFET gives larger improvement

than FDSOI due to better electrostatics

But FinFET is not compatible with Body Bias, whereasFDSOI is and provides better Body Factor than Bulk

Therefore with Forward Body Bias, FDSOI gives evenbetter speed than FinFET !

idesa cmos physics using mastar part 2of2x

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