idec journal of integrated circuits and systems...

Volume 3 · Number 2 · April 2017ISSN -2384-2113 (Online)

Volume 3 · N

umber 2 · April 2017

A 10-Gb/s programmableand flexible transceiverwith a FPGA

IDEC Journal of Integrated Circuits And Systems

jicas.idec.or.kr

jicas.idec.or.kr

IDEC Journal of Integrated Circuits and SystemsVolume 3 · Number 2 · April 2017Date of Publication April 1, 2017 Printed by Simwon401, 12, Munjeong-ro, Seo-gu, Deajeon, Republic of Korea

IC Design Education Center (IDEC)291 Daehak-ro, Yuseong-gu, Daejeon, 34141, Republic of KoreaTel. +82-42-350-8535 / Fax. +82-42-350-8540

IDEC Journal of Integrated Circuits A

nd Systems


IDEC Journal of Integrated Circuits And Systems is published in every quarter by the IC Design Education Center. Responsibility for the contents rests upon the authors and its members, not upon the IDEC.

Editorial Correspondence

_

IDEC Journal of Integrated Circuits andSystems is subject of results of researchfrom support of MPW by IDEC.

_

Authors will be asked to submit theirmanuscript online.

_

For more information, refer toinstruction for Authors at the JICAS website. (jicas.idec.or.kr)

Editorial Assistant

_

Haneul Kim(IC Design Education Center)291 Daehak-ro, Yuseong-gu, Daejeon,34141, Republic of KoreaTel : 82-42-350-8535Fax : 82-42-350-8540E-mail : [email protected]


jicas.idec.or.krVolume 3 · Number 2 · April 2017

jicas.idec.or.kr


Editorial Board

Editor-in-Chief_

In-Cheol [email protected]

Associate Editors_

Jaeha KimSeoul National [email protected]

_

Chulwoo KimKorea [email protected]

_

Byeong-Gyu NamChungnam National [email protected]

High-speed WAVE Security ChipPiljoo Choi, Hyun Il Kim, Ryang Ki and Dong Kyue Kim_

P. 25

A 10-Gb/s programmable and flexible transceiver with a FPGAHan-ho Choi, Youn-ho Jeon, and Hyeon-min Bae_

P. 01

A Patch-Clamp for detecting the DNA passageYoung Sun Moon and Gyu-Tae Kim_

P. 31

Two-Stage Distributed Amplifierand Cascaded Single-Stage Distributed Amplifierin 65nm CMOS ProcessSeongbin Kang, Yunsik Na and Munkyo Seo_

P. 08

High-efficiency analog front-end design of passive NFC tag based on 65nmJun-Beom Jang and Yong Moon_

P. 36

A CMOS Micro Array DNA Biosensor with an On-chip Controlled Electrolyte Electrochemical Potential RegulatorJun Yeon Yun, Jinhong Ahn, Nakwon Yoo, and Young June Park_

P. 13

16-PSK baseband Modem Design for Data CommunicationNam-Won Kim and Myoung-Seob Lim_

P. 19

1-13GHz Wideband LNA utilizing a Transformer as a Compact Inter-stage Network in 65nm CMOSHyohyun Nam and Jung-Dong Park_

P. 44

IDEC Journal of Integrated Circuits And SystemsVolume 3·Number 2·April 2017

CONTENTS

jicas.idec.or.kr

C1 C2

IDEC Journal of Integrated Circuits and Systems, VOL 3, No. 2, April 2017 http://www.idec.or.kr

Abstract – Digital design automation software tools have been very successful in achieving performance gains over the past 50 years as system IC density continues to increase. As the design of these mixed signal systems increases, the simulation time for verifying new algorithms becomes a significant part of overall system development time. However, it cannot be accurately verified using existing verification tools. In this thesis, we propose a programmable and flexible 10Gb/s transceiver that is a structure in which all the analog blocks that can be reused are implemented in the IC and the digital blocks that have always been a problem due to the difficulty of verification are implemented in the FPGA as a verification tool of mixed signal systems.

I. INTRODUCTION

Most modern high-speed serial links are designed with analog blocks and synthesized digital blocks. In other words, mixed-signal system design is dominant. The main reason for the mixed system design is that the digital control block is designed and synthesized using VHDL language, which makes it much easier to design a complex digital system than to design it using full-custom. Based on these advantages, various digital functions are integrated in the IC to control the entire system. Examples of synthesized digital blocks include digital loop filters, controllers, and calibrators.

However, as the design of mixed-signal systems are caused by the system level functionality offered by synthesized digital blocks.

Most of operational issues of mixed signal systems are caused by the system level functionality offered by synthesized digital blocks. If there is a problem in the system level functionality of synthesized digital blocks caused by the lack of verification, the entire system often behaves erroneously. On the other hand, analog blocks can only be reused without major problems by adjusting only small tweaks of existing blocks most of the time.

These problems are caused by the limitation of the method of verifying mixed-signal systems. Currently, there is no system-level simulation methods that can accurately and quickly verify mixed-signal systems. The actual operation of the chip is done in seconds, because we can only test micro seconds using existing simulation tools.

Therefore, most of them are verified using only matlab or verilog level simulation, so the BER can only be confirmed at the level of , which is an uncertain verification method. For these reasons, there are problems with various functionality issues in the operation of the actual chip.

To solve these problems, the proposed solution is a design of a programmable and flexible transceiver. The mixed signal system consists of a few analog blocks and synthesized complex digital blocks.

II. EXPERIMENTS

A. System Architecture The overall structure and operation of a circuit design is

shown in Fig. 1. Basically, the circuit design is implemented in the analog blocks required for the High speed serial link, that is, the basic TRX for the transmission and reception of 10Gb/s data. In the FPGA, there are synthesized digital blocks, which can control basic analog TRX blocks using the data coming from the chip.

Fig. 1. Example of a chip-FPGA communication

a. Corresponding author; [email protected]

Copyright ©2017 IDEC All rights reserved. This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

A 10-Gb/s programmable and flexible transceiver with a FPGA

Han-ho Choi, Youn-ho Jeon, and Hyeon-min Bae Department of Electrical Engineering,

Korea Advanced Institute of Science and Technology (KAIST) E-mail : [email protected]


As a result, the high speed serial transmission is executed through the connection of the chip and the FPGA. A 10Gb/s data is sampling, retiming, demuxing in the chip and enters the FPGA.

The FPGA sends out a signal to control the internal blocks of the chip using the received data. Then, the data is sent back to the TX of a chip from a FPGA, and the TX of a chip is muxing them to transmit serial data to 10Gb/s. As a result, the high speed serial transmission is executed through the connection of the chip and the FPGA. B. Transceiver Architecture

The proposed transceiver as shown in Fig. 2 is configured through a connection between the proposed IC(LEGO chip) and the FPGA. The proposed IC implements basic analog blocks for operation as a 10Gb/s transceiver. Each block of the proposed IC transmits necessary information to the FPGA to implement various digital functions.

In addition, the proposed IC can be a stand-alone 10Gb/s transceiver. The proposed IC has receiver, transmitter, clock generator and digital blocks needed to form a closed loop within the IC, enabling it to operate as a stand-alone 10Gb/s transceiver.

In the FPGA, any digital functions can be implemented based on the information provided by the proposed IC.

EQ & LA

2.5GHzRX

Phase Rotators

CML Divder & C2C

DFE & CDR Logics 4:64

Output Driver

64:4 4:1

FFE

DIV

10Gb/sData In

10Gb/sData Out

DIVTX

Phase Rotators

PI

VCOBB

PFD

DIV

From Chip to FPGAFrom FPGA to Chip

REF CLK

DLF

Control signal

receiver transmitter

Programmable & flexible

Information

clock generator

Fig. 2. Top Architecture of the transceiver. C. Receiver Architecture

The receiver consists of analog blocks for generation information to send to the FPGA. Fig. 3 shows the block diagram of a 10Gb/s RX, which consists of a continuous-time linear equalizer(CTLE), a limiting amplifier(LA), CML divider and CMOS divider for SRCG, CMOS quadrate samplers with a one-tap loop-unrolled decision feedback equalizer(DFE), a retime, a 4:64 de-multiplexer(DEMUX), a synthesized CDR logic block for making a closed loop within the IC, and a phase-rotator-based multiphase clock generator(CML divider, Harmonic Rejection Poly Phase filter, Phase rotator, Phase interpolator(PI)).

The CTLE and LA recover the data damaged by channel loss. CMOS quadrate samplers with a one-tap loop-unrolled decision feedback equalizer sample 10Gb/s data. The DEMUX and re-timer convert 10Gb/s serial data into 156.25MHz parallel data to meet the maximum operating speed in the FPGA. The phase rotator adjusts the phase of multiphase clocks and samples the data.

As the result, as shown in Fig. 4, the receiver transmits various information generated by analog blocks such as de-multiplexed data and edge, divided data for SRCG, and the system clock for the operation of digital functions in the FPGA, which is processed by the FPGA and used to implement various digital functions.

LAEQ

LA Output

CML Divider

CML to CMOS

INP INNSRCG

44

CMOS Divider

PI

PI

PI

C2C

C2C

C2C

0

90

180

PI

PI

PI

C2C

C2C

C2C

270

45

135

4

α

-α

Post-tap

Next-tap

X 4

Sampler & DFE

Retimer & DEMUX

Data

Edge

45

0,90,180,270

FIFO

+CDR

Logics

Data

DIN(10Gb/s)

DOUT(156.25MHz)

Edge

RXAcc.

From FPGA

On-

chip

T-li

ne

(5G

Hz D

iffer

entia

l Clo

ck)

From chip to FPGA

Fig. 3. The Architecture of the receiver.

LA

VCORx PR Tx PR

FFEDEMUX MUX

FPGA

EQ Driver10Gb/sData In

Receiver

Fig. 4. The Overview of the communication between the receiver and the FPGA.

LA

VCORx PR Tx PR

FFEDEMUX MUXEQ Driver10Gb/sData In

Receiver

CDRLogics

RXAcc

FIFO

Fig. 5. The synthesized digital block in the receiver.

As shown in Fig. 5, simple digital blocks(CDR logics block) are synthesized in the receiver to form a closed loop in the IC and to operate as a stand-alone 10Gbps transceiver. A CDR logic and accumulator based on a Nyquist rate BBPD are used for phase lock and A FIFO transmits the parallel data to the transmitter in the IC.


D. Transmitter Architecture The transmitter transmits 10Gb/s data by serializing 64

parallel data processed at the FPGA. Fig. 6 is the block diagram of the 10Gb/s TX. The TX consists of a 64:4 MUX implemented in static CMOS logic gates followed by a tap generator, and parallel 4:1 MUXs.

64:4MUX

4:1

Ф[3:0](2.5GHz CMOS)

TXCLK(10G/64MHz)

4

Div.

Pre-tap

pre

4:1

4:1 post

OutputDriver

DOUT(10Gb/s)

4

4

464

DIN(156.25MHz)

4 4

CurrentSumming

/2, /4, /8

Tap Data Gen.

Z-1

Z-1

Pre

Main

Post

Main-tap

Post-tap

Vdrv

1

44

4

C2C + PI

C2C + PI

Ф[0]Ф[1] 4Ф[2]Ф[3]

Clock Phase Shifter

C2C + PI

C2C + PI

DFPGA(From FPGA)

64

2 CLK(5GHz)

Fig. 6. The Architecture of the transmitter.

The FIFO in the FPGA receives 64 parallel data from the receiver and transfers it to the transmitter. TX eliminates the pre-cursor ISI of data through pre-emphasis and serializes it to transmit the 10Gb/s data. That is, it acts as a transceiver through the receiver-FPGA-transmitter.

LA

VCORx PR Tx PR

FFEDEMUX MUX

FPGA

EQ Driver

Transmitter

10Gb/sData Out

Fig. 7. The overview of the communication between the transmitter and the FPGA.

E. FIFO Architecture

Fig. 8. The Architecture of the FIFO.

Fig. 8 is the block diagram of the FIFO. Any digital

functions can be implemented in the FPGA. Each function is implemented by receiving the necessary information from the IC to implement it. For example, FPGA has digital blocks that control internal analog blocks in the IC, such as a phase rotator controller, Digital loop filter to control VCO, and Jitter-suppression loop for SRCG. Alternatively, digital

functions for testing the performance of IC, like PRBS Generator/Checker, PRBS-based random generator can be implemented in the FPGA.

Basically, each digital function in the FPGA should serve to transmit control signals to the IC after they are processed data form the IC.

F. Examples of the digital functions in the FPGA

LA

VCORx PR Tx PR

FFEDEMUX MUX

FPGA


10Gb/sData Out

data

/edg

e

Fig. 9. Implementation of the phase rotator controller. Fig. 9 shows the implementation of the phase rotator

controller. The controller of phase rotators in the IC is implemented in the FPGA. The implementation process is as follows.

The de-multiplexed data and edge samples enter the phase rotator controller of the FPGA from the receiver of the proposed IC. They are provided to the CDR logic in the controller of the FPGA to accomplish single-edge-sensitive bang-bang phase detection. Then, control signals are generated by controlling the phase of phase rotators in the digital domain through accumulation and truncation. Consequently, control signals are transmitted from the FPGA to the IC to control phase rotators. That is, the loop bandwidth of the receiver and transceiver can be adjusted in the digital domain through the phase rotator controller in the FPGA.

LA

VCO

Rx PR Tx PR

FFEDEMUX MUX

FPGA


10Gb/sData Out

BBPFD

/N

Reference Clock

Fig. 10. Implementation of the digital loop filter in the Clock Generator.

Fig. 10 shows the implementation of the digital loop filter

(DLF) for adjusting the frequency of the VCO. The CG DLF is composed of digital low-pass filter with adder, accumulator and dithering algorithm. The implementation process is as follows.

The frequency difference between the reference clock and the VCO clock is entered into the DLF in the FPGA through BBPFD in the clock generator of the IC. The accumulator in the DLF continues to accumulate frequency errors, of which 6 MSBs are used to coarse tuning the VCO frequency. Fine


tuning signals are composed of binary and thermometer codes to reduce the silicon area while minimizing the switching glitch.

Control bits in the DLF, which cannot be changed through a simulation, can be changed freely in the DLF implemented by the FPGA. Therefore, it is possible to check in real time how the frequency of VCO is adjusted accordingly.

LA

VCORx PR Tx PR

FFEDEMUX MUX

FPGA


10Gb/sData Out

data

/edg

e

PRBSChecker

PRBSGenerator

PRBS-basedRandom

Generator

Jitter Injection

Fig. 11. Implementation of the Jitter tolerance self-test. Fig. 11 shows the implementation of jitter tolerance

(JTOL) self-test. JTOL self-test is possible by implementing PRBS Generator, checker, and PRBS-based random generator in the FPGA. The implementation process is as follows.

The transmitter in the IC sends jitter-free 10Gb/s data to the receiver in the IC through the PRBS Generator in the FPGA. A PRBS-based random generator in the FPGA injects jitter into the phase in the receiver of the IC. The phase rotator in the receiver tries to filter out the injected accumulation jitter and align the output clock signal with the jitter-free transceiver output data. Then, The output clock of the RX phase rotator samples the data and sends it to the PRBS Checker in the FPGA to verify BER. Consequently, we can measure JTOL of the IC by adjusting the amount of jitter injected from the PRBS -based random generator in the FPGA.

It is possible to verify the performance of the IC accurately and quickly by implementing the JTOL self-test in the FPGA that can hardly be verified in the simulation due to take too long. G. FPGA Interface

The maximum speed that can be operated within the FPGA must also be considered to implement various digital functions in the FPGA. In order to determine the maximum clock speed of the digital function to be implemented in the FPGA according to the maximum operating speed of the FPGA, a simulation tool of the FPGA, STRATIX V was used for testing.

The maximum operating speed of the FPGA was 177.4MHz as a result of checking with the phase rotator controller which has the longest cycle among control schemes used in our lab. Fig 20 is the result of the test.

Based on result shown in Fig. 12, the speed of the system clock(156.26MHz) to be sent to the FPGA inside the IC and the speed of the de-multiplexed data (10G/64, 156.25MHz) were determined to ensure accurate design.

Fig. 12. The result of the test for determining the maximum operating speed in digital functions.

III. RESULTS AND DISCUSSION

A. Simulation setup The proposed transceiver operates by communicating

with the IC and the FPGA. Fig. 13 is a simulation setup to verify exact communication between the IC and the FPGA through the LVDS interface.

Fig. 13. Simulation setup.

The first step is to verify that the information is sent to the

FPGA through the LVDS transmitter of the IC, and that the information is forwarded to the synthesized digital block exactly through the LVDS receiver of the FPGA.

The second step is to verify that control signals generated by the synthesized digital block are forwarded to the IC through the LVDS transmitter of the FPGA, and that control signals accurately control the target block in the IC through the LVDS receiver.

As a result, simulations were performed to verify that various digital functions implemented between the FPGA and IC were correctly operated through the LVDS interface.

B. System verification

PRCONin chip

PRCONin FPGA

Data(64)Edge(32) FPGA ON

α

-α

Post-tap

Next-tap

X 4

Sampler & DFE

Retimer &

DEMUX

Data

Edge

45

0,90,180,270

NRZ dataGen

Vin_CLK(10G)

PIC2C0,90,180,270,45,135

X 6

2.5GHz CLK

(1)

(2)

Fig. 14. The simulation for phase lock. Fig. 14 shows the result of a simple simulation to verify

the proposed system. I implemented the phase rotator controller in the FPGA and confirmed that the phase lock of the proposed transceiver is correct.

In order to meet the actual operating environment, the setup is as follows. De-multiplexed data/edge samples in the IC are transmitted to the FGPA through the LVDS transmitter, and then, the LVDS receiver of the FPGA receives these data/edge samples and controls the phase rotator through the phase rotator controller.


1u

Time(s)2u 3u 4u 5u

Number

400

200

511

0

1st order loop

(a) 1u

Time(s)2u 3u 4u 5u

Number

400

200

511

0

2nd orderloop

(b)

Fig. 15. (a) 1st order loop coefficient. (b) 2nd order coefficient. Fig. 15 shows the result of the phase lock simulation. It

can be seen that a coefficient of the 1st order loop converges to a specific value by phase lock between the FPGA and the IC as shown in the Fig. 15 (a).

In addition, even if there is a frequency offset, the frequency offset is removed by the 2nd order loop as shown in the Fig. 15 (b), so phase lock can be confirmed.

EQ & LA

2.5GHzRX

Phase Rotators

CML Divder & C2C

DFE & CDR Logics 4:32

Output Driver

4:1

FFE

DIVDIVTX

Phase Rotators

PI

Receiver Transmitter

FIFO

FPGA

Global Clock

NRZ dataGen

Vin_CLK(10G)

TX Output

Global Clock

Fig. 16. The simulation for verifying operation of the proposed transceiver.

Fig. 16 shows another result of a simple simulation to

verify the proposed system. This is a simulation process to verify that the proposed transceiver with the combined IC and FPGA operates correctly.

It is simulated to verify that the 10Gb/s NRZ data coming into the IC is transmitted correctly through the receiver of the IC, the FIFO of the FPGA, and the transmitter of the IC.

Fig. 17. The output eye diagram of the TX output. Fig. 17 is the eye diagram measured by the simulation. It

was simulated at TT, 27 degrees, 1V corner. The eye diagram shows that the voltage swing is 678mV and the deterministic jitter is 2.1ps, which means that that the data is transmitted accurately with very little noise through the proposed transceiver.

Fig. 18. The output eye diagram of the TX output.

Fig. 18 is the layout of the proposed transceiver. It was

designed with a 65nm process and used a 1V supply voltage. The proposed transceiver includes one TRX lane targeting

10Gb/s data rate. As shown in the Fig. 18, a total of 336 LVDS I/Os were placed in two rows on the edge of the IC to communicate with the FPGA.

TABLE I.

Power consumption of the full chip.

65nm CMOS

1V

10Gb/s

AFE(Linear EQ + LA) 48.91mW

Datapath(Sampler + DFE + DEMUX) 12.78mW

Clockpath(CML div + PR + 9PI) 9.94mW

64:4 MUX 1.49mW

Current summer(FFE) 19.63mW

Out-driver (50ohm driver) 14.1mW

VCO 9.7mW

124.35mWTotal power

Powerconsumption

(Clock Generator) VCO buffer 7.8mW

Technology

Supply voltage

Data rate

Powerconsumption

(Receiver)

Powerconsumption(Transmitter)

Fig. 19. Test board of the proposed transceiver.

Fig. 19 shows an environment of testing our chip-FPGA

connection. We used a SPI protocol for measurement of the chip.

Fig. 20 shows its measured eye diagram at LA output using SPI control. We confirmed that the eye diagram at LA output changes as controlled.

RX W PRCON TX

CGW DLF

PRCON

SPI

DLF


Fig. 20. Eye diagram of LA output, at 2Gb/s, 5Gb/s, 10Gb/s using a SPI

Fig. 21. Phase locked VCO clock using DLF in the FPGA. Fig. 21 shows phase locked VCO clock using digital loop

filter in the FPGA. We confirmed that stable VCO clock is generated through accurate communication between FPGA and chip.

IV. CONCLUSIONS

Using the proposed transceiver, various functions can be implemented by choosing analog blocks in the IC and digital functions in the FPGA and many functions that cannot be verified at the simulation level can be verified in real time, such as Jitter tolerance self-test, Jitter peaking check, Frequency synthesizer, CDR, real-time calibration scheme.

The power consumption of the total chip is 124.35mW at 10Gbps input data and the recovered clock jitter is 2.1 and the total active area is 4 .

ACKNOWLEDGMENT

This work is supported by IDEC.

REFERENCES

[1] Hyosup Won; Taehun Yoon; Jinho Han; Joon-Yeong Lee; Jong-Hyeok Yoon; Taeho Kim; Jeong-Sup Lee; Sangeun Lee; Kwangseok Han; Jinhee Lee; Jinho Park; and Hyeon-Min Bae, "A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS," in Solid-State Circuits, IEEE Journal of, vol.50, no.2, pp.399-413, Feb. 2015.

[2] Yunju Choi; Yoontaek Lee; Seung-Heon Baek; Sung-Joon Lee; and Jaeha Kim, “A field-programmable mixed-signal IC with time-domain configurable analog blocks,” in VLSI Circuits (VLSI-Circuits), IEEE Symposium on pp. 1-2, Sep.2016.

[3] Craig R. Schlottmann; Csaba Petre; and Paul E. Haslerk, “A High-level Simulink-Based Tool for FPAA Configuration,” in IEEE Transactions on Very Large Scale Integration (VLSI) System of, vol.20, pp. 10-18, Jan.2012.

[4] C. Steiger; H.Walder; and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” in IEEE Transactions on Computers of, vol.53, no.11, pp. 1393-1407, Sep.2004.

[5] B. Razavi, “Challenges in the design high-speed clock and data recovery circuits,” in IEEE Communications Magazine of, vol.40, no. 8, pp. 94–101, Aug.2002.

[6] Jinho Han; Jaehyeok Yang; and Hyeon-Min Bae, “Analysis of a frequency acquisition technique with a stochastic reference clock generator,” in IEEE Transactions on Circuits and Systems II: Express Briefs of, vol. 59, no. 6, pp. 336–340, Jun. 2012.

[7] V. Stojanovic; and M. Horowitz, “Modeling and analysis of high-speed links,” in Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003 of, pp.589–594, Dec, 2003.

[8] Che-fu Liang; Sy-chyuan Hwu; and Shen-iuan Liu, “A 10 Gbps burst-mode CDR circuit in 0.18 m CMOS,” in Custom Integrated Circuits Conference of, 2006. CICC '06. IEEE of , pp. 599–602, Feb 2007.

[9] John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; Young H. Kwark; Sudhir Gowda; and Daniel J. Friedman, “A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90 nm CMOS technology,” in Solid-State Circuits, IEEE Journal of, vol. 41, no.12, pp. 2885–2900, Dec. 2006.

[10] T.S. Hall; C.M. Twigg; and J.D.Gray, “Large-scale field-programmable analog arrays for analog signal processing,” in IEEE Transactions on Circuits and Systems I: Regular Papers of vol. 52 of, no.11, pp.2298-2307, Nov, 2005.

[11] M. Abramovici; and C.E. Stroud, “BIST-based test and diagnosis of FPGA logic blocks,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems of, vol. 9, no. 1, pp.159-172, Feb.2001.


Han-ho Choi received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Dae-jeon, Korea, in 2015 and 2017, respectively. He is currently working toward the Ph.D. degree at KAIST.

His research interests include PLL, CDR, high-speed serial links for

optical fibers and high-speed memory interface.

Youn-ho Jeon received the B.S. degree in electrical engineering from Pusan National University, Pusan, Korea, in 2015 and M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Dae-jeon, Korea, in 2017, respectively. His research interests include PLL, CDR, high-speed serial links for optical

fibers and high-speed memory interface.

Hyeon-min Bae received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 1998 and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Illinois at Urbana-Champaign, Champaign, IL, USA, in 2001 and 2004, respectively.

From 1995 to 1996, he served his military duty in Dokdo in the East sea. From 2001 to 2007, he led the analog and mixed-signal design aspects of OC-192 MLSE based EDC ICs at Intersymbol Communications, Inc, Champaign, IL, USA. From 2007 to 2009, he was with Finisar Corporation (NASDAQ: FNSR), Sunnyvale, CA, USA, after its acquisition of Intersymbol Communications Inc.. Since 2009, he has been on the faculty of the electrical engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, where he is currently an associate professor. In 2010, he founded Terasquare, Inc., Seoul, South Korea, a venture-funded fabless semiconductor start-up which provided low power all digital 100 Gb/s IC solutions. Teresquare, Inc. was acquired by Gigpeak (NYSE:GIG) in 2015. In 2013, He also founded OBElab, Inc., Seoul, Korea, a bio startup that manufactures portable functional brain imaging systems. His research interests span a wide rage of topics in wireline communication and medical imaging systems.

Prof. Bae received the Excellence Award from the National Academy of Engineering of Korea in 2013 and the 2006 IEEE Journal of Solid-State Circuits Best Paper Award.


Abstract – This work presents a 2-stage distributed amplifier (DA) and a 2-stage cascaded single-stage distributed amplifier (CSSDA) in Samsung 65 nm CMOS technology. They are designed in cascode configuration to obtain broad bandwidth and high gain, and m-derived filter configuration is used for compact layout. The measurement results show a peak gain of 10 dB of 2-stage DA and 13 dB of 2-satge CSSDA with the 3-dB bandwidth from 5 GHz to 20 GHz. S11 and S22 are better than -10 dB over the entire bandwidth. The chip sizes are 720 × 540 μm2 and 580 × 450 μm2 for the 2-stage DA and the 2-stage CSSDA, respectively.

I. INTRODUCTION

Recently, as the era of Internet of Things (IoT) comes, the need for high-speed, high-capacity data transmission is increasing. The demand for broadband communication systems will continue to increase. In particular, broadband circuits are a key building block in various fields such as high-speed communication, high-frequency instrumentation devices and high-resolution imaging systems. Broadband amplifiers are an essential circuit block for such high-speed applications [1]-[3].

Distributed amplifiers have been popularly employed for broadband applications for their wideband characteristics. In this paper, distributed amplifiers in two different configurations are designed and fabricated in 65 nm CMOS, with the design emphases on low power and small chip area, for possible application to IoT devices.

In Section II, the overview of conventional distributed amplifier (DA) and cascaded single-stage distributed amplifier (CSSDA) is presented. Section III describes the design of 2-stage DA and 2-stage CSSDA. In Section IV, discussions on the measurement results are presented.

II. BACKGROUND

A. Conventional Distributed Amplifier (DA)

The bandwidth of resistively-loaded amplifiers is typically limited by gate and drain capacitance of transistors. In contrast, conventional DA uses a distributed matching technique where the input and output capacitance of a transistor can be absorbed by series inductors to form input and output artificial transmission lines, thereby providing wideband input and output impedance matching.

Fig. 1 shows the conventional structure of a distributed amplifier in common source configuration. Inductors in the input and output artificial transmission line absorb the gate and drain capacitance of the transistors. In the input transmission line, input voltage wave is travelling and generating drain voltage waves, which are eventually combined in-phase at the amplifier output terminal. The signals reflected in the opposite direction of the input and output lines generate gain ripples and degrade input and output return losses. Therefore, the input and output lines must be terminated by a resistor matched to the characteristic impedance of each line, to absorb incoming waves and thus to eliminate reflection. If the gate and drain capacitance of the transistors are Cg and Cd, respectively, the characteristic impedances of the input and output artificial transmission lines with Lg and Ld can be expressed by Equation (1) and (2) [4].



Two-Stage Distributed Amplifier and Cascaded Single-Stage Distributed Amplifier in 65nm CMOS Process

Seongbin Kang1, Yunsik Na and Munkyo Seoa Department of Electrical, Electronic and Computer Engineering, Sungkyunkwan University, Suwon, Republic of Korea

E-mail : [email protected]

Fig. 1. Schematic of conventional distributed amplifier.


The maximum gain at low frequencies is given in following Equation (3).

where n is the number of distributed stages and gm denotes the transconductance of each stage (the source impedance is assumed to be matched to Zg).

Conventional DA's exhibit wide bandwidth, high reverse isolation, and in general sufficient stability. However, due to the gate resistance of the transistors, the input line may have relatively high attenuation, resulting in amplifier gain reduction, especially at high frequencies [5]. In general, drain capacitance of CMOS transistors are smaller than the gate capacitance. Therefore, in order to make time delay of gate and drain line equal, additional capacitance is necessary at every drain node. Otherwise, the input and output lines may have different time delay per section, and therefore the output signals from each stage may not combine in-phase at the amplifier output, resulting in non-optimal gain. B. Cascaded Single-Stage Distributed Amplifier (CSSDA)

Fig. 2 is a schematic of a CSSDA [6], which has the potential for higher gain than conventional DA. By cascading multiple DA's, wide bandwidth and high gain characteristics are achieved. The gain of conventional DA is increased in proportion to the number of stages, n, as shown in Equation (3), but the gain of CSSDA is increased exponentially with the number of stages, n, as shown in Equation (4) [7]. This CSSDA property makes it possible to realize higher gain with lower number of stages compared to a conventional DA, which is especially useful in CMOS processes where transconductance is typically low. The low-frequency gain of a CSSDA is given as follows.

In Equation (4), Zint is the characteristic impedance of the inter-stage artificial transmission line. Higher values of Zint in general will yield higher low-frequency gain, but at the expense of lower cutoff frequency.

In conventional DA, phase matching is required between the input and output lines as described above, but in CSSDA, there is no need for such phase matching since there is only one signal path from the input to the output.

C. Structure of artificial transmission line

There are two filter structures popularly used in the artificial transmission line: one is a constant-k filter, and the other is an m-derived filter [8]. The constant-k filter consists of series inductance and shunt capacitance as shown in Fig. 3 (a). The cutoff frequency, fc, of this structure is given by Equation (5).

An m-derived filter is similar to the constant-k filter

structure, but has mutual inductance between the two inductors, as shown in Fig. 3 (b). The cutoff frequency of this structure is given by

where k is coupling coefficient and M is mutual inductance. Since the coupling coefficient k is negative for the series-aiding connection, the cutoff frequency of m-derived filter is higher than that of constant-k filter for same LC product.

III. DESIGN

A. 2-stage DA In this paper, we designed a 2-stage conventional DA

using the cascode structure in 65 nm CMOS as shown in Fig. 4. Cascode structure is in general suitable for distributed amplifiers due to their relatively high maximum available gain, high reverse isolation, stability and high output resistance. In addition, cascoding also reduces the Miller effect which may otherwise limit the bandwidth [9].

In order to increase the bandwidth and improve the return

Fig. 2. Schematic of CSSDA.

(a) Constant-k filter (b) m-derived filter

Fig. 3. Structure of artificial transmission line.


loss, an m-derived filter was used instead of the constant-k filter in the artificial transmission line. The two coupled inductors in the m-derived filter can be implemented by a

single inductor with a center tap, which reduces the total inductor area by up to 40% compared to a constant-k design.

Fig. 5 shows simulated performance of the designed 2-stage DA. All layout parasitics are carefully modeled by Advanced Design System (ADS). The 3 dB bandwidth of the 2-stage DA is from 4 GHz to 28 GHz with 12 dB peak gain. The S11 and S22 are better than -10 dB within the 3dB-bandwidth. The designed amplifier consumes 110 mW of dc power with 46 mA of the total drain current.

B. 2-stage Conventional Cascaded Single-Stage Distributed Amplifier (2-stage CSSDA)

In addition to the 2-stage conventional DA, 2-stage CSSDA is designed in 65 nm CMOS as shown in Fig. 6. The designed CSSDA employs cascode structure for the same number of transistors, and the input and output artificial transmission line uses the m-derived filter instead of constant-k filter.

The designed 2-stage CSSDA is implemented with stacked inductor shown in Fig. 7, which has a smaller footprint than a non-stacked inductor. Stacked inductor, while providing higher inductance than a non-stacked one for the same area, may have lower quality factor due to relatively high resistive loss [10].

Simulated performance of the designed 2-stage CSSDA is shown in Fig. 8. The 3 dB bandwidth is from 4 GHz to 26 GHz with peak gain of 15 dB. The S11 and S22 are better than -10 dB within the 3 dB bandwidth. The total drain current is 45 mA similar to the 2-stage CDA and the dc power consumption is 63 mW.

IV. RESULTS AND DISCUSSION

The designed 2-stage DA and 2-stage CSSDA are fabricated in 65 nm CMOS process. The S-parameters of the designed circuits are measured from 1 GHz to 30 GHz using on-wafer testing setup with Anritsu VNA. The measurement results are shown in Fig. 9. The peak gain of the 2-stage DA and the 2-stage CSSDA are measured to be 10 dB and 13 dB gain, respectively, which are lower than the simulation by approximately 3 dB. The 3 dB bandwidth is measured to be from 5 GHz to 20 GHz, which are narrower than the simulation. The discrepancy from the simulation is believed

Fig. 4. Simulation results of the designed 2-stage DA.

0 5 10 15 20 25 30-40

-30

-20

-10

0

10

20Simulation

Frequency [GHz]

Spar

amet

er [d

B]

S21S11S22

Fig. 5. Schematic of the designed 2-stage DA

in 65 nm CMOS process.

Fig. 6. Schematic of the designed 2-stage CSSDA

in 65 nm CMOS process.

Fig. 7. Layout of stacked inductor.


to be due to random process variation and modeling inaccuracies. Measured S11 and S22 were below -10 dB from 4 GHz to 22 GHz.

The measured results confirm that the gain of the 2-stage CSSDA is higher than the 2-stage DA by 3 dB, while consuming only 60% of the dc power, as simulation

predicts. The performance advantage of the CSSDA compared to

DA, in terms of high gain and low dc power consumption, will be even greater if more than two stages are cascaded.

Fig. 10 shows chip photographs of the 2-stage DA and 2-stage CSSDA fabricated in this work. The chip sizes are 720 540 μm2 and 580 × 450 m2 for the 2-stage DA and the 2-stage CSSDA, respectively. The 2-stage CSSDA occupies only 65% of the chip area of the 2-stage DA since stacked inductors are used and no additional capacitors are necessary on the drain nodes for phase matching.

Comparison with other CSSDA is shown in Table I. The distributed amplifiers in this work have smaller area and lower dc power consumption.

TABLE I. Performance comparison table.

Chip sizes are measured excluding pads.

V. CONCLUSIONS

In this paper, 2-stage distributed amplifier and 2-stage cascaded single stage distributed amplifier are designed in 65 nm CMOS process, and measured by on-wafer testing

setup. Broad bandwidth and high gain is obtained by using cascode structure and small area is obtained by using m-derived filter with stacked inductor in artificial transmission line. The 2-stage CSSDA shows peak S21 of 13 dB while the 2-stage DA exhibits peak S21 of 10 dB. Measured results show that the CSSDA provides higher gain than the DA while consuming less dc power.

Fig. 9. Measurement results of the designed DAs.

5 10 15 20 25 30

-30

-20

-10

0

10

Measurement

Frequency [GHz]Sp

aram

eter

[dB]

CSSDA S21

CSSDA S11

CSSDA S22DA S21

DA S11

DA S22

(a) 2-stage DA (chip size: 720 × 540 μm2)

(b) 2-stage CSSDA (chip size: 580 × 450 μm2)

Fig. 10. Chip photograph.

Fig. 8 Simulation results of the designed 2stage-CSSDA.

0 5 10 15 20 25 30-30

-20

-10

0

10

20Simulation

Frequency [GHz]

Spa

ram

eter

[dB

]

S21S11S22


ACKNOWLEDGMENT

This material is based upon work supported by the Ministry of Trade, Industry & Energy (MOTIE, Korea) under Industrial Technology Innovation Program. No.10067194, ‘Human detection radar sensor under obstructed conditions’ and IDEC.

REFERENCES

[1] Hyung-keuk Lee and Nam-Kyung Lee, “A compressive sensing-based data processing method for heterogeneous IoT environments,” IEEE 2017 International Conference on Platform Technology and Service (PlatCon), pp. 1 – 4, 2017.

[2] Amin Arbabian and Ali M. Niknejad, “Design of a CMOS tapered cascaded multistage distributed amplifier,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 4, pp. 938 - 947, 2009.

[3] Mohsin Tarar, Muh-Dey Wei, Marc Reckmann and Renato Negra, “Enhanced gain bandwidth and loss compensated cascaded single-stage CMOS distributed amplifier,” German Microwave Conference, pp. 335 – 338, 2015.

[4] T. T. Y. Wong, Fundamentals of Distributed Amplification. Norwood, MA: Artech, 1993

[5] Liang-Hung Lu, Tai-Yuan Chen and Yi-Jay Lin, “A 32-GHz non-uniform distributed amplifier in 0.18 μm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 11, pp. 745 – 747, Nov 2005.

[6] A. Worapishet and I. Roopkom, “Cascaded double-stage configuration for high-performance broadband amplification in CMOS,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1606-1609, May, 2005.

[7] J. Liang and C. Aitchison, “Gain performance of cascade of single stage distributed amplifiers,” Electronics Letters, vol. 31, no. 15, pp. 1260-1261, Jul. 1995.

[8] M. H. Hebb, C. W. Horton, and F. B. Jones, “On the design of networks for constant time delay," Journal of Applied Physics, 20, 616, 1949.

[9] Jun-Chau Chien and Liang-Hung Lu, “40-Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 12, Dec, 2007.

[10] J. Burghartz, M. Soyuer, K. Jenkins, and M. Hulvey, “High-Q inductors in standard silicon interconnect technology and its application to an integrated RF power amplifier,” in IEEE IEDM Tech. Dig., 1995, pp. 1015-1018.

[11] Tzu-Yuan Huang, Yu-Hsuan Lin, Jen-Hao Cheng, Jui-Chi Kao, Tian-Wei Huang, and Huei Wang, "A high-gain low-noise distributed amplifier with low dc power in 0.18 m CMOS for vital sign detection radar," IEEE MTT-S International Microwave Symposium, 2015.

[12] Ping Chen, Jui-Chih Kao, Pin-Cheng Huang and Huei Wang, "A novel distributed amplifier with high gain,

low noise and high output power in 0.18 μm CMOS technology." IEEE MTT-S International Microwave Symposium, 2011

SeongBin Kang received the B.S. degree in electrical and electronic engineering from Sungkyunkwan University, Suwon, Rep. of Korea, in 2016 and is currently working toward the M.S. degree in electrical and electronic engineering from Sungkyunkwan University, Suwon, Rep. of Korea.

His main interests are RF circuits for wireless communications, especially wideband amplifier and substrate integrated waveguide (SIW).

YunSik Na received his BS degree in electrical engineering from Chungbuk National University, Rep. of Korea, in 2014. He is currently working towards the Ph.D. degree in electrical and computer engineering at the Sungkyunkwan University, Suwon, Rep. of korea.

His main interests are RF circuits for millimeter wave multi-antenna system,

especially true time delay and attenuator.

Munkyo Seo received his BS and MS degrees in electronics engineering from Seoul National University, Rep. of Korea, in 1994 and 1996, respectively. He received his Ph.D. degree in electrical engineering from the University of California, Santa Barbara (UCSB), CA, USA, in 2007. From 1997 to 2002, he was an RF engineer with

LG Electronics Inc., Anyang, Rep. of Korea, designing microwave subsystems for wireless communication. He was an assistant project scientist with UCSB from 2008 to 2009. In 2009, he joined Teledyne Scientific Company, Thousand Oaks, CA, USA, where he worked on the design of various millimeter-wave, terahertz, and high-speed mixed-signal circuits. Since 2013, he has been with Sungkyunkwan University, Suwon, Rep. of Korea, where he is now an associate professor.


Abstract – A 12 X 12 and 32 X 32 sensor array chip for fully electronic bio material detection is presented. The sensor principle is based on a carbon nanotube field effect transistor (CNT-FET). Each sensor cell of the array chip contains a buffer circuit which provides independent sensing signal to the common correlated double sampling type successive approximation register analog/digital converter. By using the CNT-FET’s electrolyte gate characteristics, we successfully stabilized the electrochemical potential of electrolyte through voltage regulator circuits. Proper operation of the chip is demonstrated by electrochemical experiments and actual sensor realization. The chip is fabricated on the basis of a 0.35um CMOS process for a 12 X 12 array and a 32 X 32 sensor array.

I. INTRODUCTION

Nano-biosensor, a convergence technology of existing biosensor technology and nano technology has been emerged to be one of the most promising candidates to overcome the barriers of current medical issues such as single molecule analysis, real time detection, low power dissipation and miniaturization to be used as in vivo applications [1]-[2]. The electrical nano-biosensors, in particular, have additional advantages in sensing speed, detection accuracy, and semiconductor device integration possibility. However, electrical sensors suffer from parasitic noise issues such as the noise from non-specific target molecules. To reduce these effects, we proposed a sensing scheme with electrolyte potential regulation, a buffer circuit for sensor isolation, and demonstrated the actual array sensor operation through statistical measurement data.

II. ELECTROLYTE CHEMICAL POTENTIAL REGULATOR

A. Biosensor System and Sensing Method The system being measured must be at a steady state

throughout the time required to detect the sensing signal. A common cause of problems in sensing signals and their analysis is drift in the system being measured. In practice a steady state can be difficult to achieve. The solution potential can change through adsorption of solution impurities, buildup of reaction products in solution, coating degradation, and temperature changes, to list just a few factors. In this respect, the use of reference electrode using easily polarizable material, e.g. Ag/AgCl, can fix the solution potential, and this has been considered to be a de facto rule for ISFET type sensors. For CNT-FET, however, Ag/AgCl method is incomplete to reflect all these CNT-FET’s variation factors because CNT-FET uses the solution dependent electrical double layer(EDL) as the gate dielectric of transistor. Moreover, the abundant surface charges which are formed at the surface of CNT are also subject to change, resulting in time dependent current decrease or increase.

Fig. 1 (a) illustrates the typical schematic of bio-sensor operation. Specific Binding(SB) means the binding to receptors of interest, and Non-Specific Binding(NSB) is the binding to other sites. The noises of biosensors usually stem from parasitic environmental factors and NSB effects. A general method to remove noises is using a control sensor and a detection sensor simultaneously and canceling the common mode signals of both sensors. Through several subsequent procedures, which are both chemical and electrical, the remaining signal component representing SB should be detected in real time. Fig. 1 (b) shows the concept of sensing method proposed by this paper which can be used for CNT-FET type sensors. The conductance modulation effect by control sensor’s electrolyte gate is used to regulate the electrolyte’s electrochemical potential which is commonly applied to both control sensor and detection sensor. Comparing with Ag/AgCl reference electrode method which is most popular, this method shows superior common mode noise rejection characteristics and can be implemented with negligible cost.



A CMOS Micro Array DNA Biosensor with an On-chip Controlled Electrolyte Electrochemical Potential Regulator

Jun Yeon Yun, Jinhong Ahn, Nakwon Yoo, and Young June Park Department of Electrical and Computer Engineering, Seoul National University,

Seoul 151-744, Republic of Korea E-mail: [email protected]


(a) Typical schematic of Bio-sensor operation

(b) Concept of sensing method

Fig. 1. Electrolyte chemical potential regulator

B. Electrochemical Regulator Theory

Fig. 2 shows the sensor configuration. As shown in Fig. 2 (b), this sensor system is composed of many individual sensors, and each sensor has a circular island electrode. The CNT-FET is made using the single walled CNT network deposited on the electrodes to form a circular electrical channel to the common enclosing electrode in a concentric fashion. Fig, 2 (a) shows the model sensor system consisting of 2 electrodes. An external metal electrode which is used to regulate the electrolyte potential is located in the upper position and the sensor system with Au electrodes is located in the bottom position. Because the size of bottom electrode is much larger than the upper electrode, the bottom electrode is assumed to be semi-infinite.

(a) Electrode Schematic (b) Sensor Array

Fig. 2. Schematic and Bird’s eye view of CNT-FET sensors

When a potential E is imposed between the metal electrode and Au electrode, current I flows and is carried through the solution by the migration of ions. The electric field which is necessary for ions to migrate is provided by that portion of the applied potential which is dropped across the solution between the two electrodes. The potential ΦA, ΦB represents the potential at the electrolyte-metal interface region of

upper and bottom electrodes respectively. Because the ΦB

works as the gate voltage of CNT-FET, this potential should be controlled in such a way that the current of CNT-FET to be constant.

The theoretical model to determine the ΦB is as follows. Charge transfer may occur at the electrode-electrolyte interface if it is thermodynamically favorable. In a metallic electrode material(as most electrodes are) the energy level of the electrons occupies a continuum of states below the Fermi level. If this level is higher than the highest occupied molecular orbital or below the lowest unoccupied molecular orbital level of the molecules in the electrolyte then electron transfer becomes thermodynamically viable. In equilibrium these should necessarily agree with the thermodynamic equilibrium described in the Nernst Equation.

0 ln[ ]s

j jj

RTE E v cnF (1)

Where E : Electrode potential

E0 : Standard electrode potential νj : Stoichiometric coefficient cj

s : Local concentration at the surface of the electrode

n : Number of moles of electrons transferred R : Molar gas constant T : Absolute temperature F : Faraday’s constant

Whenever the potential of an electrode is forced and the electrode is polarized, it can cause current to flow via electrochemical reactions that occur at the electrode surface. When there are two simple, kinetically controlled reactions occurring, the potential of the cell is related to the current by the following(known as the Butler-Volmer equation).

0 exp ( ) exp (1 ) ( )j j j j

j jnet j eq j eq

n F n Fi i E E E E

RT RT (2)

Where inet j : net current of the redox couple j i0 j : exchange current of the species j

: Electron transfer coefficient E - Eeq j : Overpotential of a single redox couple

In the 2 electrode system consisting of upper and bottom

electrodes, the bottom electrode potential ΦB can be determined by applying the Butler-Volmer equations at both electrodes and solving the steady state current and voltage. However, solving this 2 electrode system can be very complicated if we consider the interactions between the 2 electrodes, and the IR voltage drop due to the ion transport in the solution. Moreover, depending on the ratio of exchange currents between the upper electrode and bottom electrode, a steady state condition may be never theoretically achieved. However, even though the steady


condition is not achieved, the ΦB can be controlled to be constant through the alternating control of upper electrode. (This control method is similar to the conventional potentiostat method and will be discussed in the next section.) Also, in case the exchange current of bottom electrode is very small compared to the upper electrode, the input resistance of bottom electrode can be defined to be Ri which is very large, and the ΦB can be determined by following equation using iteration method.

totneti

Ei

R (3)

01

exp ( ) exp (1 ) ( )j j

mj j

i j eq j eqj

n F n FE R i E E E E

RT RT (4) Where

E : Bottom electrode potential (ΦB) Ri : Input resistance of bottom electrode

Fig. 3 shows the Au electrode case where this equation can

be applied. Because Au is ideally polarized between the voltage range of -0.421V to 0.816V w.r.t. standard hydrogen electrode of ph7, the resistance at this range becomes very large.

Fig. 3. H2O polarization at Au electrode

Another issue to be resolved is that the ΦB value is also

dependent on the electrical double layer(EDL) capacitance because there is no dielectric layer except EDL on CNT transistor. This layer can be modeled using a combination of concepts from electrostatics and statistical mechanics, leading to the known Poisson–Boltzmann’s equation. This diffuse layer is known as the Gouy–Chapman layer or the electrical double layer. However, it was noticed that the original theory of Gouy–Chapman overestimates the interface charge. This was remedied by Stern, who realized that ions cannot approach the electrode surface closer than their ionic radius.

Therefore, the capacitance of EDL can be modeled by 2 series capacitors which has following equation

11DL

s

Stern s

C

C 2 22 0s

skTc z q

Whereλs : Debye length εs : Permitivity of solution z : Ionic valence c0 : molar concentration of ion

This equation shows that the EDL capacitance is mainly dependent on the ion characteristics, i.e. the species and the concentration of solution ion. In case the concentration of ion changes during the sensing operation, B also changes to address this variation. C. Analogy to 3 Electrode Potentiostat

Fig. 4 shows the analogy between 3 electrode potentiostat and this method. A modern 3 electrode potentiostat (Fig. 4 (a)) compensates for the solution resistance between the counter and reference electrodes. The main idea for this apparatus is using an operational amplifier, and the potential difference is removed through feedback mechanism. As shown in Fig. 4 (b), the op amplifier input is determined by the CNT gate voltage using a constant resistor to convert the CNT resistance to input voltage. The difference between Fig. 4 (b) and Fig. 4 (a) is that in Fig. 4 (b), the electrolyte potential at the CNT gate region is compensated by the overvoltage reaction of counter electrode(upper electrode in Fig. 2 (a)).

(a) Potentiostat (b) CNT electrolyte regulation

Fig. 4. Comparison of conventional potentiostat and CNT electrolyte regulation system


A. Biosensor Circuit Design Fig. 5 is a buffer circuit in every microarray sensor which

removes the parasitic capacitance effects of other sensors. Vbias is the bias voltage between carbon nanotube node and common enclosing electrode. Op amplifier keeps the bias voltage through negative feedback and the upper and lower path of feedback is determined by the Vbias polarity denoted as Vmode. Current mirror circuit which is isolated


from sensing part transfers the sensing result to open drain type output circuits. Rext is the load resistance, and amplification factor is determined by the ratio of Rext to CNT resistance. This output signal is measured by a common correlated double sampling type successive approximation register analog/digital converter which was reported by our group. [3] Measurement data can be recorded statistically to an external computer by on chip UART communication circuit.

Fig. 5. A buffer circuit of each microarray sensor to remove the parasitic capacitance factors from other sensors

IV. CONCLUSIONS B. Measurement Result

For CNT resistance sensing, CNT is deposited uniformly using dip coating method on the concentric shaped electrodes. To reduce the contact resistance between CNT and metal electrode, Au is deposited on the Al top layer using electroless plating. Fig. 6 shows the experimental DNA detection result using CMOS integrated biosensor. By functionalizing the single strand DNAs which are thiol-modified for the attachment to the Au nano particles on the CNT layer, arrayed sensor devices have been activated to detect the target DNAs(t-DNA). After about 100 seconds from the time that t-DNA was introduced, the CNT resistances of all the array sensors rapidly increased showing the t-DNA response. The concentration of t-DNA in TE buffer is 5μM. The details of experimental method are the same as the previous result of our group reported for single sensor. [3]

Without using the electrolyte voltage regulator, this sensing result shows drift and fluctuation mechanisms which diminishes the sensing sensitivity. Because these phenomena are occurring for all the sensors, this shows the mechanism is related with the electrolyte potential.

Fig. 6. DNA detection using CMOS integrated CNT biosensor The experiment environment to demonstrate chip

operation with voltage regulator is shown in Fig. 1 (b). The Vcom(1.5 V) is applied to enclosing electrode of concentric structure unit cell and the divided voltage(Vr) between carbon nanotube resistance and reference resistance(Rref = 4*Rcnt) is applied to the one of the input of operational amplifier as shown Fig. 1 (b). As a comparison experiment, the current between carbon nanotube resistance and GND is measured without voltage regulator operation (Fig. 7 (a)). The concentric structure coated by p-type CNT shows electrolyte gating effect having different drain, source electrode area ratio, and acts like a normally turned on PMOSFET. After applying step voltage to the enclosing electrode, current value of CNT is reduced as time goes by due to the delay in forming electric double layer, which plays a role in giving a gating effect. With voltage regulator, the electrolyte potential is controlled by a metal electrode connected to operational amplifier output, and uniform current is measured(Fig. 7 (b)). If Vr is larger than reference voltage(Vref = 0.8*Vcom), op-amp output goes high and Rcnt becomes smaller. Whereas, if Vr is smaller than Vref, Rcnt becomes bigger. Fig. 8 shows the simulation results using Hspice, and we confirmed that the measurement data are similar to the simulation data.

The statistical results of carbon nanotube resistance using 12 x 12 sensor array is shown in Fig. 9. Uniform resistance values are observed even though there are some arrays with abnormal resistance values by poor contact resistance between the CNT and electrode. Fig. 10 is the chip photo of 12 X 12 sensor array and 32 X 32 sensor array.


Fig. 7. Change in current value and electrolyte voltage of control

sensor (a) without voltage regulator; (b) with voltage regulator

Fig. 8. Hspice simulation result

Fig. 9. The statistical results of 12x12 microarrays

(a) 12 X 12 array (b) 32 X 32 array

Fig. 10. The photographs of CMOS integrated CNT microarrays

with on-chip electrolyte chemical potential regulator

IV. CONCLUSIONS

An effective electrolyte electrochemical potential regulation scheme is shown which can be applied to CMOS based electrical biosensors. Because potential difference is imposed between electrolyte and the metal electrode by feedback mechanism, redox reaction which is fast enough to compensate the change of reference voltage can be achieved. This means conventional referencing material like Ag/AgCl or expensive porous Pt electrode can be replaced by normal metal electrodes which are compatible to CMOS fabrication technology. In this paper, a fully CMOS-integrated CNT sensor array platforms that consist of an 12 X 12 and 32 X 32 arrays have been demonstrated. With the electrolyte chemical potential regulator and sensor isolation circuit, we showed the environmental noises of a electrical nano-biosensor can be reduced. Using this chip we can get statistical results of carbon nanotube using integrated CMOS buffer circuit without Ag/AgCl reference electrode.

0 50 100 150 200 250

-8.4x10-4

-8.5x10-4

-8.5x10-4

IDS Electrolyte

Time (sec)

Cu

rre

nt

(A)

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

Vo

ltag

e (V

)

-20 0 20 40 60 80 100 120 140 160 180-9.1x10-4

-9.2x10-4

-9.2x10-4

IDS Electrolyte

Time (sec)

Cu

rre

nt

(A)

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

Vo

ltag

e (V

)

(a)

(b)


ACKNOWLEDGMENT This work was supported by the IDEC.

REFERENCES

[1] J. Kong, N. R. Franklin, C. Zhou, M. G. Chapline, S. Peng, K. Cho, and H. Dai, “Nanotube molecular wires as chemical sensors,” Science, vol. 287, pp. 622–625, 2000.

[2] K. Besteman, J. Lee, F. G. M. Wiertz, H. A. Heering, and C. Dekker, “Enzyme-coated carbon nanotubes as single-molecule biosensors,” Nano Lett., vol. 3, no. 6, pp. 727–730, 2003.

[3] J. W. Ko, J.-M. Woo, J. Ahn, J. H. Cheon, J. H. Lim, S. H. Kim, H. Chun, E. Kim and Y. J. Park, “Multi-order dynamic range DNA sensor using a gold decorated SWCNT random network,” ACS Nano, vol. 5, no. 6, pp. 4365–4372, 2011.

Jun Yeon Yun received the B.S. degree in Electronics Engineering from Kyungpook National University in 2013. He is currently working toward the Ph.D. degree at Seoul National University. His current research interests include electrical biosensor and electron tunneling through heterogeneous junctions.

Jinhong Ahn received the B.S.

and M.S. degrees in electronic engineering from Seoul National University in 1982 and 1984, respectively. He was with LG Semiconductor from 1984 to 1999 as a Memory design engineer, and Hynix Semiconductor from 1999 to 2008 as a research fellow of advanced DRAM design. Since

2008, he has been with Nano Systems Institute (NSI) in Seoul National University as a principal researcher, and is now the president of the Duality Inc., Daejeon, Korea. His research areas in NSI were electrical sensors using nano materials and array type biosensor chip design for medical applications.

Nakwon Yoo was born in Korea in 1985. He received the B.S. degree in electronic engineering from Seong Kyun Kwan University, Seoul, Korea, in 2012. He is currently pursuing the Ph.D. degree with Seoul National University, Seoul. His current research interests include Si-based acoustic sensor with the tunneling devices.

Young June Park received the B.S. and M.S. degrees from Seoul National University (SNU), Seoul, Korea, in 1975 and 1977, respectively, and the Ph.D. degree from the University of Massachusetts at Amherst, Amherst, MA, USA, in 1983. He joined Hynix Semiconductor Inc., Icheon, Korea. Since 1988, he has been with SNU,

where he is currently a Professor with the School of Electrical Engineering and Computer Science.


Abstract This paper shows the design of low-power 16-PSK modem that requires high-speed data transmission with limited bandwidth and power. The proposed structure is comprised of modulator and demodulator. In order to reduce the error between neighboring phase symbols in the detection process of symbol, bits of each phase symbol are converted into Gray coded bits. And in order to reduce the interference effect on the adjacent channel, the rectangular signal of 16-PSK modulated symbol is smoothed as rounded shape through the LPF. The LFP consists of 33 taps through simulation which shows the approximation with low truncation error. The modem with the above-mentioned design is implemented by the MagnaChip/SK Hynix 0.35 process. The supply voltage and the maximum operating frequency in modem is respectively 3.3V and 20MHz.

I. INTRODUCTION

In the data communication system, the modulator and the demodulator transmit and receive data processed in the embedded system. It is required to make an optimum design of modem with low BER under the limited condition with bandwidth as well as power.

M-ary PSK modem is adopted as the modem which is suitable for the transmission media which does not have enough bandwidth. In the fading environment, M-ary PSK modem is preferred as better robust transmission method than M-ary QAM.

In this paper, a 16-PSK modem designed, which consists of (1) modulator with Gray code module, symbol mapping and wave-shaping filter (2) demodulator with symbol decision, symbol demapper and Gray decode module. The designed modem has baseband modulator and demodulator, where DA, AD and RF circuit part is not included. And for high-speed data transfers, parallel processing will be used. In addition, the multiplier used in the modulator occupies a lot of areas, resulting in circuit delays and degraded operations. To solve this problem, the solution with more simple design is proposed.

Fig. 1. 16-PSK baseband modem structure.

The structure of the proposed 16-PSK modem consists of

baseband modulator and baseband demodulator as shown in Fig. 1.

If serial data continuously enters into the baseband modulator, every group of 4 consecutive serial bits data is converted into 4 bits parallel data bus in serial to parallel conversion circuit. In order to reduce errors between the neighboring phase symbols, 4 bits in each phase symbol are Gray coded in the Gray encoder. The 4 bits in the Gray coded symbol is mapped to one of 16 symbols whose in-phase magnitude and quadrature magnitude with 8 bits are in memory. And each in-phase magnitude and quadrature magnitude is filtered respectively through wave-shaping LPF in each in-phase/quadrature branch for reducing the interference effects to adjacent channel.

The received symbols should be decided correctly in demodulator for restoring data transmitted from the baseband modulator. Because DA and AD are not included in this design, those 8 bits data processed in LPF at modulator are connected directly to decision device at demodulator. The decision device in in-phase branch as well as quadrature branch discriminates respectively every received in-phase signal as well as quadrature signal with 3 threshold values and sign bit. The determined data in each in-phase branch and quadrature branch is combined and decoded through Gray decoder. And those decoded parallel 4-bits data converted into serial bits stream in parallel to serial converter. The bit error rate (BER) varies depending on the environment and the modulation method used during the PSK transmission. Therefore, the modulation methods have to be determined with this in mind. The M-ary PSK performance can be judged based on the probability of bit



16-PSK baseband Modem Design for Data Communication

Nam-Won Kim1 and Myoung-Seob Lima Department of Electronic Engineering, Chonbuk National University



errors. The probability of M-ary bit error is expressed by the following equation [1].

(1)

Equation (1) represents the probability of M-ary bit error.

It is , and is the hamming

weight value assigned to [1], [2]. If there is error in symbol with 4 bits, one bit or 4 bits in worst case in symbol may be error. Because there is probability that symbol can be mistaken as neighboring symbol, 4 bits in each symbol is encoded using Gray coding rule. This Gray encoding makes error reduced to be compared with transmission without Gray encoding process.

Fig. 2. M-ary PSK bit error rate.

Fig. 2 shows the bit error probability according to M for

Equation (1) using MATLAB. When a larger PSK is used for M, there is a higher probability of error than when a smaller PSK is used [3], [4]. From these results, it is required to increase more the magnitude of symbol in higher M-ary PSK than lower M-ary PSK. In the design of 16 PSK baseband modem, LPF with arithmetic process such as multiplication includes more complexity than other logical block. Therefore, it is necessary to select the number of bits which represents the design parameter such as LPF coefficients and taps.

In this paper, the 33 taps of LPF are used. And for reducing complexity, the appropriate truncation process is selected. By comparing the repeated simulation results with theoretical result, the design parameter which satisfies the performance requirements could be selected. This paper describes the detailed structure of 16-PSK modem in chapter II. The chapter III explains the simulation results and the conclusion is written on chapter IV.

II. EXPERIMENTS

A. Baseband modulator

Fig. 3. Serial to parallel converter.

Fig. 3 shows a serial to parallel converter that converts

serial data to parallel data. When continuous signals are entered, the selection line makes input serial data to be converted into parallel data. Converting serial bits into 4-bit parallel data makes it possible more high-speed data to be transmitted with the given limited bandwidth [5].

Fig. 4. Gray encoder.

In Fig. 4, shows a Gray encoder that converts the output

from Fig. 3 into Gray code. As mentioned in introduction, the probability of decision error between neighboring symbols is higher than other case. Therefore, it is optimum to assign bits with one bit difference between neighboring symbols, which makes at most 1-bit error even though there is symbol errors between them [6]. In order to solve such problems, we will produce Gray code using a XOR gate as shown in Fig. 4. It is possible to improve the performance of 16-PSK by using the produced Gray code.

Gray coded data is entered to the stored address of the 16-ary mapper composed of in-phase data and quadrature data. The phases value allows the symbol to be mapped to the corresponding data represented according to the position of the phase. The represented data consists of 8 bits and is stored in the memory. When the encoded data are entered to the address bus in the memory, the stored value is produced. Considering the conditions for constructing an 8-bit data used in the 16-ary mapper, floating-point and fixed-point operations can be used when calculating decimal points in the hardware. To improve the accuracy of this design, a floating-point hardware design has to be implemented. However, accurate calculations consume a lot of power because they consume more hardware than fixed ones [7]. Fixed points are used in the 16-ary mapper in order to solve the problems mentioned. And in 16-ary mapper, the position where the 16 symbols are formed will be converted and saved as fixed points. By carrying out this method for processing data, the design area can be reduced.

When the in-phase data and quadrature data output from the 16-ary mapper are directly transmitted to the receiver, side-lobe spectrum may be overlapped with the adjacent channel’s spectrum which causes error to be generated.


Because the data with rectangular waveform has high-frequency signal which is side-lobe spectrum, it is necessary to make rectangular form rounded form with wave-shaping filter. Therefore, the input data is passed through the LPF to remove the side lobe which is a noise component.

(2)

Equation (2) represents the filter’s impulse response

signal of the LPF [8]. The filter’s performance will vary on . with 0 is not used because the impulse response of

filter shows a sinc function with long side-lobe in frequency domain. In this paper, we used , which has a small side lobe [1]. When MATLAB simulation is performed, errors occur when t is 0, so sampling was performed at intervals of 0.25 with a difference of -0.000001 between -4 and 4, which is the range of t. Thus, the filter factor result is 33 taps.

In a general LPF, the number of bits increases during a convolution. As the number of bits increases, the area of the hardware increases and much power is consumed.

In this paper, we propose an LPF structure that minimizes noise using the 33 taps and adds lower bit truncation processes during the intermediate convolution operation.

Fig. 5. Before and after truncation process.

Fig. 5 shows the MATLAB simulation results before and

after the truncation process for equation (2). The marked areas show differences in the process. In Fig. 5 shows that there is not a big difference in the peak value but only a slight difference in the side lobe when the results before and after the truncation operation are compared. Based on the results of the process using the truncation, it can be applied to the LPF by applying it to the intermediate calculation process of the convolution.

Fig. 6. LPF.

Fig. 6 shows the proposed LPF. The 8-bit data output from the 16-ary mapper is sequentially inputted to the D flip-flop by a clock and is then configured to transmit data to the next D flip-flop.

The input data is multiplied by a filter coefficient and a multiplier, and then truncation is performed to produce 8-bit data. The filter coefficients are composed of data converted to 8-bit fixed point data using the data calculated by MATLAB in equation (2). The computed data is additionally computed with the data truncated by the multiplier through the adder. Since carry can occur during this process, truncation process is performed on the output data of the adder to produce 8-bit data. If the process is repeated until the 33 taps are reached, y(n) is produced as 8-bit data. B. Baseband demodulator

Fig. 7. 16-PSK constellation.

Fig. 8. Decision device.

TABLE I.

Threshold parameters of the decision device.

Values Fixed point

0.905 01001110

0.605 01001011

0.38 00101100

Fig. 7 shows the constellation of the proposed 16-PSK.

The received data is mapped to recovered symbols by determining the phase of data in the baseband demodulator


according to the constellation expressed by the Gray code. The received data, according to the constellation shown as Gray code, is mapped as recovered symbols after determining the data’s status in the baseband demodulator.

Fig. 8 shows a decision device that converts 8-bit in-phase data and quadrature data received from the baseband modulator into 4-bit data. When the received data is input, a threshold value composed of fixed points is determined as shown in Table I, and data is output. is the sign bit of the received quadrature magnitude. is the sign of the received in-phase data and compares the received data value excluding the sign bit with the threshold value among the received 8-bit in-phase magnitude. When the remaining data value is larger than , 1 is output. When the remaining data value is smaller than 0, 0 data is output

through the operations with the NAND gate. The received quadrature data, excluding the sign bit, are determined through threshold values and . The determined data is output via through operation with XOR gate.

Fig. 9. Gray decoder and parallel to serial converter.

Fig. 9 is a block diagram of the structure that receives the

data output from the structure in Fig. 8 as input data, converts it into binary data and outputs it as serial data. Since 4-bit data recovered from the structure is composed of Gray codes, it is necessary to convert the data into original binary data. The structure shown in Fig. 9 is converted into binary data, receiving converted 4-bit binary data as input, and allowing serial data to be sequentially output by and

. C. Implementation and verification process

The baseband modulator and the baseband demodulator of the proposed 16-PSK modem are implemented by Verilog-HDL coding. Then, the code described is verified by RTL simulation using ModelSim of Mentor Graphics. We also modeled the proposed 16-PSK modem using MATLAB and compared it with the results of 16-PSK in Fig. 2.

The verified simulation is synthesized using Synopsys’ Design Compiler. After pre-simulation of the generated netlist and backend process using Synopsys’ Astro, we have verified the 16-PSK modem implemented through STA and post-simulation.

FPGA verification is carried out using SoC board with ALTERA’s Excalibur device and modulation and demodulation process using TFT-LCD and LED built in board.


A. Simulation verification result The simulation verification process is verified by using

MATLAB, modeled after the result, and the output value of module unit of RTL simulation of 16-PSK modem described by Verilog-HDL using ModelSim is checked.

In the simulation result of the baseband modulator, when serial data is inputted, it is confirmed that 4-bit parallel data is outputted according to the selection line. And check that it is output as the Gray code. The output Gray code confirms the 8-bit data output value which determines the position between phases through 16-ary mapper. The output 8-bit data becomes the input of the LPF and confirms the operation result value 33 taps.

In the baseband demodulator simulation results, the 8-bit data received from the baseband modulator is received and restored to the original data signal. In-phase data and quadrature data are received, and the 4-bit data determined according to the threshold value, is checked and output data converted into binary data is confirmed. Then the value converted to serial data was checked. Through this process, the input waveform of the baseband modulator was compared with the output waveform of the baseband demodulator.

Fig. 10. BER curve.

Fig. 10 shows the BER of the proposed 16-PSK modem

modeled using MATLAB. Compared with the 16-PSK BER generated by equation (1) in the same WGAN conditions, the BER characteristic was improved when it was below 20dB as shown in Fig. 10.

Fig. 11. Baseband modulator result.


Fig. 11 shows the simulation results of the baseband modulator. When the serial data is input, the binary data can be converted into parallel data, and the phase symbol shown in Fig. 7 can be confirmed by comparing the Gray data in Fig. 11. And the output value from 16-ary mapper can be confirmed using the results from in-phase and quadrature. The computation result using the proposed LPF structure can be confirmed in LPF in-phase and LPF quadrature.

Fig. 12. Baseband demodulator result.

Fig. 12 shows the simulation results of the baseband

demodulator. It can be confirmed that 4-bit Gray data is converted by receiving the data transmitted from the baseband modulator. Also, binary data and serial data can be found in Fig. 12.

Fig. 13. Chip layout.

Fig. 13 shows the chip layout generated as a result of

place and route process using Astro. As a result of Verilog-HDL coding and implementation using CMOS 350nm process, the operating frequency is 20MHz, the size is 2.74mm2, and it is implemented with about 30K gate count.

Fig. 14. Post-simulation result.

Fig. 14 shows the post-simulation results of the

implemented 16-PSK modem. The input data waveform of the baseband modulator matches the output data waveform of the baseband demodulator. B. FPGA verification result

Fig. 15. Chip test diagram.

Fig. 15 shows the environment for FPGA verification.

The environment is constructed based on the results that are sufficiently verified by simulation.

In the FPGA verification process, the input data is implemented as a look-up table through ROM in consideration of the number of cases. Then, the clock division is used to divide the frequency generated by the device into the frequencies at which the TFT-LCD can operate.

According to the clock operation, the data output from the ROM is input to the implemented 16-PSK modem, and the output data of the baseband modulator of the modem is input to the TFT-LCD and the baseband demodulator. The data output value of the baseband demodulator is output to the LED.

Fig. 16. Chip test result.

Fig. 16 shows FPGA verification and chip test results.

The first LED lighting in Fig. 16 shows that data 1 is input to the baseband modulator. The second LED lighting shows that data 1 is output through the demodulation process in the baseband demodulator. The third LED is turned off when the input data matches the output data and lights up when the output data does not match.

The result modulated through the input data is formed near 16 symbols of the TFT-LCD. In order to confirm the additional performance of the 16-PSK modem, noise was added in the modulation process using PN codes.

The dip switch of the equipment was used to determine the intensity of the noise, and the noise was constituted in


level units to add noise of five levels. In each step, the noise data added to the bits are added to the vector unit. In the implemented 16-PSK modem, when the noise of level 4 of higher is added, the input data and output data are inconsistent and the third LED is turned on.

IV. CONCLUSIONS

In this paper, we made a design of the 16-PSK baseband modem with bandwidth efficient communication under the limited bandwidth condition. Before implementing 16-PSK baseband modem with FPGA, the design parameters with low HW complexity and the required performance are selected through MATLAB simulation. The BER simulation results of modem with the selected design parameters satisfied the required performance and lower areas with reducing HW complexity. The designed 16-PSK modem employs the error reduction method using the Gray code and LPF using truncation. The overall modem design was implemented using more simple structure. By using the simpler structure of the 16-PSK baseband modem, it is expected to make an efficient design of more complex M-ary PSK modem requiring limited bandwidth and high-speed data transmission.

ACKNOWLEDGMENT

This work was supported by the IDEC.

REFERENCES

[1] M. K. Simon; M. S. Alouini, Digital communication over Fading Channels – A Unified Approach to Performance Analysis, 1st Ed., Wiley, 2000.

[2] P. J. Lee, “Computation of the Bit Error Rate of Coherent M-ary PSK with Gray Code Bit Mapping,” IEEE Trans. Commun., vol. 34, no. 5, pp. 488-491, May. 1986.

[3] D. Divsalar; M. K. Simon, “Multiple-symbol differential detection of MPSK,” IEEE Trans. Commun., vol. 38, no. 3, pp. 300-308, Mar. 1990.

[4] S. Alamouti, “A simple transmit diversity technique for wireless communications,” IEEE J. Sel. Areas Commun., vol.16, no. 8, pp. 1451-1458, Oct. 1998.

[5] B. Saltzberg, “Performance of an efficient parallel data transmission system,” IEEE Trans. Commun. Technol., Vol. 15, no. 6, pp. 805-811, Dec. 1967.

[6] J. Li; M. Wen; X. Cheng; Y. Yan; S. Song; M. H. Lee, “Differential spatial modulation with Gray Coded antenna activation order,” IEEE Commun. Lett., vol.20, no.6, pp. 1100-1103, Jun. 2016.

[7] S. Aslan; E. Oruklu; J. Saniie, “A High-Level Synthesis and Verification Tool for Fixed to Floating Point Conversion,” Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symp., Boise, USA, Aug. 2012, pp. 908-911.

[8] Michael Zoltowski, “Equation for the Raised Cosine and Square-Root Raised Cosine Shapes” [Online].

Available: http://www.commsys.isy.liu.se/TSKS04/lectures/3/MichaelZoltowski_SquareRootRaisedCosine.pdf.

Nam-Won Kim is currently pursuing an undergraduate course in the Department of Electronic Engineering from Chonbuk National University, Jeonju, Korea. His research interests include parallel computing and deep learning.

Myoung-Seob Lim received B.S.,

M.S. and a Ph.D. degree in the Department of Electronic Engineering from Yonsei University, Korea in 1980, 1982 and 1990, respectively. He has worked for the Electronics and Telecommunications Research Institute (ETRI) from 1986 to 1996. He developed the commercial CDMA system under the

joint development project between ETRI and Qualcomm from 1991 to 1994. He has joined the department of information and communication, Chonbuk National University in 1996. His research areas include the modulation/demodulation, synchronization, error correction coding for the advanced CDMA system, MIMO system, OFDM system, UWB and Vehicular Infortonics (CAN).


Abstract – Wireless access in vehicular environments (WAVE) has the potential to both improve the quality of traffic services and provide services of convenience. However, these are only guaranteed if WAVE is securely protected from security threats. In order for WAVE to be securely protected, services such as the advanced encryption standard (AES) and elliptic curve cryptosystem (ECC) are required. We implemented a security system on chip that includes the AES and ECC modules, and we then verified. The implemented cryptographic modules have a good performance when compared to other research results.

I. INTRODUCTION

Wireless access in vehicular environments (WAVE) [1] is an intelligent transport system (ITS) communication standard, which is a modification of the wireless local area network (WLAN) that is designed to be suitable for the vehicular environment. It provides a seamless two-way communication through the antennas installed on the highway with vehicles even at high speeds of 200 km/h. This makes it possible to receive traffic information on traffic jams, constructions on the road, etc., in real time. In addition, it provides convenient services such as internet surfing in vehicles.

Because of WAVE, the quality of the traffic system and users’ convenience may improve, but privacy problem and accidents caused by misinformation should also be considered. Security is essential, and so as to prevent these issues, the WAVE standard requires security services such as the advanced encryption standard (AES) [2] and elliptic curve cryptosystem (ECC) [3].

AES is a cryptographic algorithm specified by the National Institute of Standards and Technology (NIST) in 2001. ECC is a public-key cryptographic algorithm proposed by Victor Miller in 1986 and Neal Koblitz in 1987, and is based on the elliptic curve discrete logarithm problem. In the WAVE standard, AES operates in the counter with CBC-MAC (CCM) block mode [4] to ensure the confidentiality and integrity of the data communication. Elliptic curve digital signature algorithm (ECDSA) [5] and

elliptic curve integrated encryption scheme (ECIES) [6], which are algorithms based on ECC, are used as a digital signature and public key encryption algorithm. The cryptographic intellectual properties (IPs) of the AES and ECC are essential for the WAVE modem, and they must have high throughput for high-speed communication. ECC requires a lot of computation in particular, so its efficient design is important. Moreover, the WAVE standard requires ECDSA over two NIST prime fields, P256 and P224, so the ECC module within the WAVE modems can perform the finite field operations over two kinds of prime fields.

In this paper, we propose a security system on chip (SoC) for WAVE and high-speed cryptographic IPs. One of the cryptographic IPs, the AES module, is designed to have a high throughput speed between 500 Mbps and 1 Gbps. While the other cryptographic IP, the ECC module, can perform ECDSA and ECIES over P224 and P256. Our SoC includes both these IPs and is implemented using the 180 nm technology library, which produces a better performance by our cryptographic IPs when compared to other research results.

This paper is organized as follows. In Section 2, the security services defined in the WAVE standard, and the details of the AES and ECC algorithms are presented as preliminary information. We describe the design of our SoC and cryptographic IPs in Section 3. Section 4 show the implemented results and experimental environment, and we conclude this paper in Section 5.

II. PRELIMINARY

In this section, we first show the security services defined in WAVE and then present their details.

A. Security services defined in WAVE

A set of security services for confidentiality assurance, authentication, key exchange, etc., is defined in IEEE 1609.2 [1] and is shown in Table I.

TABLE I.

Cryptographic algorithm required in WAVE.

Required function Cryptographic algorithm

Key length/ finite field

Message encryption AES-CCM 128-bit Digital signature

generation/verification ECDSA P224 & P256

Key exchange ECIES P256



High-speed WAVE Security Chip

Piljoo Choi, Hyun Il Kim, Ryang Ki and Dong Kyue Kim1 Department of Electronic Engineering, Hanyang University



B. AES AES supports encryption with 128-, 192- and 256-bit key,

and WAVE requires an encryption with 128-bit key. Each 128-bit message block is encrypted or decrypted through four transformations, which are shown in Table II.

TABLE II.

Four transformations in AES.

Transformation Decryption

ByteSub Non-linear byte substitution

MixColumn Combination of each column using linear transformation

ShiftRow Cyclical shift of each row

KeyAddition Exclusive or (XOR) operation with the round key

There are various modes of operation for cryptographic

block ciphers such as counter (CTR) and cipher block chaining (CBC). Counter with CBC-MAC (CCM) is one of modes and is used for the AES block cipher in WAVE. The CCM mode is a combination of the CTR and CBC modes. The CTR and CBC modes that operate in the CCM mode are used for message encryption and message authentication code (MAC) generation, respectively. In the CTR mode, the encrypted initial vector with a counter is used for encrypting plain texts or decrypting cipher texts. In the CBC mode, only plain texts are used for generating MAC. Thus, the AES module itself is required to only perform encryption in the CCM mode.

C. ECC and cryptographic protocols based on ECC a. ECC

In WAVE, two NIST prime fields, P224 and P256, are used. The elliptic curve over P224 and P256 consists of points that satisfy the following equation,

(1)

and a point at infinity. Using points on the elliptic curve, EC point addition (ECPA) and EC point doubling (ECDA) are defined. These points can be expressed as follows:

P (x1, y1) + Q (x2, y2) = R (x3, y3). (2)

If P and Q are different points, the operation is ECPA; otherwise, the operation is ECPD. –R (–x3, y3) is another point where a straight line passing through P and Q in ECPA or a tangent on P (= Q) in ECPD meets the elliptic curve.

TABLE III.

EC Point addition (ECPA) and point doubling (ECPD).

Point addition,

Point doubling,

Table III shows the calculation details for ECPA and ECPD. The expressions in Table III are performed over a finite field, so the ECC module should be able to calculate modular multiplication (MM), modular inverse (MI), modular addition (MA) and modular subtraction (MS). By repeating ECPD and ECPA, EC point multiplication (ECPM) can be performed and is the main operation of ECDSA and ECIES. b. ECDSA and ECIES

The ECC-based cryptographic algorithms used in WAVE are ECDSA and ECIES. ECDSA is a public key digital signature algorithm using elliptic curve cryptography and is specified in FIPS 186-3. The details of the signature generation and verification are shown in Table IV.

TABLE IV.

ECDSA digital signature generation and verification.

Signature Generation Signature verification

Input m: message d: private key

m: message Q: public key (r, s): signature

Algorithm

1. Select a random integer k in the interval (1, n)

2. kG = (x1, y1) 3. r = x1 mod n

If r = 0 then go to step 1 4. e = H(m) 5. s = k-1 mod n

If s = 0 then go to step 1

1. e = H(m) 2. w = s–1 mod n 3. u1 = ew mod n

u2 = rw mod n 4. (x1, y1) = u1G + u2Q 5. v = x1 mod n

Output (r, s): signature 1 iif v = r, 0 otherwise

ECIES is the public key encryption algorithm based on

elliptic curve Diffie–Hellman (ECDH). In WAVE, ECIES is used to securely transmit the secret key, which is used in AES. In ECIES, a point is shared using ECDH, and its x point and some shared parameters are derived as a key using a key derivation function. The derived key is used to encrypt the AES key and to generate its MAC. As a result, while transmitting the AES key using ECIES, its confidentiality and integrity is guaranteed.

III. PROPOSED SECURITY SOC FOR WAVE

In this section, we show the structure of the proposed security SoC and explain the design of our AES module and ECC module. A. Structure of Security SoC for WAVE

The security SoC includes the AES and ECC modules, which are connected through a bus to the core, memories, and peripherals. The structure of the proposed security SoC for WAVE is shown in Fig. 1.


Fig. 1. Structure of security SoC for WAVE.

Cortex-M0 and AMBA AHB are used as a core and a bus, respectively. The universal asynchronous receiver and transmitter (UART) module is used to communicate with the personal computer (PC) that acts as a server for SoC verification. The ROM has a firmware for the AES and ECC modules operation. When the AES and ECC module are practically used for WAVE, an SoC similar to Fig. 1 may be connected to a WAVE modem chip through other communication methods instead of a UART module, or only cryptographic IPs may be directly embedded and connected with the bus in a WAVE chip. B. Structure of AES module

The structure of the AES module in Fig. 1 is shown in Fig. 2.

Fig. 2. Structure of AES module.

A total of 20 Sboxes are fully used, thus only 13 clock cycles are consumed to encrypt a single message block. The AES module for WAVE operates only in CCM mode, thus only encryption is necessary as explained in Section 2-B. As a result, the AES module in Fig. 2 does not include inverse Sboxes, inverse MixColumns, etc. When the AES module is connected to the bus, an AMBA AHB slave wrapper is added to the interface of the AES module. C. Structure of the ECC module

We first show the entire structure of the ECC module, and then explain the design of the MM module, which has an influence on the entire performance of the ECC module.

a. Structure of ECC module

The structure of the ECC module in Fig. 1 is shown in Fig. 3. The ECC module consists of registers, control logic, and three submodules for modular operations. The main registers are as follows: D0 and D1 store the inputs of the submodules; X0, Y0, X1, and Y1 store the two points on the elliptic curve; and T0, T1, and T2 are the temporary storage required for computing ECPA and ECPD. By controlling the inputs and outputs of the submodules, the control logic computes ECPA and ECPD, which are repeated to compute ECPM.

Fig. 3. Structure of ECC module.

Among all modular operations, both MM and MI require a high number of computations. Our MI module is based on the modified right-shift binary inverse algorithm in [7], and our MM module is based on the word-based Montgomery product [8], [9]. If the processing speed of an MM module is faster than that of an MI module, the MI can be replaced with several MMs. However, the processing speed of our MM module is about four times faster than that of our MI module. Under such conditions, the replacement method is not efficient. As a result, the structure of our ECC module is simpler than an ECC with the replacement method.

Our MM module is designed to be simpler than other MM modules based on the word-based Montgomery product, by utilizing the characteristics of the modulus p over P224 and P256. We explain the details of our MM module in the next subsection. Similar to the AES module, an AMBA AHB slave wrapper is added to the ECC module in Fig. 3 to connect with the bus. b. Structure of Modular Multiplication module

The structure of the MM module is shown in Fig. 4.

Fig. 4. Structure of modular multiplication module.


Using a single 32-bit × 32-bit multiplier, the multiplication and reduction is repeated word-by-word. Its detailed operations are shown in Algorithm 1 where w is the number of words for both input and output data. The w for P224 and P256, are seven and eight, respectively. The P0 and P1 registers that were inserted for pipelining in Fig. 4 are omitted in Algorithm 1 for the sake of simplicity.

Algorithm 1 MontMult(X, Y)

Input: X = {Xw – 1, ..., X1, X0} Y = {Yw – 1, ..., Y1, Y0}

Output: X × Y × 2–n mod M

1 : 2 : 3 : 4 : 5 : 6 : 7 : 8 : 9 : 10 : 11 : 12 : 13 : 14 : 15 : 16 : 17 :

S = {Sw – 1, ..., S1, S0} = 0 A = 0 c = 0 for i = 0 to w – 1

{c, S1, A} = X0 × Yi + {S1, S0}; for j = 1 to w – 2

{c, Sj + 1, Sj – 1} = Xj × Yi + {Sj + 1, Sj} + {c, Rj} end for {Sw – 1 , Sw – 2} = Xw-1 × Yi + {Rw, Sw – 1} + {c, Rw – 1} if(M = n)

A’ = A × n’ mod 232 // n’ × n = –1 (mod 232) {c, S0, T} = n0 × A’ + {S0 32) for j = 1 to w – 1

{c, Sj, Sj – 1} = nj × A’ + {Sj, Sj – 1} end if

end for Return S

Algorithm 1 shows the iteration of adding X × Yi to S and

right-shifting S by 32-bit where Xi is the (i+1)-th word of X, and X0 is the least significant word. Before the 32-bit right shift, we need to find q that satisfies R = A + q × M = 0 (mod 232), where M is a modulus and A = S0 + X0 × Yi mod 232. There are two moduli p and n, in the NIST elliptic curve. Depending on which modulus is used, the method to find q is different.

[Case 1: the modulus is p] Over P224, p = 2224 – 296 + 1,

so q = 232 – A mod 232, and over P256, p = 2256 – 2224 + 2192 + 296 – 1, so q = A. Since R0 is always zero, only Rj for 0 < j ≤ w is required.

TABLE V.

Rj (1 ≤ j ≤ w) for non-zero A.

j M 8 7 6 5 4 3 2 1

p (P256) A – 1 ~A + 1 A 0 0 A 0 1 p (P224) - ~A 232 – 1 232 – 1 232 – 1 A 0 1

n 0 0 0 0 0 0 0 1

Table V shows R when A is not zero, where ~A is the

one’s complement of A. When A is zero, R is zero as well. Lines 10-14 of algorithm 1 are for modulus n, hence they are not executed.

[Case 2: the modulus is n] According to the reduction method of the normal Montgomery production, q = A’ = A × n’ mod 232 where n’ × n = –1 (mod 232). q is expressed as A’ in Algorithm 1 as q is stored in the register for A. We can see that A’ × n + A = (A × n’) × n + A = A × (–1) + A (mod 232) = 0 (mod 232). Before adding A’ × n to S, S is already right-shifted, so the least significant word of A × n’, T is ignored. When A is not zero, A + T = 232, i.e., A + T is not zero. To consider the carry from A + T, R1 = 1 and Rj = 0 (1 < j ≤ w) for non-zero A, and R = 0 for A = 0.

A single clock cycle is consumed in each of line 5, 7, 9, 11 and 14 of Algorithm 1. Since lines 7 and 14 are repeated w – 2 and w – 1 times, respectively, Case 1 and Case 2 consume w2 and w × (2w+1) clock cycles, respectively. In Fig. 4, P0 and P1 are inserted to reduce the critical path. Including the clock cycles for this pipelining and two cycles for the start and end signals of the MM module, the total consumed clock cycles are shown in Table VI.

TABLE VI.

Clock cycles for MM.

Modulus is p (w2 + 3)

Modulus is n (w×(2w + 2) + 3)

P256 67 147

P224 52 115

IV. IMPLEMENTATION AND CHIP VERIFICATION A. Implemented results

Using the 180 nm technology library, we implemented our security SoC for WAVE.

TABLE VII. Performance of AES and ECC module @ 100 MHz.

AES ECC (P224) ECC (P256)

Area 21 k GE 91 k GE

Throughput 0.98 Gbps 625 ECPM/s 526 ECPM/s

Table VII shows the area and throughput of the AES and

ECC modules when they are synthesized at 100 MHz. As the AES module needs 13 clock cycles to encrypt a message block, its throughput is about 1 Gbps. In WAVE, AES operates in the CCM mode, which is a combination of the CBC and CTR modes that halves the throughput into about 0.5 Gbps. This occurs only when a single AES module is included. When two AES modules are used, each message block can be processed in the CBC and CTR modes in parallel without having to halve the throughput.

The processing time for ECPM is 1.6 ms and 1.9 ms over P224 and P256, respectively. Hence, the ECC module can compute 625 and 526 ECPM per second over P224 and P256, respectively, as shown in Table VII. According to the finite field (P256 or P224), only the iteration number of some lines in Algorithm 1 and the values of Rj (1 ≤ j ≤ w) are different, thus the overhead area is very small.


TABLE VIII. Performance comparison of our ECC module.

Area Time for ECPM (ms)

Freq. (MHz)

Technology (or device)

This work 91 k GE 1.9 100

180 nm 112 k GE 0.95 200

[10] 120 k GE 2.68 137.7 130 nm [11] 122 k GE 1.01 556 130 nm [12] 34.6 LUTs 2.26 160 Virtex 5 [13] 197 k GE 1.21 208 130 nm [14] 189 k GE 1.45 316 55 nm

Table VIII compares the synthesized results of our ECC

module with other research. Normally, as the area increases, the maximum operating clock frequency decreases after layout (place and route). For a fair comparison and as our module is synthesizable at 200 MHz, the results at 200 MHz are included and are shown to be better than the results of other ECCs in Table VIII. Since the ECC module in [10], [12], [13], [14] can compute ECPM over dual-field, their area may become smaller if the logic to compute ECPM over binary field is removed. Even after taking this into consideration, the area of the ECC module in [13], [14] is still 1.69-1.76 times larger than ours, and the processing time of the ECC module in [10] is more than twice as large as ours. The ECC module in [11] has a slightly longer processing time and a slightly larger area than ours, but its operating clock frequency is faster, thus its dynamic power may be significantly higher compared to our module. The ECC module in [12] is implemented in FPGA, so we are unable to directly compare its area to our module, but its processing time is more than twice as large as ours.

B. Chip verification

To verify our implemented chip, we used the test board shown in Fig. 5.

Fig. 5. Test board for chip verification.

The chip on the test board is connected to the PC through

a UART, and we verified that it operates normally at 100 MHz.

V. CONCLUSION

We designed and implemented a security SoC that includes the AES and ECC modules, which is required for WAVE. The AES and ECC modules embedded in the security SoC are speed-oriented designed. Our AES module

can encrypt a message block in the CCM mode with a speed of 0.5 Gbps, which can be doubled when two AES modules are used in parallel if required. Our ECC module can perform ECDSA and ECIES over the NIST prime fields, P224 and P256, and has a better performance compared to other ECC modules. The operation of the implemented chip is verified at 100 MHz. It is expected that our security SoC or only the cryptographic IPs are used to support security functions required for WAVE.

ACKNOWLEDGMENT

This work is supported by IDEC.

REFERENCES

[1] ITS Committee, "IEEE standard for wireless access in vehicular environments-security services for applications and management messages,” IEEE Vehicular Technology Society 1609.2, Apr. 2013.

[2] Standard, NIST-FIPS “Announcing the advanced encryption standard (AES),” Federal Information Processing Standards Publication 197, vol. 197, pp. 1-51, Nov. 2001.

[3] Miller, Victor S. "Use of elliptic curves in cryptography," Conference on the Theory and Application of Cryptographic Techniques, pp. 417-426, 1985.

[4] Morris Dworkin, “Recommendation for Block Cipher Modes of Operation: The CCM mode for authentication and confidentiality,” US Department of Commerce, Technology Administration, National Institute of Standards and Technology, May 2004.

[5] Kerry, C. F and C. R, “Digital signature standard (DSS),” Federal Information Processing Standards Publication 186-4, July 2013.

[6] IEEE Std 1363a, “IEEE Standard Specifications for Public-Key Cryptography-Amendment 1: Additional Techniques,” Mar. 2004.

[7] Piljoo Choi, Dong Kyue Kim, "Design of efficient modular inversion module using resource sharing," Conference Proceedings MITA 2015, pp. 298-299, Tashkent, Uzbekistan, Jun. 2015.

[8] Peter L. Montgomery, "Modular multiplication without trial division." Mathematics of computation, vol. 44, pp. 519-521, 1985.

[9] Hyun Il Kim, Dong Kyue Kim, "Design of hardware ECC for various environments," Master's Thesis Hanynag University, Feb. 2017.

[10] A. Satoh, K. Takano, "A scalable dual-field elliptic curve cryptographic processor, " IEEE Transaction on Computer, vol.52, no.4, pp. 449-460, Apr. 2003.

[11] Gang Chen, et al, "A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over GF(p) Based on a Systolic Arithmetic Unit," IEEE Transactions on Circuit and Systems, vol. 54, no. 5, pp. 412-416, May 2007

[12] Hamad Marzouqi, et al, "A high-speed FPGA implementation of an RSD-based ECC processor,"


IEEE Transaction on VLSI System, vol. 24, no. 1, pp. 151-164, Jan. 2016.

[13] Jyu-Yuan Lai, et al, "A highly efficient cipher processor for dual-field elliptic curve cryptography," IEEE Transactions on Circuit and Systems, vol. 56, no. 5, pp. 394-398, May 2009.

[14] Zilong Liu, et al, "An efficient and flexible hardware implementation of the dual-field elliptic curve cryptographic processor," IEEE Transaction on Industrial Electronics, vol. 64, no. 3, pp. 2353-2362, Mar. 2017.

Piljoo Choi received the B.S. and M.S. degrees in Electronic Engineering from Hanyang University in 2010 and 2012, respectively. He is currently a Ph.D. candidate in the Department of Electronic Engineering at Hanyang University, Korea. His research interests are in the areas of security SoC (System on Chip),

crypto-coprocessors, and information security.

Hyun Il Kim received the B.S. and M.S. degrees in Electronic Engineering from Hanyang University in 2015 and 2017. He is currently a master’s student in the Department of Electronic Engineering at Hanyang University, Korea. His research interests are in the areas of crypto-coprocessors.

Ryang Ki received the B.S. degrees in Electronic Engineering from Hanyang University in 2017. She is currently a master’s student in the Department of Electronic Engineering at Hanyang University, Korea. Her research interests are in the areas of crypto-coprocessors, and functional safety.

Dong Kyue Kim received the B.S., M.S. and Ph.D. degrees in Computer Engineering from Seoul National University in 1992, 1994, and 1999, respectively. From 1999 to 2005, he was an assistant professor in the Division of Computer Science and Engineering at Pusan National University. He is currently a full professor in the Department of

Electronic Engineering at Hanyang University, Korea. His research interests are in the areas of security SoC (System on Chip), crypto-coprocessors, and information security.


Abstract - A patch-clamp circuit of removing the offset with reduced noise was designed and checked in the condition of measuring the ionic current for detecting the passage of DNAs through nano-hole. The significant reduction of noise according to the measurement condition was observed whether the shielding cage surrounds or not, reminding the importance of the extra care for checking the level of the noise. The separation of the command voltage with high input impedance enables the maintenance of the same potential across the counter electrode and the working electrode. The noise level was measured to be around ~ nA, rather higher than the level of the measurement of the DNA passages. The tuning of the offset voltages is needed depending on the electrolyte condition, too.

I. INTRODUCTION

The identification of the sequence of DNAs becomes more demanding in many fields of the biological application. Even though the time for the DNA sequencing gets shorter, the faster identification is still more desirable. The biological comparison of each acid base in DNAs is based on the comparison with the reference peaks of DNAs. Recently the possibility of the electrical characterization of the DNA bases has been suggested by checking the current of the DNA passage through the nano-hole. With the integrated chip with nano-holes in the solution containing the amplified DNAs, the events of the passage of DNAs through the holes result in the current pulse with the typical heights and widths depending on the driving force in the solution. The low level of the current around ~100pA with 100us of the pulse width requires less noise for reliable determinations. In addition, the offset voltage in the electrolyte solution demands the offset canceling for the better resolution in the measurement setup. Because the voltage can change with the formation of the double layers between the electrodes in the electrolyte, the active clamping of the voltage is crucial to identify the ionic current, requiring a patch-clamp amplifier. In case of patch-clamp, voltage or current are targets of clamp for controlling. The integration of patch-clamp circuits with the offset canceling and reduced noise will enable the fast

identification of DNA sequencing by optimizing the measurement signals.

Fig. 1. Schematic diagram of a biosensor consisting of a nanopore in a capacitor membrane, and molecular dynamics of DNA translocation through the pore.[2]

Fig. 2. Examples for identifying DNAs through nano-pore by current measurement.[1] The wider bandwidth with less noise needs a compromise

between the speed and the resolution. The left figure of Fig. 1 denotes the measurement scheme of the ionic current by DNA passages through the nano-holes. Depending on the cis or trans configuration of DNAs, series of the current pulse can be varied owing to the alteration of DNA bases in DNAs. For avoiding the unexpected built-in potential or the spurious current around the conducting substrate, the surface of the chips should be passivated by insulating layers as depicted as yellow lines. The right figure illustrates the step



A Patch-Clamp for detecting the DNA passage

Young Sun Moon1 and Gyu-Tae Kim2a

Department of Micro/Nano System, Korea University1 Department of Electrical Engineering, Korea University2 E-mail : sjoyfuls@ korea.ac.kr, [email protected]


of the DNA passages through nano-hole. For the higher resolution of the signal, the speed of the passage through the hole should be controlled or monitored with better SNR. The slower speed of the passage makes it easy for identifying the acid base from the electrical signal.

(a)

(b)

Fig. 3. (a) Conventional patch-clamp amplifier setup for detecting DNA passage through the nanopore. (b) Schematics of the patch-clamp designed for Integrated Circuits: headstage, voltage-gain difference amplifier, and track-and-hold circuit. In Fig. 2, Dunbar group et al reported the current pulses with the level of the current pulse about ~125pA and the duration about 200us. Because the DNAs are composed of two helical chains, it should be stripped into single chains with a radius of 1.0nm to enable the passage through nano-holes. One nucleotide unit was measured to be 0.33nm, and comprises the DNAs with millions of nucleotides. Assuming one million number of bases along a DNA chain, the 200us of the current pulse should be distinguished in the interval of 0.2ns, which is not so easy for clearly identifying each base pair owing to the finite bandwidth of the amplifier. So the slowing down of the passage speed of DNA chains through nano-hole are desirable for the better identification. Because the electric field is the main driving force, the alteration of the distribution of the electric field with time can be a good strategy for controlling the speed. The slowdown of DNA passages with wider bandwidth but less noise level is still challenging as an electrical identification tool of DNA sequence. In this report, we reproduced the patch-clamp

circuit with less noise and offset canceling following Kim et al[1]. The common mode noise can be rejected by adopting the differential scheme of the input amplifiers. By proper choice of the amplification factor, the compromise between the speed and the better resolution can be optimized.

(a)

(b)

Fig. 4. (a) Circuit of differential amplifier adopted in our circuit design. (b) Layout of the Patch clamp circuit in the Virtuous.

II. EXPERIMENTS

In our studies, we followed the scheme of Kim et al by the MPW MS350-1502 of IDEC. The function of the patch-clamp amplifier was checked by using the Arduino Pro Mini for generating the pulses of the stimulus signal and NI DAQ as an oscilloscope for monitoring the current level. The spectral response of the amplifier was measured inside or outside of the shielding chamber for comparing with the environmental noise. The signal was compared with the conventional patch-clamp from AXON Instrument.

A. Design of the circuit Fig. 3 (a) denotes the situation of the DNA passage through nano-hole by the potential of VCMD with the conversion of the current to the voltage followed by the amplification of the voltage signal. Owing to the equipotential feedback between the inverting and the non-inverting terminal of the op amp A1, a driving electric force with the potential of


VCMD moves the dipole of the DNAs between EREC and EREF. The output voltage is derived as Eq. (1) with the canceling of the offset voltage and proportional to the input current. By tuning the ratio of the resistances, the proper amplification factor can be set.

(a)

(b)

Fig. 5. (a) Test PCB for checking the response of the amplifier. (b) NI DAQ for monitoring the output voltage from the circuits.

….. (1)

Fig. 3 (b) is the design we have adopted for the

patch-clamp circuit following Kim et al. The patch-clamp circuit is composed of the headstage, the voltage-gain difference amplifier (VGDA), and Track-and Hold circuit. By applying the enabling or disabling signal to the switching transistors of SH, the circuit switches between the transconductance amplifier and signal capturing circuit. Depending on the threshold voltage of transistors, the proper level of the gate voltages to the transistors should be chosen. In our checks, the function of the transconductance amplifier was good but without the proper function of the signal capturing, which should be improved in the next design. Fig. 4 depicts the steps which have done by using the Virtuoso Schematic Editor, Spectre, and Calibre. Pre-simulation and post-simulation were done for

comparing with the signal from the fabricated chip. For the design of the buffer, the schematic of Fig. 4 (a) was adopted in a differential input with less influence from common-mode noises. Fig. 4 (b) shows the layout of the chips containing three patch-clamp trans-conductance amplifiers and three op-amps. The successful operating part of the circuit was about 1/3, probably damaged during the measurement of the characteristics. In some cases, the failures of the circuit after the measurement were also observed, indicating the susceptible to the electric shock by electrostatic discharges. The protection scheme from the electrostatic shock should be considered in the next design.

(a)

(b)

Fig. 6. (a) Pre-Layout simulation result of the patch-clamp circuit as in Fig. 3. (b) Output voltage vs input current in patch-clamp circuit as in Fig. 3(b).

The fixed ratio of the resistances should have been

designed by some steps for checking the level of the signal. B. Test condition of the circuit The chip was packaged in a form of LQFP and mounted as in Fig. 5 (a). The left side of the chip contains three patch-clamp transconductance amplifiers with three op-amps at the right side. The Vcc was applied by the voltage source with the level of 3.3V and the voltage signal was monitored by the NI DAQ with the bandwidth of 10kHz. For simple check of the function, the buffer circuits at the right sides were checked in the measurement of buffering scheme. The overall signal was compared with the pre- or post-simulation results fro


m the Virtuous. The input current of 1 uA was applied with the voltage source of 1V and the 1MΩ resistor connected to the input port of the patch clamp or the buffer circuit. The driving digital signal fed into SH was generated by the 3.3V standard Arduino Pro Mini, which can be also possible to operate with 3.0V of mercury battery.

(a)

(b)

Fig. 7. (a) Cis and trans of patch-clamp system for DNA detection through nanopore by current measurement. (b) Axon DAQ system for current measurement.


A good linear dependency between the input current and the output voltage is desirable for the identification of the current as shown in Fig. 6 (a). In spite of differential input condition in circuit design, the apparent shift of the output voltage in Fig. 6 (a) was expected, which can be understood by the single ended configuration of the measurement. In the experiment, similar shift of the output voltage was also observed. For the better resolution, the check of the differential voltages between the output voltage and VCMD should be done.

Fig. 6 (b) shows the output voltage from the patch-clamp circuit, nicely fitting to the pre-layout simulation in Fig. 6 (a). The negative slope of the output voltage just comes from the opposite definition of the current direction for the measurement. In real situation with DNA passages through nano-holes, the direction of the current flow should be defined by the case of Fig. 3 (a).

(a)

(b)

Fig. 8. (a) Comparison of background voltage signal depending on the power mode (b) Noise power spectrum of the Patch Clamp Circuit.

To check the noise level of the system, we checked the

signal level in the setup of the nanopore measurement as shown in Fig. 7. Fig. 7 (a) shows the probes for the detection of the ionic current resulting from the passage of DNAs and Fig. 7 (b) the measurement setup with Axon DAQs and patch-clamps. The headstage was positioned inside the metal shield cages for reducing the environmental noises, which was confirmed to be very effective for removing the power-noises. The low-pass filter with a corner frequency of 10kHz was also efficient to remove the high frequency noises.

Proper choices of the filter were also important to achieve higher S/N ratio. Because low corner frequency of the low-pass filter can cut the signal pulse or deform the shape of the signal, signal analysis with the filter setting seems to be required.

Fig. 8 (a) shows the significant reduction of the background noise whether the DC adapter or the battery powered. In case of DC adapter, 30times bigger noise level with 60Hz frequency component was observed. With the use of the metal-shield case and the battery power, much reduced noise level was achieved as shown in Fig. 8 (b).

In Table 1, we can clearly see a big advantage of noise reduction by smaller standard deviation of the output signals. So proper shielding with metal-cages and proper grounding will be very helpful for assessing the low level measurements.

But, the noise power spectrum shows much higher levels than the best target value of [1], which should be improved for ultra-low sensitive measurements.


TABLE I Statistics on the background voltages from the Patch Clamp Circuit

depending on the power mode

Power Mode Average Voltage (V)

Standard Deviation (V)

DC Adapter 0.9824 0.19717

Battery 0.99798 0.00679

IV. CONCLUSIONS By IDEC processes, we fabricated the patch-clamp

transconductance circuit suggested by Kim et al. A good linear dependence of the input current with the output voltage was confirmed with reduced noise level in the battery-powered and metal-shielded condition, still requiring the improvement of the noise level. Owing to the difference of the design rule such as threshold voltages, the voltage tuning for on/off of the switching transistors was rather difficult, which should be considered for the complete operation of the circuit.

ACKNOWLEDGEMENT

This work was supported by the IDEC.

REFERENCES

[1] J. Kim, K. D. Pedrotti, and W. B. Dunbar, “A patch-clamp ASIC for nanopore-based DNA analysis”, IEEE Trans. Biomed. Cir. & Systems, vol. 7. no. 3, pp. 285-295, Jun 2013.

[2] Gracheva, M. E., Xiong, A., Aksimentiev, A., Schulten, K., Timp, G., & Leburton, J. P., “Simulation of the electric response of DNA translocation through a semiconductor nanopore-capacitor”, Nanotechnology, vol. 17. no. 3, pp. 622-633, Jan 2006.

Gyu-Tae Kim received B.S, M.S and PhD degree in Physics from Seoul National University in 1992, 1996 and 2000. During 2000-2002, he worked as a Humboldt Fellow at the Max-Planck Institute for Solid State Physics in Stuttgart. In 2002, he joined the faculty of Electrical Engineering, Korea University. His research interests include emerging

electronic devices such as low-dimensional nanoscale electronic devices, and organic electronic devices.

Young-Sun Moon received B.S degree in electrical engineering from Korea University, Seoul, Korea, in 2013, where she is currently working toward the Ph.D. degree in micro/nano systems. Her research interests include 2-dimensional field effect transistors, and tunneling effect.


Abstract The high-efficiency NFC AFE(Analog Front-End) was proposed and implemented in 65nm CMOS process. We proposed the novelty architecture of Envelope Detector which is the most important block in passive mode tag because those generate their own power. The Envelope Detector generating negative voltage and it can generate the negative voltage of -0.68V that is used for body bias and can detect the small voltage swing of 0.5V. The area of the high-efficiency NFD AFE is 1.9mmx2mm and it is very small compared with the conventional NFC AFE. The digital part of NFC is also verified by FPGA board. So the proposed NFC tag is feasible for many applications.

I. INTRODUCTION

Wireless power transfer has broad applications from mobile phone chargers to biomedical implants [1]. NFC(Near field Communication) is wireless technology that enables the variety of additional services including the transceiver within 20cm at 13.56MHz band and equipped in mobile communication terminal. NFC does not require physical contact, and therefore, it allows more convenient access for information delivery [2]. A number of multi-media equipment like digital camera, personal computer, PMP, and MP3 Player, Samsung pay and white pay have adopted the NFC technology nowadays. [3] ISO(International Organization for Standardization) sets the various standards of NFC and RFID depending on types and modulations based on the standards as shown in TABLE I [3-5].

TABLE I

Modulation specification of 13.56MHz RFID and NFC

ASK(Amplitude Shift Keying) modulation on TABLE I is

adopted in many communication systems such as NFC and RFID(Radio Frequency Identification) [6]. The ASK modulations is different according to ISO standard types, different circuits should be used when the signal is demodulated from Tag. Tag takes charge of demodulation in analog part and memory block is in charge of digital part. Analogue part has its own power supply when Tag is on as active mode. However, in passive mode, if signal is sent wirelessly form the Reader, the power is self-generated by coupling through antenna made of inductor. Therefore, the role of AFE(Analog Front-End) is very important in passive mode tag. AFE block includes the low-voltage bandgap, the LDO(Low-Drop Out regulator) with the bias-boosted gain stage, and the adaptive dc limiter [2]. This paper proposed the AFE part that can demodulate every signal with ASK 8 ~ 100% modulation using 65nm CMOS process and verified its operation with the measurement of chip. The digital part that can process data are configured using FPGA. The operation of the NFC Tag is verified by linking the packaged chip and the digital part.

The remainder of this paper is organized as follows. In Section II, the proposed high-efficiency AFE of NFC Tag design is presented. The post-simulation results are described in Section III and experimental results are provided in Section IV. Finally, the conclusion is given in Section V.

II. HIGH-EFFICIENCY PASSIVE NFC AFE TAG DESIGN

A. Envelope Detector The AFE block diagram of the proposed high-efficiency

passive NFC Tag is shown in Fig. 1.

Fig. 1. AFE block diagram

of the proposed passive multi-mode NFC Tag

ISO Standard Data rate Modulation (Reader to Tags)

Modulation (Tags to Reader)

14443 Type A 106kbit/s ASK 100% ASK 10% OOK 14443 Type B 106kbit/s ASK 10% ASK 10% BPSK 18092 Passive 212kbit/s ASK 10% ASK 10%



High-efficiency analog front-end design of passive NFC tag based on 65nm

Jun-Beom Jang1 and Yong Moona

Department of Electronic Engineering, Soongsil University, Korea E-mail : [email protected]


When the Reader antenna and Tag antenna are within 10cm, signals are transmitted by inductor coupling of Tag antenna. The transmitted signal goes through matching network and is delivered to the DC rectifier and the envelope detector without any loss. The DC rectifier is the first block to incoming signal with amplitude changing depending on ASK modulation ratio is received and corrected by the relatively steady DC 2V voltage. In BGR (Band-Gap Reference), the DC Rectifier output, VDC is applied and steady DC voltage 0.67V is generated without the dependency to the surrounding temperature change. The regulator receives VDC and BGR output, VREF, and creates the steady 1V DC voltage that can operate with the demodulator and digital part. The Envelope detector output, VENV, and the regulator output, VDD, are entered to the demodulator and the demodulator demodulates the emitted signal to antenna.

Envelope Detector is used in various ways such as ET(Envelope-Tracking), AM radio receiver, and so on [9]. The proposed Negative Voltage Generating Envelope Detector is shown in Fig. 2 [3].

CENV

RENV

CDCM

ANT

ANT

VENV

VDCM

Fig. 2. Schematic of the proposed Negative Voltage

Generating Envelop Detector

As the proposed Tag has one input signal form ANT, it was designed to have single input compared with the conventional circuit. Also, the resistance, RENV, was added beside the capacitor, so the amplitude of VENV was increased by 55% compared with the conventional Envelope Detector that has no resistance [3], and it can detect the small voltage swing of 0.5V. Also, when ASK modulation is applied in Modulator block and the response signal was sent through antenna, minus voltage called VDCM can be generated to use

VDD to increase the output amplitude. After the simulation, maximum VDCM is about 0.68V. B. Voltage Limiter

The NFC Signal of 13.56MHz is received via the NFC antenna and generates the DC voltage through the DC Rectifier. The DC Rectifier in this paper is the Voltage Multiplier structure and it is composed of 4 stages to increase the distance between NFC Reader and NFC Tag. It could be possible to generate the stable DC voltage even though low voltage is applied. But if the distance between the NFC Reader and NFC Tag is in short and tag generates the large DC voltage, it may cause damage to the internal circuitry like Bandgap Reference and LDO Regulator. The Voltage Limiter is required to prevent damages to the internal circuit and its schematic is shown in Fig. 3.

When the output voltage of DC Rectifier is lower than the sum of the threshold voltage with M2, M3, M4 and the current flows through R, so it turns on M1. The size of the NMOS which is turned on is large when the current is discharged.

Fig. 3. Schematic of the Voltage Limiter

C. Bandgap reference and regulator

The conventional circuit of BGR and Regulator was used in this design, and those circuits were modified suitable for 65nm process and its schematics are shown in Fig. 4 [11]. The amplifier used in BGR and regulator was designed to have two amplification stages and the PNP transistor used in BGR is implemented in CMOS process using N-well.

Because the regulator output is easily changed according to the external temperature and environment, the output of the voltage Multiplier (VDC) is inappropriate as the power source for the internal circuit. The BGR circuit is suitable, because the output voltage is not sensitive to the changes in external temperature and environment.

(a) (b)

Fig. 4. (a) Schematic of BGR (b) Schematic of LDO Regulator

The LDO regulator is a circuit that provides accurate and stable DC voltage with small difference between input voltage and output voltage. The circuit consists of pass elements, the error amplifier, the reference circuit, and the feedback network. The regulator uses the bandgap reference VREF to provide the stable DC voltage.

D. Demodulator

The demodulator used the conventional circuit in this design and its schematic is shown in Fig. 5 [11]. In Fig. 5, VENV is the first input but starts to operate after the regulator output, VDD, is entered. VREF goes through the unit gain buffer and is the input to the amplifier and Schmitt trigger block. VENV goes through RC filter and only the rising edge and falling edge signals are entered to the amplifier [11].


The rising edge and falling edge are entered to the Schmitt trigger block and the Schmitt trigger demodulates them into square wave [11].

Fig. 5. Schematic of demodulator

E. Load Modulator

The Load Modulator circuit is shown in Fig. 6. It is composed of a NMOS and a MOS Capacitor. When the gate of the NMOS receive, the response signal of 847KHz from the Digital Block, it is connected the drain of the MOS connected antenna with the source of the MOS connected MOS capacitor, and it changes the amplitude of Reader signal.

Fig. 6. Schematic of Load Modulator

F. Power-On Reset circuit

The Power-On Reset circuit used in this work is shown in Fig. 7. The circuit for resetting the Digital Block after sending data and the response data between the Reader and the Digital Block is the Power-On Reset. It is composed of MOS Capacitor and Schmitt Trigger.

The output voltage of the DC Rectifier was used as the supply voltage of the Power-On Reset. The current mirror to control the amount of current was used on the Stage-3. Since the input of the Schmitt Trigger and the MOS Capacitor is connected, the current applied through the current mirror determines the reset wait time until the capacitor charging voltage goes the high switching point of the Schmitt Trigger.

After the reset, the data does not come from the Reader and the MOS Capacitor enters discharge state. This makes the switching point of the Schmitt Trigger pull down, it is possible to reset the high switching point when sending the data again.

Fig. 7. Schematic of Power-On Reset

G. Digital block

The digital block receives the signal passed through the ASK demodulator, converts thoes into data stream, and determines the response signal. It modulates the response signal, and transmits data to the load modulator. In this paper, FPGA is used to verify digital part with the designed NFC Analog Front-End. The digital block diagram for data processing is shown in Fig. 8.

Fig. 8. Block diagram of NFC digital part

In 14443 Type A standard, the signal transmitted from the

Reader to the Tag sends 1-frame data(8bits) as modified Miller-coded signal. For this reason, the digital block needs to convert the data through the Modified Miller-coded demodulator. The modified Miller coding signal discriminates 1 bit of data as 1 and 0 according to the position of the pulse appearing in 1 bit cycle. Fig. 9 shows the modified Miller coding signal [12].

Fig. 9. Modified Miller Code Signal


The modified miller coded signal always shows data 1 when the pulse signal comes after the half period for 1 bit period. However, the data 0 is different according to the value of the previous data. If the previous data value is 1 , the pulse is not displayed for 1 bit period. If the previous data value is 0 , the pulse signal comes before the half period for 1 bit period. One frame is composed of 8 bits. MSB and LSB are represented by SOF(Start Of Frame) and EOF(End Of Frame), which indicate the start and end of data. The Modified Miller code Demodulator determines the SOF and EOF of the data and demodulates the signals from SOF to EOF into data and stores it. The stored data is transferred to the next digital block, the Data Module.

The Data Module compares the data defined in NFC Protocol with the data received and defines the data and determines the corresponding response data. Unlike the input data, the response data consists of 2 frames and sends total 16 bits of data. The response data is also transmitted in the data defined in NFC protocol, and the tag ID and information are transmitted [12]. The response data is also modulated and transmitted to the load modulator of the AFE. The modulation of the response data is modulated by the ASK OOK(On & Off Keying) Modulator of the digital block. The modulation scheme of the response data is shown in Fig. 10.

Fig. 10. Scheme of response data modulation

The response data is modulated with the Manchester

code. In the Manchester code, when one bit is transmitted, the transition of voltage occurs at the center of each bit time. Therefore, the receiver can see the transmission speed only by looking at the transmitted signal. 1 is expressed as High to Low, and 0 is expressed as Low to High. The modulated response data is generated by signal transmitted to the load modulator through the 847KHz subcarrier frequency and the OOK modulation scheme. The subcarrier frequency is output when the modulated response data is high, and when it is low, output is 0. The modulated OOK signal is transmitted to the LM_IN of the AFE load modulator and the load modulator transmits the response signal to the reader via the antenna.

III. SIMULATION RESULTS The proposed high-performance passive NFC Tag was

designed using 65nm CMOS process and CADENCE Spectre was used for the verification.

The simulation results of the proposed Negative Voltage Generating Envelope Detector depending on ASK modulation value are shown in Fig. 11. By the simulation, it shows that 8 ~ 30% ASK modulation specifications were satisfied using the proposed NFC Tag.

(a)

(b)

(c)

(d)

Fig. 11. Simulation result of VENV and VDCM versus ASK modulation ratio (a) 8% (b) 10% (c) 20% (d) 30%


Fig. 12 shows the simulation result between the envelope detector with and without resistance RENV. According to the simulations, it showed that the proposed circuit operates better compared to the previous works [3].

Fig. 12. Simulation comparison result of the proposed Negative Voltage Generating Envelope Detector and conventional Envelop Detector

The simulation results for the operation of BGR,

Regulator, and Demodulator are shown in Fig. 13. According to the simulation, it shows that the waveform was demodulated correctly by constant VREF voltage.

Fig. 13. Simulation result of Demodulation

Fig. 14 is the simulation results of the Power supply

consist of DC Rectifier, Bandgap Reference, LDO Regulator and Power-On Reset.

The ASK signal of Modified Miller coding, RX_IN coming from the Reader goes in the DC Rectifier. It makes the output voltage of the ASK signal (RX_IN) which is entering low at this simulation.

Power-On Reset and Bandgap Reference is supplied with the output voltage of DC Rectifier (VDC). The Bandgap Reference outputs the constant voltage (VREF) and the Schmitt Trigger operates the reset function (POR_RST) after passing the charging time of the high switching point of the Schmitt Trigger.

After the LDO Regulator receives the VREF from the Bandgap Reference, VREG could be obtained through the Error Amplifier operation. It is used as the Power supply voltage(VDD) of the NFC Analog Front-End.

Fig. 15 is the simulation result of Demodulation operation. The ASK signal of Modified Miller coding,

RX_IN coming from the reader enters the proposed Envelop Detector for ASK 8 ~ 100% Modulation. RX_IN is the modulated 100% ASK in this simulation. VREC is the output of the Envelope Detector. VREC is passed through the filter, which enters the one input of the Comparator. The other input of the Comparator receives the VREF, the Comparator output (OUT_FILTER) is generated around the VREF. The comparator receiving the OUT_FILTER and VREF is connected to the Schmitt Trigger, which produces the demodulated Signal, OUT_DEMOD.

OUT_DEMOD goes to the interfacing buffer for the Digital Block. This operation is done by the PAD in this design. The Digital Block receives the data through the operation of demodulation and sends the response signal.

The Response signal of Manchester coding has the carrier frequency of 847KHz. Receiving the response signal can watch that the amplitude of the RX_IN changing at the rate of 847KHz.

Fig. 14. Simulation result of Power Supply


Fig. 15. Simulation result of Demodulation

IV. MEASUREMENT RESULTS

A. on-wafer measurement The chip measurement was conducted using the probing

test process in probe station and connection with the antenna is implemented with the resonant frequency of 13.56MHz. The size of the implemented ship is 1.9mm 2mm and the chip microphotograph is shown in Fig. 16.

Fig. 16. Chip microphotograph

The proposed NFC AFE receives the signals from the

Reader antenna by connecting the antenna which should be placed within 10cm distance. The Reader sends the regular

signals for Tag with the programmed communication protocols depending on ISO standard, the different waveforms with ASK 8% to 100% could be sent. The pictures of chip measurement and test result are shown in Fig. 17 and Fig. 18 respectively.

Fig. 17. Measurement environment

of the proposed high performance NFC AFE

(a) (b)

Fig. 18. Measured waveforms of high performance NFC AFE versus ASK modulation rate of reader (a) 30% (b) 50%

After the chip measurement, it shows that the

demodulation operation is verified correctly using the designed chip.

B. chip measurement

The package measurement was performed to the package and the FPGA, and the reader signal was input via the antenna. By implementing the operation of the digital block through the FPGA, NFC AFE was verified with digital block. The chip measurement environment and test result are shown in Fig. 19 and Fig. 20 respectively.

Fig. 19. Measurement environment of the NFC AFE package


(a)

(b)

Fig. 20. (a) Measured of NFC AFE ASK demodulator signal

(b) measured of FPGA response signal After the chip measurement, it shows that the proposed

NFC AFE operation is verified using the packaged chip.

V. CONCLUSIONS The high-efficiency passive NFC AFE is proposed and

implemented in 65nm CMOS process. We proposed the novel architecture of Envelope Detector that is most important block in passive mode Tag, because those generate their own power. The Negative Voltage Generating Envelope Detector is proposed and it can generate the negative voltage of -0.68V that is used for MOSFET body bias. Also it can detect the small voltage swing of 0.5V. The digital blocks capable of data processing were implemented in FPGA and is used for NFC AFE verification. The operation of the NFC AFE was verified on-wafer and the packaged chip in test environment. The area of the NFC AFE is 1.9mm 2mm and it is very small compared with the previously reported NFC AFE.

Since the proposed passive NFC AFE Tag has high efficiency in power and area, it is feasible to use the proposed tag for NFC applications for various wireless communication systems.

ACKNOWLEDGMENT This research was supported by the

project(NRF-201617221365) in the field of science and technology which was funded by the government(Ministry of Education) in 2016 and supported by the Korea Research Foundation. This work is supported by IDEC.

REFERENCES

[1] Yan Lu, Xing Li, Wing-Hung Ki, Chi-Ying Tsui, and C. Patrick Yue, “A 13.56MHz Fully Integrated 1X/2X Active Rectifier with Compensated Bias Current for Inductively Powered Devices,” IEEE, Solid-State Circuits Conference Digest of Technical Papers(ISSCC), pp.66-67, Feb. 2013.

[2] Jong-Wook Lee, Ngoc Dang Phan, Duong Huynh-Thai Vo, and Vinh-Hao Duong, “A Fully Integrated EPC Gen-2 UHF-Band Passive Tag IC Using an Efficient Power Management Technique,” IEEE Transactions on Industrial Electronics, Vol.61, No.6, pp.2922-2932, Jun 2014.

[3] Jung-Hyun Cho, and Peter H. Cole, and Shiho Kim, “An NFC transceiver using an inductive powered receiver for passive, active, RW and RFID modes,” IEEE, International SoC Design Conference (ISOCC), pp.456-459, Nov. 2009.

[4] Jung-Hyun Cho and Shiho Kim, “Design of single-chip NFC transceiver,” Journal of The Institute of Electronics Engineers of Korea (IEEK), Vol.44, No.1, pp.68-75, Jan. 2007.

[5] IDEC NEWSLETTER (http://idec.knu.ac.kr/), Vol.105, No.3, Mar. 2006

[6] Guangjie Cai, Alan Pun, David Kwong, and KC Wang, “A 2.4pj/bit ASK Demodulator with 100% Modulation Rate for 13.56MHz NFC/RFID Applications,” IEEE International Symposium on Circuits and Systems (ISCAS), pp.734-737, Jun, 2014.

[7] Hyun-Chul Shim, Chung-Hyun Cha, Jong-Tae Park, and Chong-Gun Yu, “Design of a Low-Power CMOS Analog Front-End Circuit for UHF Band RFID Tag Chips,” Journal of The Institute of Electronics Engineers of Korea (IEEK), Vol.45, No.6, pp.28-36, Jun. 2008.

[8] G.N. Jadjav and S.Hamedi-Hagh, “UHF class-4 active two-way RFID tag for a hybrid RFID-based system,” IEEE, RF and Microwave Conference (RFM), pp.337-342, Dec. 2011.

[9] Jooseung Kim, Seungbeom Koo, Yunsung Cho, Byungjoon Park, Kyunghoon Moon, and Bumman Kim, “Highly Efficient Envelope-Tracking Modulator Over Wide Output Power Range for Dual-Mode Power Amplifier,” IDEC Journal of Integrated Circuits and Systems (JICAS), Vol.1, No.1, pp.28-35, May. 2015.

[10] , CMOS (IDEC 42), 2ed ed. , Oct.

2010. [11] J.-W.Leel,2, D.H.T. Vol, and S.H. Hong, and 3Q.-H.

Huynh, “A fully integrated high security NFC target IC using 0.18um CMOS process,” IEEE, ESSCIRC, pp.551-554, Sep. 2011.

[12] NFC FORUM, “NFC Digital protocol Technical Specification” Vol.1, Nov, 2010


Jun-Beom Jang received the B.S. degree in electronic engineering from Soongsil University, Seoul, Korea, in 2016. He is currently working toward the M.S. degree in electronic engineering from Soongsil University, Seoul, Korea. His main interests include design of CMOS analog integrated circuit and NFC.

Yong Moon received the B.S., M.S, and Ph.D. degrees from the Depart-ment of Electronics Engineering, Seoul National University, Seoul, Korea, in 1990, 1992 and 1997, respectively. From 1997 to 1999, he was with LG Semicon co., Ltd., where he contributed to senior research engineer. Since 1999, he has been

with Soongsil University, Seoul, Korea, where he is a professor with School of Electronic Engineering. His research interests include PLL, low-power circuit, mixed signal IC and RF circuits.


Abstract - A low power wide-band low noise amplifier (LNA) is presented in 65 nm CMOS. A compact inter-stage network utilizing one transformer and a resistor is proposed to obtain ultra-wide bandwidth. The designed LNA achieves 1 - 13 GHz bandwidth with > 10 dB of power gain. The simulated noise figure ranges from 9.6 to 10.5 dB over 1-13 GHz with power consumption of 11mW at 1.2 V of power supply.

I. INTRODUCTION

Recently, growing research on reconfigurable multi-band-standard and ultra-wideband (UWB) systems has increased interest in broadband low-noise amplifier (LNA) design. A broadband LNA must have good input matching and low noise figure over a multi-GHz bandwidth (BW), while consuming low power. The primary objective in the design of the LNA is to suppress the additive noise at the subsequent stages and to achieve sufficiently large gain. In most systems, this objective should be achieved while constraining the LNA input to 50 Ω for impedance matching with external components such as an antenna or filter.

In order to achieve wideband impedance matching, a multiple-section bandpass filter with inductively generated common-emitter (CE) SiGe or common-source (CS) CMOS LNA have been proposed in [1] and [2], respectively. If the noise requirement is not that critical, a resistive shunt-shunt feedback or simply a resistive termination in parallel at the input of the amplifier can be considered with an improved linearity. The bandpass-filter-based UWB CG-LNA proposed in [3] reduces power consumption and improves the linearity compared to the UWB CS-LNA. However, the large number of inductors consumes large amount of area and also increases the noise figure. Using a common gate (CG) transistor for input matching is reported in [4]-[6], but the additional CS stage degrades the linearity and consumes more power. A differential UWB CG-LNA employs capacitive cross-coupling to reduce the noise figure [7], but this cross-coupling also increases the quality factor of the parallel RLC input network, which causes the decrease of the bandwidth. In addition, the presence of the resister has

an adverse effect on the amplifier`s noise figure in either way and suffers from potential instability though it has slightly better noise performance.

A big design challenge for UWB LNAs is wide bandwidth and the stringent linearity requirement over a wide frequency range due to the large numbers of in-band interferences in UWB system, and the cross-modulation/inter-modulation caused by blockers or transmitter leakage in a reconfigurable receiver. Furthermore, while fT increases with technology scaling, linearity worsens due to lower supply voltage and high-field mobility effects. Therefore, wideband linearization in deep-sub-micron CMOS process is a new trend. However, most of the linearization methods reported so far are aimed at the narrow band applications.

In this paper, we present a 1 – 13 GHz wideband LNA consisting of five stages. We propose a compact transformer-based inter-stage network which has comparable bandwidth enhancement ratio (BWER) compared with the π-type inductor peaking (PIP) network with much smaller area consumption. The five stages are cascaded, each of which utilizes drain and gate parasitic capacitances and a transformer with series resistor. A CG configuration with a biasing inductor at the source is used as the first stage to provide a wideband 50 Ω matching at the input while achieving a good linearity and a moderate noise figure. The LNA has three cascode amplifiers followed by the common drain (CD) buffer at the output stage. The designed LNA achieves a wide enough bandwidth to cover the whole 1 – 13 GHz frequency range, a 14.3 dB of maximum gain, and 9 dB of minimum NF having less than 11 mW of power consumption.

The paper is organized as follows. Section II presents the topology for 5-stage LNA. Simulation and measured results are presented in Section III. Conclusions are drawn in Section IV.



1-13GHz Wideband LNA utilizing a Transformer as a Compact Inter-stage Network in 65nm CMOS

Hyohyun Nam and Jung-Dong Parka

Division of Electronics and Electrical Engineering, Dongguk University, Seoul E-mail : [email protected]


Fig. 1. Schematic diagram of the designed wideband LNA.

Vin

Vb2

Vb1

Vout

Vb3M1

M2

M3

M4

M5

M6

M7

M8

M9

VDD

Vb1 Vb1 Vb1

Fig.2 Transformation of PIP to single Transformer with a resistor.

R3

LP1 LS1

R1

LD1

R2

LD2

II. PROPOSED 5-STAGE LNA

A. Design consideration of the proposed CG-LNA The general block diagram of front stage for the LNA is

shown in Figure 1, where a compact inter stage network utilizing only one transformer and a resistor is formed. A CG amplifier with a source inductor is used as the first stage. Since a source inductor is used to provide the bias current, the noise contribution is much lower than using a resistor.

The inductor at the source of M1 is designed to resonate out the node capacitance at the center frequency. With a desired 1 - 13 GHz bandwidth, the LC resonant frequency should be higher than this frequency to ensure stable circuit operation. However, a large inductor can lead to over-peaking of gain, and hence, circuit instability. As suggested by simulation, the circuit becomes unstable when the inductor exceeds ~ 1 nH.

B. Transformer based Inter-stage Network

A π-type inductor peaking (PIP) method has been proposed which can achieve a bandwidth enhancement ratio (BWER) more than 3. While PIP can greatly enhance the bandwidth of the cascaded amplifier, it requires three different inductors and two resistors for each inter-stage of the cascaded amplifiers which makes the multistage amplifier quite bulky. This bulky PIP can be approximately transformed into a compact single transformer with a small resistor with conversion equations as below. Figure 2 shows the conversion of PIP into a compact transformer based inter-stage network.

10

1

DS

D

LLLk

(1)

))(1( 210

201

DDS

DSP LLLk

LLL

(2)

))(1( 210

101

DDS

DSS LLLk

LLL

(3)

213 || RRR (4)


By utilizing the proposed transformer as a compact inter-stage network, BWER is comparable to PIP method with much smaller occupation area. The top metal (whose thickness is 3 μm) is used for the transformer, which only occupies an area of 175 x 175 μm2, as shown in Figure 3.

C. Noise analysis of the proposed CG-LNA The trans-conductance of the CG-LNA is given by

(5)

where Zin(s) is defined by

(6)

The LNA noise factor is defined by (neglecting ro)

(7)

where X(s) is defined by

(8)

where γ, α, and δ are process-dependent parameters. Because Ls partially cancels the parasitic capacitance at the source node of the transistor in front stage, its noise contribution remains much less than that of the transistor even at relatively high frequencies. The noise is dominated

by the thermal noise (second term), which is mainly frequency-independent. The frequency-dependent gate induced noise (third term), and the frequency shaping of the resistor noise (fourth term) results in a small variation of the CG-LNA noise factor over the BW.

Fig. 3. Layout of the PIP transformer with top metal layer (i.e., OA layer in Samsung 65 nm technology). The area of the transformer is 175 x 175 μm2.

Fig. 4. Post-layout simulation result of S21 for the 5-stage LNA.




III. SIMULATION AND MEASUREMENT RESULTS

Figure 4 presents the simulated S21. The maximum

voltage gain is 16.2 dB and the minimum gain is 10.5 dB between 3.8 and 12.5 GHz for the LNA. The 3 dB bandwidth of the gain is wider than 14 GHz. The peak is as a function of gm where the peak can be flattened by choosing

correct bias current. Figure 5 and 6 shows the simulated input and output reflection coefficients. S11 is lower than -10 dB between 3.8 and 12.5 GHz for the LNA. The output buffer achieves excellent matching up to 17 GHz. The noise figure (NF) of the LNA is shown in Figure 7. The minimum noise figure is 9.4 dB at 12.8 GHz in simulation.

The LNA was fabricated in Samsung 65 nm RFCMOS

Fig. 7. Post-layout simulation result of noise figure for the 5-stage LNA.

Fig. 8. Chip micrograph (Size : 0.73 x 1.68 mm2)

Fig. 9. Measured result of S21 with correct bias current for the 5-stage LNA.

Fig. 10. Measured result of S11 for the 5-stage LNA.




technology. Figure 8 shows the chip micrograph. The overall chip area is 0.73 x 1.68 mm2. The LNA consumes 11 mW from a 1.2 V supply. The measured S-parameters are shown in Figure 9 to 12. Within 1 – 13 GHz, the measured small-signal gain (S21) with correct bias current achieves a maximum value of 14.3 dB at 8.2 GHz, and has a minimum value of 10.2 dB at 4.32 GHz. The measured 3-dB bandwidth of the gain is wider than 13GHz. In this frequency range, the measured output return loss (S22) is less than -10 dB, the measure input return loss (S11) is less than -10 dB, and the measured isolation (S12) is less than –52.4 dB. The simulation in general agrees well with the measured results. The relatively large discrepancy in S22 can be attributed to the source follower used for output matching. The stability factor K calculated from the measured S-parameters is greater than 1 suggesting unconditional stability of the circuit. At 8.2 GHz with maximum gain, the proposed LNA has P1dB of -16.33 dBm. The measured P1dB is well matched with simulation result.

IV. CONCLUSIONS

In this study, a low power wide-band 5-stage low noise amplifier (LNA) was realized in Samsung 65 nm CMOS. The designed wideband LNA demonstrated 1-13 GHz of bandwidth with > 10 dB of the gain flatness by using the proposed compact inter-stage network.

ACKNOWLEDGMENT

This work was supported by IDEC (IC Design Education Center).

REFERENCES

[1] A. Ismail and A. A. Abidi, “A 3–10 GHz low noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2269–2277, Dec. 2004.

[2] A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS low noise amplifier for 3.1–10.6 GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.

[3] X. Fan, E. Sánchez-Sinencio, and J. Silva-Martinez, “A 3 GHz–10 GHz common gate ultrawideband low noise amplifier,” in Proc. IEEE Midwest Symp. Circuits and Systems, Aug. 2005, pp. 631–634.

[4] K. Chen, J. Lu, B. Chen, and S. Liu, “An ultra-wide-band 0.4–10 GHz LNA in 0.18 -mCMOS,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 54, no. 3, pp. 217–221, Mar. 2007.

[5] C. F. Liao and S. I. Liu, “A broadband noise-canceling MOS LNA for 3.1–10.6-GHz UWB receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 329–339, Feb. 2007.

[6] W. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linear broadband CMOS LNA employing noise and distortion cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1164–1176, May 2008.

[7] S. Shekhar, J. S.Walling, and D. J. Allstot, “Bandwidth extension techniques for CMOS amplifiers,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2424–2438, Nov. 2006.

Hyohyun Nam received the B.S. degree and M.S. degree in electrical and computer engineering from University of Seoul, Seoul, Korea, in 2013 and in 2015, respectively. He is currently pursuing the Ph.D. degree in electronics and electrical engineering at Dongguk University, Seoul, Korea.

His current research interests include advanced CMOS device designs and RF integrated circuits.

Jung-Dong Park received the

B.S. degree from Dongguk University, Seoul, Korea, in 1998, the M.S. degree in Gwangju Institute of Science and Technology (GIST), Gwangju, Korea, in 2000, and the Ph.D. degree in EECS from the University of California at Berkeley, in 2012.

His research include device physics and modeling, analog, RF, mixed-signal, mm-wave integrated circuits, and microwave electronics including antennas.

Fig. 13. Simulation vs. Measured result of P1dB for the 5-stage LNA.

idec journal of integrated circuits and systems...

Documents