ic-unicamp mc 603/613 - 20061 - 1 finite state machines mixed style rtl modeling extraído da george...
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MC 603/613 - 2006 1 - 1
IC-UNICAMP
Finite State Machines Finite State Machines Finite State Machines Finite State Machines
Mixed Style RTL Modeling
Extraído da George Mason Univ.Extraído da George Mason Univ.ECE 545ECE 545
Lecture 5Lecture 5
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IC-UNICAMP Finite State Machines (FSMs)Finite State Machines (FSMs)Finite State Machines (FSMs)Finite State Machines (FSMs)
• Any Circuit with Memory Is a Finite State Machine– Even computers can be viewed as huge FSMs
• Design of FSMs Involves– Defining states– Defining transitions between states– Optimization / minimization
• Above Approach Is Practical for Small FSMs Only
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IC-UNICAMP Máquina de EstadosMáquina de EstadosMáquina de EstadosMáquina de Estados
Circuito Sequencial Síncrono Genérico
CCFF
CCSi
Si+1
X
YCC FF
SiSi+1
XY
Máquina de Moore Máquina de Mealy
Saída Y muda apenas na transição do clock
Saída Y pode mudar emqualquer instante, em função da entrada X
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IC-UNICAMP
Estado Entradas Saídas
Atual Próximo
S0
S2
S1
Síntese de uma máquina de estadosSíntese de uma máquina de estadosSíntese de uma máquina de estadosSíntese de uma máquina de estados
S0
S1
S2
S3
Diagrama de Transição de Estados
Mooreentr
Mealyentr / saída
Tabela de Transição de Estados
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IC-UNICAMP
Estado Entradas Saídas
Atual Próximo
00
01
10
Síntese de uma máquina de estadosSíntese de uma máquina de estadosSíntese de uma máquina de estadosSíntese de uma máquina de estados
Codificação dos estados• S0 = 00 etc
Equações booleanas dos circuitos combinacionais• Si+1 = fS (Si, X) • Y = fY (Si, X) (em maq. de Moore, só S)
• Sintetizar os CCs• Elementos de memória podem ser FF-D ou FF-JK
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IC-UNICAMP Moore FSMMoore FSMMoore FSMMoore FSM
• Output Is a Function of Present State Only
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clockreset
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IC-UNICAMP Mealy FSMMealy FSMMealy FSMMealy FSM
• Output Is a Function of a Present State and Inputs
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Present StateRegister
clockreset
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IC-UNICAMP Moore MachineMoore MachineMoore MachineMoore Machine
state 1 /output 1
state 2 /output 2
transitioncondition 1
transitioncondition 2
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IC-UNICAMP Mealy MachineMealy MachineMealy MachineMealy Machine
state 1 state 2
transition condition 1 /output 1
transition condition 2 /output 2
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IC-UNICAMP Moore vs. Mealy FSM (1)Moore vs. Mealy FSM (1)Moore vs. Mealy FSM (1)Moore vs. Mealy FSM (1)
• Moore and Mealy FSMs Can Be Functionally Equivalent– Equivalent Mealy FSM can be derived from Moore
FSM and vice versa
• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States– Smaller circuit area
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IC-UNICAMP Moore vs. Mealy FSM (2)Moore vs. Mealy FSM (2)Moore vs. Mealy FSM (2)Moore vs. Mealy FSM (2)
• Mealy FSM Computes Outputs as soon as Inputs Change– Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM
• Moore FSM Has No Combinational Path Between Inputs and Outputs– Moore FSM is more likely to have a shorter critical
path
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IC-UNICAMP Moore FSM - Example 1Moore FSM - Example 1Moore FSM - Example 1Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
S2: “10”observed
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IC-UNICAMP Mealy FSM - Example 1Mealy FSM - Example 1Mealy FSM - Example 1Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
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IC-UNICAMP Moore & Mealy FSMs – Example 1Moore & Mealy FSMs – Example 1Moore & Mealy FSMs – Example 1Moore & Mealy FSMs – Example 1
clock
input
Moore
Mealy
0 1 0 0 0
S0 S1 S2 S0 S0
S0 S1 S0 S0 S0
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IC-UNICAMP FSMs in VHDLFSMs in VHDLFSMs in VHDLFSMs in VHDL
• Finite State Machines Can Be Easily Described With Processes
• Synthesis Tools Understand FSM Description If Certain Rules Are Followed• State transitions should be described in a process
sensitive to clock and asynchronous reset signals only
• Outputs described as concurrent statements outside the process
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IC-UNICAMP Moore FSMMoore FSMMoore FSMMoore FSM
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present State
Next State
Outputs
clockreset
process(clock, reset)
concurrent statements
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IC-UNICAMP Mealy FSMMealy FSMMealy FSMMealy FSM
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
Present StateRegister
clockreset
process(clock, reset)
concurrent statements
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IC-UNICAMP FSM States (1)FSM States (1)FSM States (1)FSM States (1)
architecture behavior of FSM is type state is (list of states); signal FSM_state: state;begin process(clk, reset) begin if reset = ‘1’ then FSM_state <= initial state; elsif (clock = ‘1’ and clock’event) then case FSM_state is
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IC-UNICAMP FSM States (2)FSM States (2)FSM States (2)FSM States (2)
case FSM_state is when state_1 => if transition condition 1 then FSM_state <= state_1; end if; when state_2 => if transition condition 2 then FSM_state <= state_2; end if;
end case; end if; end process;
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IC-UNICAMP Moore FSM - Example 1Moore FSM - Example 1Moore FSM - Example 1Moore FSM - Example 1
• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
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IC-UNICAMPMoore FSM in VHDL (1)Moore FSM in VHDL (1)Moore FSM in VHDL (1)Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)BEGIN
IF(reset = ‘1’) THENMoore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state IS
WHEN S0 => IF input = ‘1’ THEN
Moore_state <= S1; ELSE Moore_state <= S0; END IF;
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IC-UNICAMP Moore FSM in VHDL (2)Moore FSM in VHDL (2)Moore FSM in VHDL (2)Moore FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Moore_state <= S2; ELSE Moore_state <= S1; END IF;
WHEN S2 => IF input = ‘0’ THEN
Moore_state <= S0; ELSE
Moore_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
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IC-UNICAMP Mealy FSM - Example 1Mealy FSM - Example 1Mealy FSM - Example 1Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
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IC-UNICAMP Mealy FSM in VHDL (1)Mealy FSM in VHDL (1)Mealy FSM in VHDL (1)Mealy FSM in VHDL (1)
TYPE state IS (S0, S1);SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)BEGIN
IF(reset = ‘1’) THENMealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state IS
WHEN S0 => IF input = ‘1’ THEN
Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;
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IC-UNICAMP Mealy FSM in VHDL (2)Mealy FSM in VHDL (2)Mealy FSM in VHDL (2)Mealy FSM in VHDL (2)
WHEN S1 => IF input = ‘0’ THEN
Mealy_state <= S0; ELSE Mealy_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
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IC-UNICAMPMoore FSM – Example 2: State diagram
C z 1 =
resetn
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
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IC-UNICAMP
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore FSM – Example 2: State table
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IC-UNICAMP Moore FSMMoore FSMMoore FSMMoore FSM
Present StateRegister
Next Statefunction
Outputfunction
Input: w
Present State: y
Next State
Output: z
clockresetn
process(clock, reset)
concurrent statements
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IC-UNICAMP
USE ieee.std_logic_1164.all ;
ENTITY simple ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END simple ;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
IF resetn = '0' THENy <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
Moore FSM – Example 2: VHDL code (1)
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IC-UNICAMP
CASE y ISWHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;WHEN B =>
IF w = '0' THENy <= A ;
ELSEy <= C ;
END IF ;WHEN C =>
IF w = '0' THENy <= A ;
ELSEy <= C ;
END IF ;END CASE ;
Moore FSM – Example 2: VHDL code (2)
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IC-UNICAMP
Moore FSM – Example 2: VHDL code (3)Moore FSM – Example 2: VHDL code (3)Moore FSM – Example 2: VHDL code (3)Moore FSM – Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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IC-UNICAMP Moore FSMMoore FSMMoore FSMMoore FSM
Present StateRegister
Next Statefunction
Outputfunction
Input: w
Present State: y_present
Next State: y_next
Output: z
clockresetn
process(w, y_present)
concurrent statements
process(clock, resetn)
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IC-UNICAMP
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y_present, y_next : State_type ;
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THENy_next <= A ;
ELSEy_next <= B ;
END IF ;WHEN B =>
IF w = '0' THENy_next <= A ;
ELSEy_next <= C ;
END IF ;
Alternative VHDL code (1)
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IC-UNICAMP
WHEN C =>IF w = '0' THEN
y_next <= A ;ELSE
y_next <= C ;END IF ;
END CASE ;END PROCESS ;
PROCESS (clock, resetn)BEGIN
IF resetn = '0' THENy_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THENy_present <= y_next ;
END IF ;END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ;END Behavior ;
Alternative VHDL code (2)
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IC-UNICAMP
A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
resetn
w 1 = z 0 =
Mealy FSM – Example 2: State diagram
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IC-UNICAMP
Present Next state Output z
state w = 0 w = 1 w = 0 w = 1
A A B 0 0 B A B 0 1
Mealy FSM – Example 2: State table
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IC-UNICAMP Mealy FSMMealy FSMMealy FSMMealy FSM
Next Statefunction
Outputfunction
Input: w
Present State: yNext State
Output: z
Present StateRegister
clockresetn
process(clock, reset)
concurrent statements
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IC-UNICAMP
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY Mealy ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END Mealy ;
ARCHITECTURE Behavior OF Mealy ISTYPE State_type IS (A, B) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
IF resetn = '0' THENy <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
Mealy FSM – Example 2: VHDL code (1)
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IC-UNICAMPMealy FSM – Example 2: VHDL code (2)Mealy FSM – Example 2: VHDL code (2)Mealy FSM – Example 2: VHDL code (2)Mealy FSM – Example 2: VHDL code (2)
CASE y IS WHEN A => IF w = '0' THEN
y <= A ;ELSE
y <= B ;END IF ;
WHEN B =>IF w = '0' THEN
y <= A ;ELSE
y <= B ; END IF ;END CASE ;