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Development of Reusable Environment for I2C Protocol

PRESENTED BY:SANKULA SIVA SANKARS.S.G.KRISHNA YADAV .KKANCHI SRILATHA V.VAMSI KRISHNA M.NIKLESH REDDY Project Guide: PADMANABAN

1/21/2015Copyright CoreEL Technologies (I) Pvt. Ltd.2Aim:

To verify I2C masterObjectives:

1.To conduct a literature survey to understand the functionality of I2C.

2.To define specifications.

3.To develop the simulation model of the I2C master DUT.

4.To develop the reusable verification Environment.

5.To analyze functional & code coverage reports.

Copyright CoreEL Technologies (I) Pvt. Ltd.Introduction:The name stands for Inter - Integrated Circuit Bus

A Small Area Network connecting ICs and other electronic systems

Originally intended for operation on one single board / PCB

Synchronous Serial Signal Two wires carry information between a number of devices One wire use for the data One wire used for the clock Today, a variety of devices are available with I2C Interfaces Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D converter1/21/2015Copyright CoreEL Technologies (I) Pvt. Ltd.

Features:Data transfer between ICs and systems at relatively low rates Classic I2C is rated to 100K bits/second Fast Mode devices support up to 400K bits/second A High Speed Mode is defined for operation up to 3.4M bits/second

Reduces Board Space and Cost By: Allowing use of ICs with fewer pins and smaller packages Greatly reducing interconnect complexity Allowing digitally controlled components to be located close to their point of use.1/21/20154Copyright CoreEL Technologies (I) Pvt. Ltd.

I2C specificationSingle master single slave

Synchronous

Bidirectional Serial Communication

7-bit addressing mode

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5

Master: Initiates a transfer by generating start and stop conditions Generates the clock Transmits the slave address Determines data transfer direction

Slave: Responds only when addressed Timing is controlled by the clock line 1/21/20156Copyright CoreEL Technologies (I) Pvt. Ltd.

Top level diagram

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R/WDATA_INADDRESSRESETCLOCKMICRO PROCESSOR I2C MASTER CONTROLLER

SCLSDADATA_OUT

Pin DescriptionSIGNAL NAMESIGNAL DIRECTIONDEFINITIONACTIVE STATEClockInputMicroprocessor clockN/AResetInputSystem resetActive LowAddressInputAddress bits reading and writing to configuration and data registersN/ADataBi-directionalData busN/ARWInput1 = RD0 = WRSDABi-directionalI2C Data bus lineN/ASCLUni-directionalI2C Clock lineN/A

1/21/20158Copyright CoreEL Technologies (I) Pvt. Ltd.

Operation of I2C BusStart Condition

Slave address + R/W Slave acknowledges with ACK

All data bytes Each followed by ACK

Stop Condition

ACK from SlaveACK from Receiver

Remember : Clock is produced by MasterStartStopSCLSDA1/21/20159 Copyright CoreEL Technologies (I) Pvt. Ltd.

WRITE OPERATION: generate start commandwrite slave address + write bitreceive acknowledge from slave write datareceive acknowledge from slavegenerate stop command

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Read operation:

generate start bit

Read slave address + read bit

receive acknowledge from slave

Read data

Send acknowledge to slave

write no acknowledge (NACK) to slave, indicating end of transfer

generate stop signal

1212121212TIMING DIAGRAM

D0D1D2xxxxxxxxxxxxA0A1 A2 A3A4A5xxxxD8D9xxxxxxxxD7CLKRESETR=1/W=0DATA_INDATA_OUTADD

1/21/2015Copyright CoreEL Technologies (I) Pvt. Ltd.13ObjectivesPhase-IPhase-IISurvey20-1-2015specifications27-1-2015simulationWill complete by 6-2-2015environment14-2-2015coverage15-2-2015

Schedule:-Gantt chart

Deliverablesverify model and DUTTest plan and valid test cases Environment using System VerilogCode and Functional Coverage reports1/21/2015Copyright CoreEL Technologies (I) Pvt. Ltd.14

Referenceswww.nxp.comSPI vs I2C pdfwww.ti.comwww.opencores.org

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