i2c datasheet

i

Technical Data Sheet

Part Number: T-CS-PE-0007-100

Document Number: I-IPA01-0045-TDS Rev 14

May 2011

Technical Data Sheet

Inter Integrated Circuit (I2C)

Document No: I-IPA01-0045-TDS Rev 14, May 2011 © 2005-2011 Cadence Design Systems, Inc. Page ii


©2005-2011 Cadence Design Systems, Inc. All rights reserved

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Neither the whole nor any part of the information contained in, or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright owner.

The product described in this document is subject to continuous developments and improvements and is supplied "AS IS". All warranties implied or expressed including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded. Cadence Design Foundry, Inc shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Cadence Design Foundry products are not authorized for use as critical components in life support devices or systems without the express written approval of an authorised officer of Cadence Design Foundry, Inc. As used herein:

1. Life support devices or systems are devices of systems that are (a) intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Licensing

Licensing this product does not imply a right under the Philips I2C Patents to make, use or sell any integrated circuit or other electronic device implementing the product. To implement this product in an integrated circuit or other electronic device, a patent licence must first be obtained from Philips Electronics N.V.

I2C Technical Data Sheet

Document No: I-IPA01-0045-TDS Rev 14, May 2011 © 2005-2011 Cadence Design Systems, Inc. Page 1


Features

• Uses the AMBA APB protocol, version 2.0 • Uses I2C bus specification version 2.0 (100Khz and 400KHz) • Programmable for both normal (100 kHz) and fast bus data rates (400 kHz) • Programmable as either a master or slave interface • Programmable to use normal or extended addressing • Capable of clock synchronization and bus arbitration • Fully programmable slave response address • Optional reversible FIFO with parameterizable depth (same register array for receive

and transmit) • Slave monitor mode when set up as master • Supports I2C bus hold for slow host service • Supports combined format transfers both as master and slave • Slave time out detection with programmable period • Transfer status interrupts and flags • System clock speed over 200 MHz (0.13 µm technology)

Description

The I2C module is a bus controller that can function as a master or slave in a multi-master, two-wire serial I2C bus. In master mode, the I2C interface can transmit data to a slave and initiate a transfer to receive data from a slave.

Control Register

TX Data Register

RX Data Register

Status Register

InterruptController

APBI/F

Clock EnableGenerator

RX ShiftRegister

SCL/SDAInterface

ControlFSM

When embedded as a master in a multi-master bus, the I2C performs arbitration for bus ownership and clock synchronization with other bus masters. This prevents any corruption of data when more than one master tries to transmit or receive data at the same time.

Also, it can use both normal (7 bit) addressing or extended (10 bit) addressing modes. This option is programmable in master mode and automatic in slave mode by detecting a specific code in bits [7:3] of the first address byte.

When configured in slave mode, the response address is fully programmable. General call addresses are not acknowledged.



A register type FIFO can be implemented in the design as an option. This FIFO is reversible to keep the gate count of the module low with the same FIFO used both for transmit and receive. It is accessed by the host through a single APB register.

In master mode, the FIFO allows the host to load a request for multiple data bytes transfer and receive notification when this request is serviced by the I2C interface, or if the transfer is terminated prematurely due to error or time out. The host can determine the reasons and the outstanding amount of data by reading the interrupt status register and transfer size register.

In slave mode, the FIFO allows for buffering the received data or storing transmit data in advance in the FIFO to reduce the load on the host servicing the I2C interface.

The I2C interface is capable of holding the I2C bus by keeping the sclk line low until the host provides more data to allow transfer to continue, or until the host allows the transfer to be terminated. If bus hold mode is not activated by the host, the I2C interface terminates the transfer, if acting as master, or allows it to be terminated, if acting as a slave, after the amount of data provided by the host is transferred.

In either master or slave mode, the I2C interface is capable of detecting excessively long periods of the sclk signal being low on the bus which is signified by a maskable interrupt. The time out period is programmable by the host.

When set up as master, the I2C module can be driven in slave monitor mode. In this mode, an attempt is made to access a slave to check if that slave is ready to respond and perform a transfer. In this mode, when an address is sent to a slave, an interrupt is generated if the slave responds with ACK without any data to be transferred. If the slave does not respond with ACK, the I2C module waits for a back-off time before repeating to address the slave and continues to do this until the slave responds with ACK to its address.

The I2C module has a single clock domain operating on a single clock edge.

Signal Interfaces

The I2C has two sets of signals, one to deal with I/O and another to interface with the AMBA APB bus as detailed below.

n_p_reset

I2CI/F

pclk

penablepwrite

paddr[11:0]pwdata[15:0]prdata[15:0]

i2c_irq

sda_outsda_oensda_inputscl_outscl_oenscl_input

psel

Interface and Bus Signal Descriptions

Signal Name I/O Description

n_p_reset I Active low reset for entire block

pclk I Peripheral bus clock, rising edge used throughout.



psel I APB signal. Selects this specific APB interface for data transfer. Used along with penable to perform data transfers.

penable I APB signal. When set high indicates that data transfers are enabled.

pwrite I APB signal. When set high and psel is active, it indicates that data is to be written to the I2C interface.

paddr[11:0]

I APB address bus of selected master

pwdata[15:0]

I APB write data

prdata[15:0]

O APB read data

i2c_irq O Interrupt request to host. When active high indicates that the I2C requires host intervention.

scl_input I Actual state of the external SCL signal

sda_input I Actual state of the external SDA signal

scl_out O Clock to be placed on external SCL signal.

scl_oen O Output enable for the SCL output buffer

sda_out O Data to be placed on external SDA signal.

sda_oen O Output enable for the SDA output buffer

APB Timing Characteristics

Tispen Tihpen

TihpelTispe

l

TihpaTispa

TihpwTispw

TihpwdTispwd

TovprdTohprd

pclk

penable

psel

paddr

pwrite

pwdata

prdata

n_p_resetTihnres

Tisnres

Tclk

Parameter Description Min Max Unit

Tclk Clock period 5 DC ns



Tihnres n_p_reset hold after pclk N/A N/A

Tisnres n_p_reset setup before pclk N/A N/A

Tihpen penable hold after pclk 0 — ns

Tispen penable setup before pclk 50%

— Tclk

Tihpsel psel hold after pclk 0 — ns

Tispsel psel setup before pclk 50%

— Tclk

Tihpa paddr hold after pclk 0 — ns

Tispa paddr setup before pclk 50%

— Tclk

Tihpw pwrite hold after pclk 0 — ns

Tispw pwrite setup before pclk 50%

— Tclk

Tihpwd pwdata hold after pclk 0 — ns

Tispwd pwdata setup before pclk 50%

— Tclk

Tohprd prdata hold after pclk 0 — ns

Tovprd prdata valid after pclk — 30%

Tclk

Note Timing achieved using trial layout with 0.13 µm technology.

Programming Interface

Register Map

The following registers can be configured to determine the functionality of the interface.

Offset Address R/W

Reset Value Function

0x00 R/W 0x0 Control register

0x04 RO 0x0 Status register

0x08 R/W 0x0 I2C address register

0x0C R/W 0x0 I2C data register

0x10 RO 0x0 Interrupt status register

0x14 R/W 0x0 Transfer size register

0x18 R/W 0x0 Slave monitor pause register

0x1C R/W 0x1F Time out register



0x20 RO 0x2FF Interrupt mask register

0x24 WO 0x0 Interrupt enable register

0x28 WO 0x0 Interrupt disable register

Control Register

The main control register which defines in which mode the interface operates.

Bit 15 14 13 12 11 10 9 8

Func divisor_a divisor_b

Bit 7 6 5 4 3 2 1 0

Func — CLR_FIFO SLVMON HOLD ACKEN NEA MS RW

Function Signal Name Description

RW read_write Direction of transfer: 1 - master receiver 0 - master transmitter. This bit is used in master mode only.

MS master_slave Overall interface mode: 1 - master 0 - slave

NEA normal_extended Addressing mode: 1 - normal (7-bit) address 0 - extended (10-bit) address. This bit is used in master mode only.

ACKEN ackn_enabled Enable transmission of ACK when master-receiver: 1 – acknowledge enabled, ACK transmitted 0 – acknowledge disabled, NACK transmitted. This bit must always be set if FIFO is implemented.

HOLD hold_bus Hold I2C sclk low until host services the data resources or clears this bit. 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes.

SLVMON

slave_monitor Slave monitor mode. 1 - monitor mode. I2C master transmits slave address and terminate if ACK. Repeat if NACK. 0 - normal operation. I2C master transmits slave address and transfers data if ACK. This bit is used in master mode only.



CLR_FIFO

clear_fifo This bit is implemented only if FIFO is implemented. Setting this bit to 1 automatically initializes the FIFO to all zeros and clears the transfer size register. This flag is used in both master and slave modes and is automatically cleared on the next APB clock after being set.

-- Reserved Always read zero

divisor_a Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1.

divisor_b Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1.

Status Register

Bit 15 14 13 12 11 10 9 8

Func — — — — — — — BA

Bit 7 6 5 4 3 2 1 0

Func RXOVF TXDV RXDV — RXRW — — —

Function

Signal Name Description

— Reserved Always reads zero

RXRW RX read_write Indicates the mode of the transmission received from a master.

RXDV Receiver Data Valid Indicates that there is valid, new data to be read from the interface.

TXDV Transmit Data Valid Indicates that there is still a byte of data to be transmitted by the interface.

RXOVF

Receiver Overflow This flag is set when the receiver receives a byte of data before the previous byte has been read by the host.

BA Bus Active Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it.



Address Register

Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. APB write access to this register always initiates a transfer if the I2C is in master mode. Reserved bits always read as zeros.

Bit 15 14 13 12 11 10 9 8

Func — — — — — — ADD(9) ADD(8)

Bit 7 6 5 4 3 2 1 0

Func ADD(7) ADD(6) ADD(5) ADD(4) ADD(3) ADD(2) ADD(1) ADD(0)

Data Register

When written to, the data register sets data to transmit. When read from, the data register reads the last received byte of data. Reserved bits always read as zeros.

Bit 15 14 13 12 11 10 9 8

Func — — — — — — — —

Bit 7 6 5 4 3 2 1 0

Func DATA(7) DATA(6) DATA(5) DATA(4) DATA(3) DATA(2) DATA(1) DATA(0)

Interrupt Status Register

All bits of this register are cleared upon read.

Bit 15 14 13 12 11 10 9 8

Func — — — — — — ARB_LOST —

Bit 7 6 5 4 3 2 1 0

Func RX_UNF TX_OVF RX_OVF SLV_RDY TO NACK DATA COMP

Function Signal Name Description



COMP Transfer complete Master Mode In master write, this bit is always set when all the supplied data is successfully written to the slave and transfer is about to be terminated with STOP sequence. If FIFO is implemented and hold bit is set, COMP bit is also set as soon as the data is successfully written to the slave, but transfer is not terminated at this point. This allows for combined transfers to be performed even when FIFO is implemented. If the host clears the HOLD bit instead of continuing the transfer, COMP bit is set again during the STOP sequence generation. In master read, this bit is set when all the requested data has been successfully read from a slave and transfer is to be terminated with STOP sequence. Slave Mode In slave receive, this bit is set whenever the master terminates the transfer by generating STOP sequence. In slave transmit, this bit is set whenever all the data supplied by the host is transmitted and the last byte was not acknowledged by the master which terminates the transfer with STOP sequence.

DATA More data Master Write or Slave Transmitter If FIFO not implemented, this bit is set as soon as the I2C data register is loaded in the output shift register of the I2C interface. If FIFO is implemented, this bit is set whenever there are only 2 bytes left in the FIFO. In slave transmitter mode, this bit is also set if the FIFO is emptied but I2C master returned ACK on the last byte transmitted by the slave. Master Read or Slave Receiver If FIFO is not implemented in the design, this bit is set whenever a byte is received and stored in the I2C register. If FIFO is implemented, this bit is set whenever there are only 2 free locations in the FIFO.

NACK Transfer not acknowledged

Master Mode This bit is set whenever the accessed slave responds with a NACK during address or data byte transfer. Slave Mode This bit is set if FIFO is implemented and is in slave transmitter mode when a master terminates the transfer before all data supplied by the host is transmitted.

TO Transfer time out Master and Slave Mode This bit is set whenever the I2C sclk line is kept low for longer time than the value that is specified by the time out register.



SLV_RDY

Monitored slave ready

This bit is set only if I2C interface is in master mode, SLVMON bit in the control register is set and the addressed slave returns ACK.

RX_OVF Receive overflow Master Read or Slave Receiver If FIFO is not implemented, this bit is set whenever there is valid data in the I2C data register and a new byte is received. The second byte is not acknowledged and contents of I2C data register remains unchanged. If FIFO is implemented, this bit is set whenever FIFO is full and a new byte is received. The new byte is not acknowledged and contents of the FIFO remains unchanged.

TX_OVF FIFO transmit overflow

This bit is available only if FIFO implemented in the design. Set if the host attempts to write to the I2C data register more times than the FIFO depth.

RX_UNF FIFO receive underflow

This bit is available only if FIFO implemented in the design. Set if the host attempts to read from the I2C data register more times than the value of the transfer size register plus one.

— Reserved Always reads zero.

ARB_LOST

arbitration lost Master Mode This bit is set if a master loses bus ownership during a transfer due to ongoing arbitration.

Bits [15:10]

reserved Always reads zero.

Transfer Size Register

This register is available only if FIFO is implemented in the design. Its meaning varies according to the operating mode as follows:

• Master transmitter mode: number of data bytes still not transmitted minus one • Master receiver mode: number of data bytes that are still expected to be received • Slave transmitter mode: number of bytes remaining in the FIFO after the master

terminates the transfer • Slave receiver mode: number of valid data bytes in the FIFO

This register is cleared if CLR_FIFO bit in the control register is set.

Bit 7 6 5 4 3 2 1 0

Func Transfer Size (7) *

Transfer Size (6) *

Transfer Size (5) *

Transfer Size (4)*

Transfer Size (3)

Transfer Size (2)

Transfer Size (1)

Transfer Size (0)

* - The presence of these bits depends on the setting of `define p_xfer_size_width.

Slave Monitor Pause Register

This register is associated with the slave monitor mode of the I2C interface. It is meaningful only when the module is in master mode and bit SLVMON in the control register is set.



This register defines the pause interval between consecutive attempts to address the slave once a write to an I2C address register is done by the host. It represents the number of sclk cycles minus one between two attempts.

The reset value of the register is 0, which results in the master again trying to access the slave immediately after unsuccessful attempt.

Bit 7 6 5 4 3 2 1 0

Func — — — — Pause

(3) Pause

(2) Pause

(1) Pause

(0)

Time Out Register

The value of time out register represents the time out interval in number of sclk cycles minus one.

When the accessed slave holds the sclk line low for longer than the time out period, thus prohibiting the I2C interface in master mode to complete the current transfer, an interrupt is generated and TO interrupt flag is set.

The reset value of the register is 0x1f.

Bit 7 6 5 4 3 2 1 0

Func TO(7) TO(6) TO(5) TO (4) TO (3) TO (2) TO (1) TO (0)

Note - the Time Out register is active in slave mode as well as master mode. In slave mode when sclk is slow enough the timeout register will cause the timeout interrupt to fire. In this case the timeout interrupt should be masked.

Interrupt Mask Register

Each bit in this register corresponds to a bit in the interrupt status register. If bit i in the interrupt mask register is set, the corresponding bit in the interrupt status register is ignored. Otherwise, an interrupt is generated whenever bit i in the interrupt status register is set.

Bits in this register are set through a write to the interrupt disable register and are cleared through a write to the interrupt enable register. All mask bits are set and all interrupts are disabled after reset. Interrupt mask register has the same format as the interrupt status register.

Bit 15 14 13 12 11 10 9 8

Func — — — — — — ARB_LOST

—

Bit 7 6 5 4 3 2 1 0




Interrupt Enable Register

This register has the same format as the interrupt status register.

Setting a bit in the interrupt enable register clears the corresponding mask bit in the interrupt mask register, effectively enabling corresponding interrupt to be generated.

Bit 15 14 13 12 11 10 9 8

Func — — — — — — ARB_LOST —

Bit 7 6 5 4 3 2 1 0


Interrupt Disable Register

This register has the same format as the interrupt status register.

Setting a bit in the interrupt disable register sets the corresponding mask bit in the interrupt mask register, effectively disabling corresponding interrupt to be generated.

Bit 15 14 13 12 11 10 9 8

Func — — — — — — ARB_LOST

—

Bit 7 6 5 4 3 2 1 0




Physical Estimates

Gate count 4200 with 8 byte FIFO 3000 without FIFO

FF count 245 with FIFO 183 without FIFO

Power estimate (0.13 µm @ 200 MHz) 1.2 mW with FIFO 750 µW without FIFO

SOC-Internal pins (in) 33

SOC-Internal pins (out) 17

SOC-External pins (in) 2

SOC-External pins (out) 4

SOC-External pins (bi-directional) 0

Verification

All our IP modules are verified to one of the following levels. Gold IP has been to target silicon. Silver IP has been to silicon in FPGA. Bronze IP has been verified in simulation with logical timing closure. In development IP has not yet been verified.

Please contact the IPGallery™ ([email protected]) for the latest verification information.

Deliverables

The full IP package comes complete with: • Verilog HDL • Cadence RTL Compiler synthesis scripts and SDC constraints • Verilog testbench • I2C User’s Guide with full programming interface, parameterization instructions and

synthesis instructions.

i2c datasheet

Documents

inter integrated circuit

sclk cycles minus

life support device

life support devices

technical data sheet

interrupt status register

sclk line low

cadence design foundry