Hyperspectral Imaging is the process by which image data is obtained simultaneously in dozens or hundreds of narrow, adjacent spectral bands. These bands contain a wealth of information. When examining datasets of any dimensionality, researches are generally looking for subsets of the data that are interesting, that is to say, that displays some measure of structure or departure from normal distribution. The abundance estimation problem is also part of the process, and the Image Space Reconstruction Algorithm (ISRA) is one of the iterative methods used to estimate abundance. When ISRA is used to approximate the abundance in a set of hyperspectral images some interesting results are obtained as shown in previous work1. The main limitation in the use of this algorithm is that the solution is time consuming. The purpose of this project is to port some or all parts of the algorithm over hardware, using FPGAs, with the objective of reducing the execution time. The algorithm has been studied, divided into equivalent hardware units, and some parts of the system have been synthesized. Results of the synthesis will be shown. This solution is novel in the low level approach selected for the classification algorithm in general.

•Work in the elaboration of ISRA code in VHDL• Synthesis the code in VHDL.• Computer interface to send and receive data from FPGA.• Testing ISRA algorithm.• Port to Xilinx Virtex IV.

The purpose of this research is to analyze the Image Space Reconstruction Algorithm (ISRA) and work on the hardware implementation of the algorithm with the objective of reducing the execution time.

Research Goals

FPGA Implementations of Image Space Reconstruction Algorithm (ISRA)

Javier Morales, Julio Sosa, Nayda SantiagoElectrical and Computer Engineering Department

University of Puerto Rico, Mayagüez Campus

This work was supported in part by CenSSIS, the Center for Subsurface Sensing and Imaging Systems, under the Engineering Research Centers Program of the National Science Foundation (Award Number ECE-9986821).

Abstract

Introduction

Future Work

References

In this research we working on the hardware implementation of one abundance estimator algorithm. This algorithm are Image Space Reconstruction Algorithm (ISRA). Researchers use this method in software implementations to estimate abundances. The problem with this software implementation are the number of iterations that they have to make to find a solution. This method are very time consuming; we chose ISRA because it is a very useful method to estimate abundance. Some researchers implement this algorithm for numerous situations or applications and ISRA most of the time converge faster than EMML. For example, studies of tomography in which investigators use these two methods shows that ISRA is easier and converges faster most of the time.

1. Rosario, S. Iterative Algorithms for Abundance Estimation on Unmixing of Hyperspectral Imagery. Master of Science, Thesis, 2004.

2. Keshava N., Mustard J. F., “Spectral Unmixing“, IEEE Signal Processing Magazine, 19: 44-57, January issue

1 2002.3. Hongtao Du, Hairong Qi, “An FPGA implementation of parallel ICA for dimensionality reduction in

hyperspectral images”, Proceedings of IEEE International,

Geoscience and Remote Sensing Symposium, IGARSS '04, Volume:

5, 20-24 Sept. 2004, Pages: 3257 – 32604. M. Leeser, J. Theiler, M. Estlick, J.J. Szymanski,

“Design tradeoffs in a hardware implementation of the k-

means clustering algorithm, Proceedings of the IEEE, Sensor Array and Multichannel Signal Processing Workshop, 16-17 March 2000, Pages: 520 – 524

5. Yu Wei, Charoensak C., “FPGA implementation of non- iterative ICA for detecting motion in image

sequences”, Control, Automation, Robotics and Vision, ICARCV, 7th International Conference, 2-5 Dec. 2002, Volume 3,

Pages: 1332-1336.6. Computer Arithmetic Algorithms, 2nd Edition, Israel

Koren, Published by A.K. Peters, Natick, MA, 2002.

State of the Art• Most abundance estimation methods in the literature are implemented in software; the limitation is that these implementations are time consuming.• Some of the algorithms implemented in FPGAs which have illustrated its feasibility in improving execution time are Parallel Independent Component Analysis (PICA), Independent Component Analysis, and K-means.• To the best of our knowledge, ISRA has not been implemented in hardware.

Spectral UnmixingSpectral unmixing is the procedure by which the measured spectrum of a mixed pixel is decomposed into a collection of constituent spectra, or endmembers, and a set of corresponding fractions, or abundances, that indicate the proportion of each endmembers present in the pixel.2

ISRA Abundance Estimator

Endmember Determination

HSI

Abundance Map

Endmember

Figure 1. Unmixing Diagram Process

In our case the matrix A is the endmembers matrix (m x n), b is the pixel in observation (m) and is the abundance vector.x̂

Results• Floating Point Adder Unit and Synthesis• Floating Point Multiplier Unit and Synthesis• Initial study of mathematics of ISRA algorithm• Xilinx Virtex II Pro

• The ISRA algorithm will be used for coral (SeaBED) image understanding (R2) and its hardware implementation will allow faster information management (R3).• The hardware implementation of ISRA will aid in monitoring Coral reefs health in coastal shallow waters and other underwater habitats (S4).

RELEVANCE TO CENSSIS STRATEGIC RESEARCH PLAN

Hardware Implementation

Image Space Reconstruction Algorithm (ISRA)

ISRA is a iterative algorithm used to estimate the proportion of each endmember present in the pixel of a hyperspectral image. ISRA depends on the previous iteration for the next one computation. ISRA guarantees the convergence and positive values in the results of the abundances. The ISRA algorithm is an iterative, multiplicative method that is given by the equation:

Explanations

Figure 3. Block diagram of hardware implementation.

We present on Figure 3 a block diagram of the hardware implementation of the ISRA algorithm. This block diagram is composed of registers, comparator, demux, control unit, adders, multipliers, and the transposition function block. All the data is stored inside the FPGA on the register blocks. The pixels observations are arranged from registers 0 to 2m, the endmembers matrix is organized in register blocks from 2m+1 to 2n and the abundance vector is arranged in blocks from 2n+1 to 2p-1. Before the data are stored on registers we proceed to multiply each pixel in observation with the endmember matrix, those results are added. In the same time the endmember matrix is multiplied by the transpose of each endmember row and by the abundance vector. Each results of this multiplication are added. The results of the both sums are divided and then are multiplied by the value of the previous iteration. The result obtained in this step is compared to determine if the iteration continue or converge. The comparator block, this comparator subtract the recent iteration with the previous iteration and then this result is compared with a tolerance, to determine if the iteration should continue or if there is convergence.

m

ikT

iij

m

iijik

jkj

Xaa

abXX

1

11

ˆ

ˆˆ

Figure 2. ISRA Algorithm

Floating Point Adder

The floating point adder is a binary adder using the IEEE Standard 754, which is the standardized way of the floating point numbers. Because the data entering could be negative this not only an adder it also subtracts if needed. Figure 4 shows the process to add or subtract two floating point numbers.6

Figure 5. Synthesis Floating Point Adder

The process to add or subtract two floating point operands are as follow: decode (unmix) the three components of the floating point numbers concatenating the implicit 1 to the mantissa, align both mantissa by /e1 – e2/ (Exponent Rule), compare both operands, compute signs, add or subtract the mantissa, normalize the mantissa, compute the exponent and encode (mix) the three components of the number. In Figure 5 we show the synthesis of the Floating Point Adder Subtract.

Figure 4. Floating Point Adder/Subtractor

Acknowledgement • We would like to thanks Miriam Leeser and her research group for their assistance.

Demux1:2p

Controller

32 Bit Register

0

32 Bit Register

2m+1

32 Bit Register

2n

32 Bit Register

2m

32 Bit Register

2n+1

32 Bit Register

2p-1

Sele

ct Set

Matrix Multiplication

Matrix Multiplication

Matrix Multiplication

32 Bit Register

2p-1

Use

Divider

Multiplier

Comparator

TranspositionFunction

32 Bit Register

2n+1

in

okIn/Out

OUT

3232

3232

32 32

32

Done

Ready

Adder with Accumulator

Adder with Accumulator