hybrid stability studies
DESCRIPTION
Hybrid stability studies. Multi – chip hybrid stability problem when more then ~ 2 chips powered up -> common mode oscillation Strasbourg experiments => sensitivity to decoupling on V125 line Instability not observed on single chip test setups but known - PowerPoint PPT PresentationTRANSCRIPT
Jan, 2001 CMS Tracker Electronics 1
Hybrid stability studies
Multi – chip hybrid stability problem when more then~ 2 chips powered up -> common mode oscillation
Strasbourg experiments => sensitivity to decouplingon V125 line
Instability not observed on single chip test setups but known sensitivity of preamp to resistance in V125 supply identified (during design phase) and solved on chip by splitting V125 with separated bond pads
Outline
Explanation/simulation of phenomenonPossible solutionsSingle chip measurements of implemented solutionsConclusions
Mark [email protected]
Jan, 2001 CMS Tracker Electronics 2
7.1
mm
8.1 mm
APV25s1 layout
Jan, 2001 CMS Tracker Electronics 3
inputFET inverter
stageV125
V125
Preamp schematic – 1 channel
inverter stage originally included to allow maximumuse of dynamic range available at shaper output
required for p-strip readout
inverter FET operating point determined by input FETsince both device sources connected to V125
use simplified schematic
sourcefollower
Jan, 2001 CMS Tracker Electronics 4
Common mode stability concerns identified during design stage
on-chip track resistance leads to positive feedback patharound preamp -> common mode instability which getsworse with increasing number of channels
track resistances
Jan, 2001 CMS Tracker Electronics 5
On-chip solution implemented
Split V125 supply on chip with separate bond pads effectively removes on-chip coupling
Problem solved? Thought so but .....
CommonV125 supply
on hybrid
Jan, 2001 CMS Tracker Electronics 6
Multi-chip schematic
If sufficient resistance present in common V125 paththen problem can re-surface (more chips => more channels)
(can still occur for a single chip if resistance big enough)
Jan, 2001 CMS Tracker Electronics 7
Simulation
Approach use single channel model, put in calculated resistances for tracks but multiply values by 128
Look at dependence of transient response on external resistor in V125 supply – one chip only here
-0.545
-0.540
-0.535
-0.530
-0.525
-0.520
-0.515
volts
100x10-6
806040200
time
0 mOhms
5 mOhms
10 mOhms
Figure 5
Preamp output shows some increase in gain for resistances up to 10 m equivalent
(note origins of waveforms offset for clarity)
Jan, 2001 CMS Tracker Electronics 8
Increasing common resistance still further
Instability sets in for equivalent resistance >30 m
frequency similar to that observed on hybrid (~30 kHz)
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
volts
100x10-6
806040200time
30 mOhms
35 mOhms
Figure 6
Interim Conclusion
instability effect can be simulatedstrong evidence that V125 supply resistance to blamesimulation may help to find solution
Jan, 2001 CMS Tracker Electronics 9
Solutions to problem
More than one – some more attractive than others
reduce power plane resistance on hybrid probably end up pushing problem elsewhere
Maintain V125 separation on hybrid, through connector, through mother cable, ...... where to stop?
others .........
Preferred solution
Concentrate here on option that appears to be mostrobust
Jan, 2001 CMS Tracker Electronics 10
Proposed solution
V125 supplies preamp input FETs onlyV125 supply to inverter stage derived from V250 via resistor probably better to supply each chip from individual resistor (~100) to ensure current shared equallyInput and inverter FET common sources completely decoupledby power supplies
Jan, 2001 CMS Tracker Electronics 11
How does it work?
Previous preamp power scheme
Current in inverter stages determined by operating pointof input devices (scaled by relative widths)
New scheme
Voltage on gates of inverter transistors same as beforeAll 128 inverter FETs operate in parallel to maintain theircommon sources at a threshold above gate voltages -> ~V125 => current in inverters defined by resistor value
V125
V125
V125
V250
Vg
Vg
Vg+Vt = ~V125
Jan, 2001 CMS Tracker Electronics 12
Experimental results with single chip pcb
APV25s1 test pcb altered to allow inverter V125connection to V125 or to V250 via 100 resistor
response to internal calibrate pulse (16 channels)
V125 V250/100
100
50
0
100500
100
50
0
100500
no common mode subtraction used for above plots
if algorithm used which calculates CM excluding channels containing signal
100
50
0
100500
100
50
0
100500
16 cal chans
remaining112 channels
V125 V250/100
appears to be good solution – minor drawback of powerconsumption in resistor
Jan, 2001 CMS Tracker Electronics 13
Can go further ...
Why not derive input FET source voltage from V250 too?
Not as robust as previous solution to supply line resistance
Significant increase in power consumption (~25%)
But supply is now only two rails and currents balanced
Jan, 2001 CMS Tracker Electronics 14
Experimental results 2 rail operation
100
50
0
100500
100
50
0
100500
100
50
0
100500
No CM subtraction
CM subtract usingaverage of channels not containing signal
CM subtract usingmedian value of allchannels
cal pulse response
performance not apparently affected by supplyinginput FET current from V250 via 24 resistor
Jan, 2001 CMS Tracker Electronics 15
Conclusions
Stability problems encountered with 1st hybrid versionunderstood and can be simulated
Proposed solution of deriving inverter V125 supply fromV250 via a resistor appears robust. Only significant drawbacka minor increase in power consumption.