hx7019atgfa preliminary datasheet--ver0.2read.pudn.com/downloads140/sourcecode/others/...02 2008/...

Himax Display, Inc. http://www.himaxdisplay.com

Himax Display, Inc.

( DOC No. HX7019ATGFA-DS )

��640X360 0.38” LCOS Module Preliminary version 02 September, 2008

DATA SHEET

-P.1- �� Himax Display, Inc. Confidential

September,2008 This information contained herein is the exclusive property of Himax Display, Inc. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax Display, Inc.

Himax Display, Inc. http://www.himaxdisplay.com

Revision History

Version Date Author Description of Changes

01 2008/08 CJ Linda

New setup

02 2008/ Linda 1. WS stage� CS stage 2. Add Optical specification 3. Add Reliability test 4. Add Mechanical dimension 5. Add Package Specification

��640X360 0.38” LCOS Module � �� September, 2008

-P.2- Himax Display, Inc. Confidential

September 2008

This information contained herein is the exclusive property of Himax Display, Inc. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax Display, Inc.

��640X360 0.38” LCOS Module DATA SHEET Preliminary V02

Contents 1. About This Document ................................................................................................3

2. General Description....................................................................................................3

3. Features.......................................................................................................................3

4. Quick Reference Data.................................................................................................4

6. Pin Assignment...........................................................................................................6

7. Pin Description ...........................................................................................................7

8. Function Description..................................................................................................8

8.1 Relationship between Input Data and Output Position.................................8

8.2 Input Timing .....................................................................................................9

8.3 Relationship between Input Data and Output Voltage ..................................9

8.4 γγγγ Correction Characteristic Curve ................................................................10

8.5 Digital to Analog Converter ...........................................................................11

8.6 Serial Interface ...............................................................................................12

8.7 Details of Read/Write Sequence Through Two Wire Serial Interface.........13

9. DC Characteristics....................................................................................................17

9.1 Absolute Maximum Ratings ..........................................................................17

9.2 Recommended Operating Conditions..........................................................17

9.3 Electrical Characteristics ..............................................................................18

10. AC Characteristics ................................................................................................18

11. Optical Characteristics .........................................................................................19

11.1 Optical Specifications....................................................................................19

11.2 Optical Specifications....................................................................................19

11.3 HX7019 Panel Reflection Spectrum..............................................................23

11.4 HX7019 Panel R-V Curves .............................................................................23

12. Reliability Test .......................................................................................................24

13. Package Specification ..........................................................................................25

13.1 Packing Procedure ........................................................................................25

13.2 Label Information...........................................................................................26

14. Green Product .......................................................................................................26

15. Mechanical Dimension .........................................................................................26


September 2008



1. About This Document

This document validates solely for the product of Himax Display, HX7019. This document is for customer’s reference only, and it subjects to change without notice. NOTE: HX7019 has passed CS (Commercial Sample) stage.

2. General Description

HX7019 is an active matrix liquid crystal display with resolution of 640 x 360 x 3 dots. HX7019 is ideal for portable and industrial applications. Horizontal digital data drivers and vertical scan drivers are integrated with single crystal pixel transistors meet the performance demands of light weight, high speed and high resolution applications. HX7019 receives 8-bits x 3-dots of digital display data per clock simultaneously and generates corresponding voltage output of 256 level gray scales, which displays 16M colors simultaneously.

3. Features

� Display Resolution of 640x360x3

� Support VGA(640x480)/Q720P(640X360) input source

� No spacers in the display area.

� RGB 8-bit digital inputs/ digital dual edge inputs.

� Integrated horizontal data and vertical scan drivers.

� Horizontal and vertical bi-directional scanning.

� Embedded DE mode timing controller.

� Maximum 15V (VDDA) power input.

� Capable of displaying 256 gray scales by 12 x 3 (RGB separately) internal γ

reference voltages.

� Embedded programmable gamma reference voltages.

� Embedded programmable VCOM voltage.

� Two-wire serial interface for internal register setting.


September 2008



4. Quick Reference Data

Description Specification Unit

Outer Package Dimensions 55.2X13 mm Active Area Dimensions 8.448 X 4.752 mm

Active Area Diagonal 0.38” inch Native Aspect Ratio 16:9 - Display Resolution 640x360x3 pixels

Pixel Pitch 13.2X13.2 um Pixel Configuration RGB -

Gray Level 256 ( 8-bits ) - Optical efficiency: Reflectance 17 %

Optical Mode Reflective - Liquid Crystal Type Twisted Nematic -

Operating Temperature 0 ~ 70 (Note 1) °C Operation Mode Normally White -

Response Time (Tr+Tf) 15 ms

All values specified at a display ambient temperature of 25°C. There is no scrolling area in the case of HX7019. Note 1: If imager is operated at temperature higher than 50 °C (on heatsink), the display will be appeared worse quality and its useful life will be reduced due to the characteristics of Liquid Crystal.


September 2008



5. Block Diagram

Display Area(640x3x360)

Even Source Driver

Odd Source Driver

Gate D

river

TCON

Two wired serialbus

ProgrammableGamma Buffer

R,G,B input

Bus Control


September 2008



6. Pin Assignment

U1

HX7019AFPC39

VDDAL3

BIASX4

VSSA5

VSSAL6

VSSD7

SDA8

SCL9

R710

R611

R512

R413

R314

R215

R116

R017

G718

G619

G520

G421

DE22

INV23

CLKX24

VDDD25

VDDD26

G327

G228

G129

G030

B731

B632

B533

B434

B335

B236

B137

B038

VSSD39

VDDA2VCOM1

Display Area


September 2008



7. Pin Description

Pin name I/O Function Description

R0~R7 G0~G7 B0~B7

I/O Display data input

The display data is input with 8-bit × 3 dots (RGB) per CLK clock. For each input dot, X0 is the LSB and X7 is the MSB.

DE I Display active

CLKX I X-axis shift clock input The display data is stored to the internal data register at the rising edge of CLKX.

BIASX I Data driver bias resistor

Connect a bias resistor to VSSA to generate data driver bias current.

INV I Data inversion input

The INV controls data inversion internally to data driver. The INV signal controls these data received on the R [7:0]/G [7:0]/B [7:0] pins. Display data is inverted when INV=H. Display data is not inverted when INV=L.

SDA I/O Two wire serial interface Data I/O Serial data I/O

SCL I Two wire serial interface Clock input Input clock for serial bus.

VCOM Reference common voltage Connect 0.1uF capacitor to GND

VDDA I Driver power supply 15V VSSA I Driver ground Ground for VDDA VDDD I Logic power supply 1.8V VSSD I Logic ground Ground for VDDD


September 2008



8. Function Description

Following by the general timing standard of VGA (480P)/Q720P (360P) (Refers to Chapter 8.2: Input Timing), customers can light on HX7019 display. If the DE is logically high, HX7019 starts to latch input data into its line buffer immediately. Followed by the start pulse falling edge, a total 640X24 bits input data latched at 640 continuous at CLKX rising edge. Both Gamma and Vcom are embedded with HX7019, which are programmable through two-wire serial bus.

8.1 Relationship between Input Data and Output Position

Input data format: 8-bit × 3 (3 dots per CLK) Input data width: 24 bits (1 pixels data) with X7 is MSB and X0 is LSB

first � last RL

R0~R7 G0~G7 B0~B7 ••• R0~R7 G0~G7 B0~B7 “H” OUT0 ••• OUT639

last � first RL R0~R7 G0~G7 B0~B7 ••• R0~R7 G0~G7 B0~B7

“L” OUT639 ••• OUT0

The following pictures show the final display results when adjusts the UD and RL.

UD=0, RL=0 UD=1, RL=0

��

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UD=0, RL=1 UD=1, RL=1

��

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September 2008



8.2 Input Timing VGA (640x480):

Description Min. Typ. Max. Unit

Horizontal Total 720 800 880 Pixel

Horizontal Display -- 640 -- Pixel

Horizontal Blanking 80 160 220 Pixel

Vertical Total 490 525 600 Line

Vertical Display -- 480 -- Line

Vertical Blanking 10 45 120 Line

Frame rate 100 120 -- Hz

Pixel Clock -- 50 -- MHz

Q720P (640X360): Description Min. Typ. Max. Unit

Horizontal Total 720 800 900 Pixel

Horizontal Display -- 640 -- Pixel

Horizontal Blanking 80 160 260 Pixel

Vertical Total 370 380 540 Line

Vertical Display -- 360 -- Line

Vertical Blanking 10 45 180 Line

Frame rate 100 120 -- Hz

Pixel Clock -- 36.5 -- MHz

8.3 Relationship between Input Data and Output Voltage

The output voltage is determined by these 8-bit digital input data, internal signal “POL”, and the 6 γ correction reference voltage. Through 6 embedded γ correction reference voltage, Gamma1 ~ Gamma6 are for positive polarity voltage output, and embedded voltage Gamma7 ~ Gamma12 are for negative polarity voltage output.

Gamma Voltage Data

Gamma1, Gamma12 00H Gamma2, Gamma11 3FH Gamma3, Gamma10 7FH Gamma4, Gamma9 BFH Gamma5, Gamma8 FBH Gamma6, Gamma7 FFH


September 2008



8.4 γγγγ Correction Characteristic Curve

FFH

C0H

Input data

80H

40H

00H

VDDA 1/3VDDA

Gamma9 Gamma8 Gamma7 Gamma6 Gamma5 Gamma4 Gamma3 Gamma2 Gamma1 Gamma10 Gamma11 Gamma12


September 2008



8.5 Digital to Analog Converter

HX7019 contains 12 x 3 (RGB) DACs with resolution of 8 bits. Each bit contains output buffer amplifiers and is written via a two-wire serial interface. All DAC are provided with reference input. The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the VDDA pin provides the high reference voltage for the corresponding DAC. Since the input coding to the DAC is straight binary, the ideal output voltage is given by:

12

*31

−−= NoutP

DVDDAVDDAV

12

*31

32

−−= NoutN

DVDDAVDDAV

Where D = decimal equivalent (0~255) of the binary code that is loaded to the DAC register; N = 8, VoutP=V1~V6, VoutN=V7~V12, Vcom voltage can select one of them (VoutP and VoutN) via a two-wire serial interface.

Vout

D

VDD

VDDA32

255 0

VDDA31

outNV

outPV


September 2008



8.6 Serial Interface HX7019 is controlled via a two wire serial interface. The device is connected to this

bus as slave devices. HX7019 has a 7-bit slave address. There are seven MSBs as 1001000. (Refer to chapter 8.7 Details of read/write sequence of the Two-wire serial interface).

Two-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START condition, when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte followed by an R/W bit (this bit determines whether data will be read from or written to the slave device).

The slave whose address corresponds to the transmitted address responds by pulling SDA low during the 9th clock pulse (this is the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register.

2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL.

3. When all data bits have been read or written to, a STOP condition is established. In Write/Read mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP condition. The master will then bring the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a STOP condition.


September 2008



8.7 Details of Read/Write Sequence Through Two Wire Serial Interface

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A A A

S 1 0 0 1 0 0 0 W A A A A A P

S 1 0 0 1 0 0 0 W S 1 0 0 1 0 0 0 R A A A A P A

7 bit address

7 bit address

7 bit address

7 bit address

7 bit address

7 bit address START condition

register address register data Acknowledge

Acknowledge STOP condition

register address

register address

register address

register data register data register data

register data register data

Acknowledge START condition WRITE command

Direction: From master to HX7019 From HX7019 to master Note: R=READ=1 and W = Write =0

Random Write Operation

Random Read Operation

Page Write Operation

Page Read Operation


September 2008



Table 8.1: Description of two wire serial interface Register I2C register ADDR. DATA. Default Value note

[ 00 ]h [ LR , UD , CLK_B , 1 , 0 , DTREN , 1 , SWAPEN ] h [ 1 , 1 , 0 , 1 , 0 , 1 , 1 , 0 ] control setting

[ 01 ]h [ SC_I2C , PFVC , PFVR , PFVRB , PFV1 , PFV2 , PFV3 , PFV4 ] h [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] control setting

[ 02 ]h [ PFV5 , PFV6 , PF_PT , TST_EN , TS3 , TS2 , TS1 , TS0 ] h [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] control setting

[ 03 ]h [ TRIGMA , YSEL , DGE , OP_DRV , YSCAL ,

Q720P , A1 , A0 ] h [ 0 , 0 , 0 , 1 , 0 , 1 , 0 , 0 ] control setting

[ 04 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] control setting

BSXCH, BSVCOM [ 05 ]h

[ BSXCH3 , BSXCH2 , BSXCH1 , BSXCH0 , BSVCOM3 , BSVCOM2 , BSVCOM1 , BSVCOM0 ] h [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ] bias current ctrl

BSRING, BSRINGB [ 06 ]h

[ BSRING3 , BSRING2 , BSRING1 , BSRING0 , BSRINGB3 , BSRINGB2 , BSRINGB1 , BSRINGB0 ] h [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ] bias current ctrl

BSV1, BSV2 [ 07 ]h [ BSV13 , BSV12, BSV11 , BSV10 , BSV23 , BSV22 , BSV21 , BSV20 ] h [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ] bias current ctrl



VCOMX [ 0a ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 ] VCOM (10.3V)

VCOMX [ 0b ]h [ VCOMPN , A6 , A5 , A4 , A3 , A2 , A1 , A1 ]

h [ 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] VCOM (10.3V)

V1XR [ 0c ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] RGMAP1(15V)

V2XR [ 0d ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ] RGMAP2(13.75V)

V3XR [ 0e ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 1 , 0 , 1 , 1 , 1 , 0 ] RGMAP3(12.85V)

V4XR [ 0f ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ] RGMAP4(12.25V)

V5XR [ 10 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ] RGMAP5(11.14V)

V6XR [ 11 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 1 , 0 , 0 , 1 , 1 , 0 ] RGMAP6(10.5V)

V7XR [ 12 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 1 , 1 , 0 , 1 , 0 ] RGMAN6(9.5V)





V12XR [ 17 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ] RGMAN1(5V)

V1XG [ 18 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] GGMAP1(15V)

V2XG [ 19 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ] GGMAP2(13.75V)

V3XG [ 1a ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 1 , 0 , 1 , 1 , 1 , 0 ] GGMAP3(12.85V)

V4XG [ 1b ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ] GGMAP4(12.25V)

V5XG [ 1c ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ] GGMAP5(11.14V)


September 2008



I2C register ADDR. DATA. note

V6XG [ 1d ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 1 , 0 , 0 , 1 , 1 , 0 ] GGMAP6(10.5V)

V7XG [ 1e ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 1 , 1 , 0 , 1 , 0 ] GGMAN6(9.5V)

V8XG [ 1f ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 1 , 1 , 1 , 0 , 1 , 0 ] GGMAN5(8.86V)

V9XG [ 20 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 1 , 1 , 0 , 0 , 1 , 1 ] GGMAN4(7.75V)



V12XG [ 23 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ] GGMAN1(5V)

V1XB [ 24 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ] BGMAP1(15V)

V2XB [ 25 ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ] BGMAP2(13.75V)





V7XB [ 2a ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 0 , 1 , 1 , 0 , 1 , 0 ] BGMAN6(9.5V)

V8XB [ 2b ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 0 , 1 , 1 , 1 , 0 , 1 , 0 ] BGMAN5(8.86V)

V9XB [ 2c ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 0 , 1 , 1 , 1 , 0 , 0 , 1 , 1 ] BGMAN4(7.75V)

V10XB [ 2d ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 0 , 0 , 1 , 0 , 0 , 0 , 1 ] BGMAN3(7.15V)

V11XB [ 2e ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1 ] BGMAN2(6.25V)

V12XB [ 2f ]h [ A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 ] h [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ] BGMAN1(5V)


September 2008



Table 8.2: Description of two wire serial interface Default Register

Default setting/ Description Note LR=1, display left to right UD=1, display up to down CLK_B = 0, input CLK posedge sample data

DTREN = 1, dithering enable SWAPEN = 0, fixed Xch RGB driving sequence SWAPEN = 1, Xch RGB driving sequence change SC_I2C = 0, disable single cell

PFXX = 0, OP on Reserve for test mode. It must be set to 0 in normal mode.

TST_EN=0, disable test mode Reserve for test mode. It must be set to 0 in normal mode.

TRIGMA = 0, disable RGB separated gamma voltage. R, G, B gamma voltage are all controlled by R gamma voltage.

TRIGMA =1, enable separated gamma voltage

YSEL = 0 Suggest user to use YSEL=1. DGE = 0, disable dual edge interface BSXX[3:0] = [1,1,1,1], bias current control, the larger number the larger bias current is driven

OP_DRV = 1, enable Xch OP driving OP_DRV=0 in the normal operation YSCAL=0, yscaling case I YSCAL=1, yscaling case II Q720P=1, input resolution is 640X360 Q720P=0, input resolution is 640X480 VCOMPN=1, VCOM range is 2/3VDDA~VDDA

VCOMN=0, VCOM range is 1/3VDDA~2/3VDDA

Gamma reference voltage / Code Gamma reference voltage / Code Gamma reference voltage / Code

V1XR= = 15V [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ]

V1XG= = 15V [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ]

V1XB= = 15V [ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ]

V2XR = 13.75V [ 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ]

V2XG = 13.75V [ 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ] V2XB = 13.75V [ 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 ]

V3XR = 12.85V [ 0 , 1 , 1 , 0 , 1 , 1 , 1 , 0 ]

V3XG = 12.85V [ 0 , 1 , 1 , 0 , 1 , 1 , 1 , 0 ] V3XB = 12.85V [ 0 , 1 , 1 , 0 , 1 , 1 , 1 , 0 ]

V4XR = 12.25V [ 1 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ]

V4XG = 12.25V [ 1 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ] V4XB = 12.25V [ 1 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ]

V5XR = 11.14V [ 1 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ] V5XG = 11.14V [ 1 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ] V5XB = 11.14V [ 1 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ] V6XR = 10.5V [ 1 , 1 , 1 , 0 , 0 , 1 , 1 , 0 ]

V6XG = 10.5V [ 1 , 1 , 1 , 0 , 0 , 1 , 1 , 0 ]

V6XB = 10.5V [ 1 , 1 , 1 , 0 , 0 , 1 , 1 , 0 ]

V7XR = 9.5V [ 0 , 0 , 0 , 1 , 1 , 0 , 1 , 0 ]

V7XG = 9.5V [ 0 , 0 , 0 , 1 , 1 , 0 , 1 , 0 ]

V7XB = 9.5V [ 0 , 0 , 0 , 1 , 1 , 0 , 1 , 0 ]

V8XR = 8.86V [ 0 , 0 , 1 , 1 , 1 , 0 , 1 , 0 ]

V8XG = 8.86V [ 0 , 0 , 1 , 1 , 1 , 0 , 1 , 0 ]

V8XB = 8.86V [ 0 , 0 , 1 , 1 , 1 , 0 , 1 , 0 ]

V9XR = 7.75V [ 0 , 1 , 1 , 1 , 0 , 0 , 1 , 1 ]

V9XG = 7.75V [ 0 , 1 , 1 , 1 , 0 , 0 , 1 , 1 ]

V9XB = 7.75V [ 0 , 1 , 1 , 1 , 0 , 0 , 1 , 1 ]

V10XR = 7.15V [ 1 , 0 , 0 , 1 , 0 , 0 , 0 , 1 ]

V10XG = 7.15V [ 1 , 0 , 0 , 1 , 0 , 0 , 0 , 1 ] V10XB = 7.15V [ 1 , 0 , 0 , 1 , 0 , 0 , 0 , 1 ]

V11XR = 6.25V [ 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1 ] V11XG = 6.25V [ 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1 ] V11XB = 6.25V [ 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1 ] V12XR = 5V [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ]

V12XG = 5V [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ]

V12XB = 5V [ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 ]

VCOMX= 10.3V [ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 ]


September 2008



9. DC Characteristics

This section describes about the following topic:

� Absolute Maximum Rating � Recommended Operating Conditions � Electrical Characteristics

9.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit

VDDA -0.5 to +16.5 V Power supply voltage VDDD -0.5 to V

Input voltage CMOS/TTL Input -0.5 to VDDD V

Note: The Device is subjected to permanent damaged if stresses go beyond those absolute maximum ratings listed above.

9.2 Recommended Operating Conditions

Rating Parameter Symbol Min. Typ. Max.

Unit

VDDA 15 V Power supply voltage VDDD 1.6 1.8 2.0 V

V1 ~ V6 32 VDDA - VDDA-0.1 V

V7 ~ V12 31 VDDA - 3

2 VDDA V γ correction reference voltage

VCOM 31 VDDA - VDDA-0.1 V

Input capacitance Cin - - 5 pF Operation frequency fCPV - 50 - MHz


September 2008



9.3 Electrical Characteristics

Specification Parameter Symbol Condition Min. Typ. Max.

Unit

High level input voltage

VIH1 0.7×VDDD - VDDD

Low level input voltage

VIL1

R0~R7, G0~G7, B0~B7, CLKX, DE, SC, ID0, 0 - 0.3×VDDD

V

0.8×VDDD High level input voltage

VIH2

-

- VDDD

Low level input voltage

VIL2

SDA, SCL

0 - 0.2×VDDD

V

Input leak current IL -1 - 1 µA VDDD static current

IVDDD DE=CLK=R[7:0] =G[7:0]=B[7:0] = ID0= VDDA=0 V

- 30 - µA

10. AC Characteristics

Specification

Parameter Symbol Condition Min. Typ. Max. Unit

Clock pulse width tCLK 20 ns Clock pulse low period

tCLK(L) 8 ns

Clock pulse high period

tCLK(H) 8 ns

Data & DE setup time tSETUP 4 ns Data & DE hold time tHOLD 4 ns

CLKX 80

tCLK( tCLK(LtCLK

20

Data DE

tSETUP tHOLD


September 2008



11. Optical Characteristics Reflective twisted-nematic liquid crystal mode is employed in HX7027. When no

voltage is applied, HX7027 presents bright state (i. e. the normally white mode). The images darken up as the applied voltage increases. Different gray-level can be obtained by tuning the applied voltage

HX7027 is a color-filter-inside (CF-LCOS) design that exhibits color images by single panel.

11.1 Optical Specifications

Item Symbol Value Unit Ambient Temperature

Ta 25±5 �

Ambient Humidity Ha 50±20 %RH Supply Voltage Vdda 15±0.3 V Input Signal According to typical value in “ELECTRICAL

CHARACTERISTICS”

11.2 Optical Specifications

Item Condition Min. Typical Max. Unit Notes

Reflectance %(430~650nm) @F/2.5 15 17 - % Note 1

Uniformity of Reflectance

Measure VESA 9 pts as figure 80 - - % Note 2

Contrast Ratio Full white/black @F/2.5 80 110 - Note 3

x 0.52 0.56 0.6 R

y 0.283 0.323 0.363 x 0.236 0.276 0.316

G y 0.49 0.53 0.57

x 0.11 0.15 0.19 B

y 0.132 0.172 0.212 x 0.295 0.335 0.375

Chromaticity

W y

Unity light source

0.34 0.38 0.42

- Note 4

TR Full bright to dark - 5 - ms

TF Full dark to bright - 10 - ms Respons

e Time gray to

gray average

Gray scale 6x6 matrix - 16 - ms

Note 5

PS. All values are measured the normal direction to the panel.


September 2008



Note 1: Definition of Reflectance� Reflectance is measured by MDIS (Westar Inc.) Measure the Reflectance of gray scale 255 at center point. Figure 1.1 shows the optic measurement system of MDIS. Figure 1.2 shows the polarization direction of incident light.

Figure 1.1 MDIS optic measurement system

Incident Light Polarization Direction

Figure 1.2 Polarization direction of incident light


September 2008


��640X360 0.38” LCOS Module DATA SHEET Preliminary V02Note 2: Definition of Uniformity of Reflectance

Measure the luminance of gray 255 at 9 points by MDIS. Uniformity = Minimum[L(1),L(2),L(3),L(4),L(5),L(6),L(7),L(8),L(9)] /

Maximum[L(1),L(2),L(3),L(4),L(5),L(6),L(7),L(8),L(9)] Note 3: Definition of Contrast Ratio:

Luminance of gray 255 and gray 0 are measured by MDIS at the center point. The contrast ratio is calculated by the following expression.

CR=L255/L0 PS. 1. L255= Luminance of gray level 255

2. L0= Luminance of gray level 0 Note 4: Definition of Chromaticity

WRGB reflection spectrums were measured by MDIS (Westar Inc.) The color chromaticity values are calculated by assuming an equal intensity

visible waveband (430nm~650nm) light source.

Definition of ANSI 9 points on panel


September 2008



Note 5: Definition of Response Time (TR and TF) Measured by HIMAX DISPLAY photo diode sensor & oscilloscope under temperature 45��

Figure 5.1 Definitions of TR and TF Figure 5.2 Definition of gray to gray switching time

�

Figure 5.1 Definition of TR and TF

Figure 5.2 Definition of gray to gray switching time

�

�

�

�

�


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11.3 HX7019 Panel Reflection Spectrum

Reflection spectrum is measured by MDIS (Westar Inc.)

White Spectral Response

0

5

10

15

20

25

30

400 440 480 520 560 600 640 680 720Wavelength (nm)

Ref

lect

ance

(%)

11.4 HX7019 Panel R-V Curves

The R-V Curve is measured by MDIS (Westar Inc.).

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Voltages

Nor

mal

ized

Ref

lect

ance

(%)


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12. Reliability Test

Item Specification Judgment Criteria

HTST : High Temperature Storage Test 85 ºC , 240 hrs , 3 pcs

LTST : Low Temperature Storage Test -40ºC , 240 hrs , 3 pcs

HTHHST : High Temperature and High

Humidity Storage Test

60 ºC , 90%RH , 240 hrs, 3 pcs

TCST : Temperature Cycling Storage

Test

-20 ºC (0.5 hr ) / 60ºC (0.5 hr ), 100 cycles, 3 pcs

HTBT : High Temperature Bias Test 70 ºC , 240 hrs, 3 pcs

HTHHBT High Temperature and High

Humidity Bias Test

50 ºC, 90%RH , 240 hrs, 3 pcs

LTBT : Low Temperature Bias Test -20 ºC, 240 hrs, 3 pcs

ALT Altitude Test

193mbar(12,000m) ,72 hrs,3pcs

After being returned to the normal temperature and being left for more

than 2 hours , the judgment is made

according to Note A�B�C�D

CNTPIO Connector Plug In and Out 20 times

FPCB FPC Bending Test ± 90 degree, 10 times

Package Vibration Proof Follow ISTA Spec, 1 Box

Package Drop Test Follow ISTA Spec, 1 Box

After test , the judgment is made according to Note B�C�D

Note: A. CR after RA test is higher than one half of the initial CR. B. No functional failure. C. No extra mura or defect. D. No obvious deformation or break.


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13. Package Specification

�� Box content�12 trays + cover tray. (Note: Each tray can contain 20 panels). �� Box dimension�368 (L) x 175 (W) x 245 (H) (Unit� mm) �� Gross Weight �Approximately 1.9 kg

13.1 Packing Procedure

12trays + cover 20panels per tray

Sponge

Carton

Label


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13.2 Label Information

Label information indicate grading of LCOS module, part ID, module name and shipping quantity.

14. Green Product

TBD 15. Mechanical Dimension

The mechanical dimensions are for customer’s reference design-in purpose. The mechanical dimensions has indicated as the drawing, HX7019-Module_Mask-DA as shown on the following page.

hx7019atgfa preliminary datasheet--ver0.2read.pudn.com/downloads140/sourcecode/others/...02 2008/...

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