hw/sw co-verification challenges and solutions · 3. 0 p h y 2 pcie gen 2,3 phy e t h e r-n e t h...

Sandeep Gor – Staff Application Engineer

April 9, 2015

HW/SW Co-VerificationChallenges and Solutions

2

Past 10 years: IP bottom-up verification approach

Metric Driven Verification Environment

AutomaticStimulus

Generation

Data and AssertionCheckers

BFM Signal Layer

Coverage Monitor

StimulusSequences

Customer’s Application Specific ComponentsCPU subsystem

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SoC XYZ

DesignIP

RTL Simulator

Comprehensive IP and Sub-

System verification: should

work in ANY SoC context

3

Paradigm Shift In the Market

Ubiquity of software

Move to Standards-based protocols and IPs

Increasing complexity and # of IP’s to be integrated

Application / end-user driven requirements

Shrinking time-to-money

Mixed Signal and Low Power Verification Complexity

Debug consuming over 50% of verification task

Design

Trends

Shift from:

Serial HW/SW

Development

To:

Parallel HW/SW

Development

Shift from:

IP Creation

To:

SoC Integration

4

From serial to parallel HW/SW development

Block Chip PrototypeSilicon

lab test Field test

ROM

ContentDrivers / RTOS / Applications

Diagnostics

& FirmwareHW/SW

Spec

Serial HW->SW Development

Block Chip PrototypeSilicon

lab test Field test

ROM

ContentDrivers / RTOS / Applications

Diagnostics

& FirmwareHW/SW

Spec

Time to market

advantage of 6 to

9 months

Parallel HW->SW Development

Integrate HW/SW Early and Often

HW designed in SW context

Software exposed to Spec changes

5

Ever-growing System Development Complexity

Man

ufa

ctu

rin

g

System QA

Syst

em M

od

elin

g an

d H

W-S

W P

arti

tio

nin

g

Sub-system VerificationSub-systemIntegration

SW Driven SoC Bare Metal / DriversValidation

SoC HW VerificationSoC

Integration

FW/Drivers development

FW/Driverson accurate IP / Sub-System

OS & peripheral Bring-up

on virtual models

Middleware Bring-up

Middleware Development &Testing

Interconnect Performance& Verification

Power convergence

Digital – AMSconvergence

OS & Peripherals Bring-up on accurate HW

Virtual platform creation

System Performance and Power analysis

IP Qualification /Development

IP Verification

Bare Metal on SiliconBring-up

Silicon Test

OS on SiliconBring-up

System on SiliconBring-up

System QA

System Performance & Power analysis

Gate-level Validation

IPS

ub

-Syste

mS

oC

Fir

mw

are

/ D

rive

rs

OS

&

Mid

dle

wa

reA

pp

s

Time

Ha

rdw

are

So

ftw

are

Early Software Development

and HW-SW Validation System

and Silicon

Validation

SoC / Sub-System

Integration & Verification

IP Design and

Verification

Silicon

7

• HW/SW requires High Performance Platforms

• Multiple disconnected SoC simulation environments– Virtual Platform, RTL Sim, HW Acceleration/Emulation, FPGA

Prototype, Post Silicon

• Reducing SoC integration time and effort– Integrating many design IPs and SW components

– Requires significant time and effort to verify integration

– High cost to re-integrate & re-verify changes

– Debug is a major challenge to isolate the root cause

– Verification effort for SoC derivatives is too high

• Verifying that SoC can support required SW applications– Increased software content to develop, integrate, & verify

– SoC must be architected up front to support SW Use Cases

– Must verify against functional, power & performance requirements

Challenges in HW/SW Co-Verification

8

HW/SW Requires High Performance Platforms

SDK

•Highest speed

•Ignore hardware

•Earliest in the flow

Virtual Platform

•Almost at speed

•Less accurate (or slower)

•Before RTL

•Great to debug (but less detail)

•Easy replication

RTL Simulation

•KHz range

•Accurate

•Excellent HW debug

•Little SW execution

AccelerationEmulation

•MHz Range

•RTL accurate

•After RTL is available

•Good to debug with full detail

•Expensive to replicate

FPGA Prototype

•10’s of MHz

•RTL accurate

•After stable RTL is available

•OK to debug

•More expensive than software to replicate

Prototyping Board

•Real time speed

•Fully accurate

•Post Silicon

•Difficult to debug

•Sometimes hard to replicate

9

A System-centric Look at a Modern SoC

Software

Bare

meta

l so

ftw

are

DS

P s

oft

ware

Init

SW

fo

r b

oo

t, p

ow

er,

secu

rity

RTOS

Drivers

Communications L2

Communications L1

Firmware / HAL

Communications L3

Mobile communications

software stack

Bare metal software

Operating Systems (OS)

Drivers

Applications

Middleware

Firmware / HAL

Application software

stack

• Many IPs– Standard IO

– Wifi, USB, PCIe, etc.

– Standard internal interfaces– AXI, ACE etc

– System infrastructure – Interconnect, interrupt

control, power mangement, timers…

– Differentiators – custom accelerators, modem…

• Many cores– Homogeneous

– Heterogeneous

• Lots of software– Part of core functionality

– communication stack, DSP software, GPU microcode…

– User application swinfrastructure– Android, Linux…

10

SoC SW & Verification Challenges and Solutions

Power & thermal profiling and analysis of real world

traffic

Multi-core early SW bring-up and integration

Processor based SW use case testing to verify multi-core cache & IO coherency,

concurrency, PSO, etc…

Debugging of complex multi-core SoC SW scenarios on

RTL sim/emulation platforms

Integrating & verifying 100’s of IPs & SW from ARM,

internal teams, & 3rd parties

Characterizing & analyzing SoC performance &

efficiently debugging issues

Verification of IPs on AMBA interconnect w/ adherence to cache coherent (ACE)

protocol


Drivers

Middleware

Firmware / HAL

Development flow needs to support HW/SW integration & verification environments on multiple platforms

Profiling real traffic

Hybrid for early OS & SW bring-up

SW-Driven use case verification

Synchronized embedded SW debug

on ARM RTL CPU

Rapid SoC integration & verification

SoC verification and performance analysis

VIP

System Development Suite

Virtual

PlatformFormal Tools Emulators

Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

11



traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

12

Full OS level and above SW Validation Challenges

Tapeout Silicon Samples Product Ships

SW

HW

System

Legend

HW Development & Verification

Continuous System Validation

Next Generation SW-Driven SoC Flow


SW Dev

On model


System Validation

SW Dev and Bringup On real HW design, Silicon

SW-Enhanced SoC Flow

Traditional SoC then SW Flow

Continuous SW Development & Bringup

SW Dev and Bringup on Silicon

System Validation

Enabled By

Virtual Platform

FPGA Prototype

Emulation

Powered By

Platform Hybrids

Emulation + Virtual Platform + FPGA

13

ARMv8/v7 Early OS & SoftwareBring Up

Customer RTL

RTL

TLM

Mem I/F

Component Color Key

SoC Interconnect Fabric

DDR3 Display

INTC

Timer

CSIDSI

UART

GPUMemory

ControllerSATAUSB3

…

System

Boot

Peripheral Fabric

USB2

Ethernet

SW Integrator

UARTsTimers

ARM Fast

Models A57 x 4 A53 x 2

AXI4 or ACE-Lite Interrupts

Smart DDR

model

eMMC

Interrupt

Manager

TLM

/ RTL

Bridge

Reconfigurable Interconnect

CPU Sub-system RTL I/F

Reset

Manager

TLM

MemorySmart

DDR

Resets

Virtual

Platform

Emulator

AV

IPValidate SoC + OS at 5-10 MHzHigh-performance memory coherency

Execute SW at 100MHzWith standard or custom processor models

Reduce SoC Debug EffortSystem Messages

HW / SW Debuggers

Plug and Play Integration with RTLSoC-specific transactors and RTL I/F

14



traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

15

The Eras of VerificationLooking at the past and into the future

SW-Driven

Verification Era

Directed Testing Era

(aka “Stone Age)

HVL Coverage Driven Verification Era

- Simple ad-hoc testbenches

- Tests created by hand

- Not scalable – requires more engineers to scale

- Difficult to achieve good quality

- Constrained-random stimulus automates test creation

- Coverage metrics used for coverage closure

- Ideal for exhaustive “bottom up” IP/Subsystem verification

- Scale verification by automatically generating more tests

- Best suited for RTL simulation on IP and subsystem

- SoC “top down” use case testing

- Automated constrained random generation of SW tests

- With coverage metrics

- Reuse across simulation, emulation, FPGA prototype, and post-silicon

1980

1990

2000

2010

2020

16

SoC level Verification & Validation Requirements

• How to communicate/share use cases between users

• How to Create and Reuse Use Cases from IP to SoC

• How to use c code natively on many cores and communicate between cores

• How to automate laborious manual C test writing & debug and add metrics

• How to run use cases across all execution platforms

Platform

Virtual Platform Simulation Emulation FPGA Prototype Silicon Board

User

ArchitectHW

Developer

SW

Developer

Verification

Engineer

SW Test

Engineer

Post-silicon

Validation

Engineer

Vert

ical R

euse

Horizontal Reuse

Use Case Reuse

Scope

(Integration)

IP

Sub-System

OS & Drivers

Bare Metal SW

System on Chip

(HW + SW)

Middleware

(Graphics, Audio,

etc..)

17

Solution : Test Creation at Abstract Level

18

Solution

• Faster complex SoC test creation

• Abstraction: UML style use-case diagrams

• Automation: system use-case test

generation

• Portability: reuse across all execution

platforms

• Measurement: SoC-level HW/SW

coverage metrics

21



traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

22

Additional cycles are needed for system-level power analysis

OFF

SoC Power Analysis Requires “Deep” Cycles(@100MHz for 10 secs => 1 Billion cycles)

time

Power

Deep cycles:Dynamic power profiling calculates average power over long run w/ “real” stimulus & SW interactions

Identify and analyze peak and average power at system level

Local Max Case:

Simulation captures narrow window

Analyze power with

real SW scenarios

or benchmarks

On

OnOn

On

On

On

On

OFF

OFF

OFFOFF

OFF

OFFOFF

On

OFF

OFF

OnOn

On

On

On

On

OFF

OFF

Component-levelSystem-level

Simulation Run

Sample frequency

Operating Systems

(OS)

Drivers

Middleware

Firmware / HAL

23

Dynamic Power Analysis

RTL/Gates

• Peak and average power consumption

over any time window

• Instance-based power navigation

• System-level power analysis for large

SoC (with software)

• MHz Throughput

• No emulation capacity overhead

• Higher accuracy

• Calculate peak and average power

Emulator

Technology Libraries

OptionalCPF/U

PF

File*

Dynamic Power Analysis

24

DPA should be Flexible Solution for HW/SW Co-Verification

ARM RealView

Software Debugger

Simulator

HDL DebuggerDPA option

Power Profiler

A unique platform tuned for high-performance HW/SW co-verification and

power profiling at the system-level perspective

Emulator

High-performance verification

platform from RTL acceleration

to system emulation

SW

25



traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

26

ARM v8 SoC HW/SW Debug

Sim

ula

tor

Em

ula

tor

Synchronized with

design & testbench

debugger

A53/A57 Post-process SoC

Debug

• Integrated & synchronized

HW/SW debug with testbench

• For verification & design teams

• Enables off-line debugging

Embedded C source

code debug with

assembly view

SW Variable

tracing

27

ARM v8 SoC HW/SW Debug

A53/A57 JTAG SW Debugger

• Interactive SW debugging on

Emulator

• Support for SW developers

using RealView, Lauterbach,

etc..

JTAG Debugger

support for SW

Developers on

Emulator

ARM RealView

Debugger

Lauterbach

Debugger

Em

ula

tor

28



traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

29

• Significant engineering effort required to integrate & verify IPs (Customer IPs + 3rd Party IPs)– Each IP has many configuration options

– IPs must be configured consistently together with SW Drivers & VIPs

– Largely a manual, error-prone effort

• Need to develop multiple environments on different platforms for verification/validation & SW bring-up/integration– Virtual Platform, Simulation, Emulation, FPGA Prototype, Post-Silicon

– Cumbersome integration work of RTL/SW/VIP repeated per platform

– Some platforms have special requirements requiring model changes

• Late spec changes and/or derivative platforms are difficult to support within short market windows– Shift from ARM v7 to v8 was not planned by many mobile projects

Challenges in ARM SoC Integration

30

Flow Automation

Design Verification

Environment

Package Add Meta-Data

Generate

Verification

EnvironmentAssemble

RTL

Package

3rd Party and

Customer

IP & VIP

Subsystem to SoC

Design & Verification

Environments

IP & VIP

31

Factory Flow

Virtual

Platform

Simulation

Platform

Emulation

Platform

Prototyping

Platform

3rd Party IP

ARM IP

Customer IP

VIP

TB Integrator

SoC

Project

Library

Build & Run

Generator

Hybrid TLM/RTL

Assembly

UVM e/SV TB

Assembly

Interconnect

WorkBench

Embedded TB

Assembly

RegApp

SW Assembly

VIP

Packager

Ethernet VIP

ARM SoC Design & Verification Environment

A57

FM

A53

FM

PCIE

Ctrl

PCIE

VIP

CSI

Ctrl

CSI

VIP

DDR MMAV

DDR Ctrl

BBDSI

Ctrl

DSI

VIP

I2C

Ctrl

I2C

VIP

BBBB BB

IPXACT

Package IP, VIP,

eSW, Meta-data

Generate build

& run scripts

Rapidly generate

SoC DVE configs

GUI for capturing SoC design

& verification environment with

additional meta-data

IP

Packager

ARM

32

• Rapid generation of ARM SoC design & verification environments – Pre-packaged ARM FM/RTL IP + CDNS IP/VIP

– For performance modeling and analysis

– For SW bring-up and development

– For HW/SW integration and verification

– Targeting multiple execution platforms, including hybrid platforms

• Reduce errors in manual integration based on paper specs– Single source, machine-readable specification data

• Improve turn-around time for late spec changes– By automating integration tasks

• Improve time to market for SoC derivatives– Quickly generate and verify incremental changes to SoC platform

Advantage for Automation in SoC Integration

33



traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

34 © 2013 Cadence Design Systems, Inc. All rights reserved.

Representative ARM SoC

Corelink CCI-400

A53 Cluster A57 Cluster

CustomerGPU

S4 S3 S2 S1 S0

ADB ADB ADB

ADB

Corelink GIC-400

Corelink NIC-400

PCIeRC

LCDDMA

V8 Mobile

Example

System

Corelink NIC-400 (2x1)

ADB Co

relin

k N

IC-4

00ADB ADB

Corelink TZC-400

Customer DDR Controller

F0F1F2F3

On-Chip ROM

SRAM

Video SRAM

#2

#4

L2 Cache

CustomerDMA

ADB

#1

#3

#2

#4

L2 Cache

#1

#3

Timers

UART

Corelink NIC-400 Corelink NIC-

400

IP IP IPIPIP

DVFS CLK/PSO

Domain

CLK/PSO

Domain

SystemControl

Processor

Coherent

Masters

Non-Coherent

Masters

IP

ADB ADB

ADB


Corelink CCI-400


CustomerGPU

S4 S3 S2 S1 S0

ADB ADB ADB

ADB

Corelink GIC-400

Corelink NIC-400

PCIeRC

LCDDMA

V8 Mobile

Example

System


ADB Co

relin

k N

IC-4

00ADB ADB

Corelink TZC-400


F0F1F2F3

On-Chip ROM

SRAM

Video SRAM

#2

#4

L2 Cache

CustomerDMA

ADB

#1

#3

#2

#4

L2 Cache

#1

#3

Timers

UART


400

IP IP IPIPIP

DVFS CLK/PSO

Domain

CLK/PSO

Domain

SystemControl

Processor

Coherent

Masters

Non-Coherent

Masters

IP

ADB ADB

ADB

Performance Challenges

What is the latency of the processor

clusters to memory paths including all async bridges ?

What is the latency of the processor

clusters to memory paths including all async bridges ?


Corelink CCI-400


CustomerGPU

S4 S3 S2 S1 S0

ADB ADB ADB

ADB

Corelink GIC-400

Corelink NIC-400

PCIeRC

LCDDMA

V8 Mobile

Example

System


ADB Co

relin

k N

IC-4

00ADB ADB

Corelink TZC-400


F0F1F2F3

On-Chip ROM

SRAM

Video SRAM

#2

#4

L2 Cache

CustomerDMA

ADB

#1

#3

#2

#4

L2 Cache

#1

#3

Timers

UART


400

IP IP IPIPIP

DVFS CLK/PSO

Domain

CLK/PSO

Domain

SystemControl

Processor

Coherent

Masters

Non-Coherent

Masters

IP

ADB ADB

ADB


What is the latency of the processor clusters to

memory paths including all async bridges ?

What is the bandwidth of the paths from IP with high bandwidth demands to

memory ?


Corelink CCI-400


CustomerGPU

S4 S3 S2 S1 S0

ADB ADB ADB

ADB

Corelink GIC-400

Corelink NIC-400

PCIeRC

LCDDMA

V8 Mobile

Example

System


ADB Co

relin

k N

IC-4

00ADB ADB

Corelink TZC-400


F0F1F2F3

On-Chip ROM

SRAM

Video SRAM

#2

#4

L2 Cache

CustomerDMA

ADB

#1

#3

#2

#4

L2 Cache

#1

#3

Timers

UART


400

IP IP IPIPIP

DVFS CLK/PSO

Domain

CLK/PSO

Domain

SystemControl

Processor

Coherent

Masters

Non-Coherent

Masters

IP

ADB ADB

ADB


What is the bandwidth and latency of the paths from real-time IP to memory ?

What is the bandwidth and latency of the paths from real-time IP to memory ?


• Create and maintain Performance Testbench

• No standard Performance Monitors which are protocol agnostics

• Analysis of the Performance Data

Performance Infrastructure Challenges


Solution

Interconnect

Workbench

Assembly

Performance

Measurements

UVM Testbench

IP-specific

Traffic Profiles

SoC Traffic

Testbench

CoreLink 400

System IP

RTL & IP-XACT

Simulator

Performance

Analysis

Verification

Closure

Interconnect

Workbench

Analysis &

Debug

Performance

Analyzer

For Interconnect IP Integration•Performance of use case traffic loads

•Verify configuration functionality

For SoC Integration•Validate performance in context of IPs

Benefits Shorten performance tuning and analysis

iteration loop from days to hours

Reduce testbench development time from

weeks to hours

Tune

Architecture

Manual

SoC

Testbench

Automate Simulate Analyze

VIP Library

for AMBA®

User

Meta-Data




traffic











protocol


Drivers

Middleware

Firmware / HAL






on ARM RTL CPU



VIP


Virtual


Prototyping

PlatformPlanning &

Management

Debug

ToolsSimulatiors

41

Cache Coherent ACE Verification IP

• Generates coherent stimuli and

responds to snoop bursts

• Includes cache model

• Can be configured as ACE or ACE-lite

• Monitors protocol correctness;

• Collects coverage

• Includes cache model

• Can be configured as ACE or ACE-lite

Legend: DUT VIP

Cache Cache

Mem Mem

M2Passive Master

S3Passive Slave

Mem

Cache

M2DUT Master

S1Active slave

S2DUT slave

S3DUT slave

M1Active Master

Cache

• Responds to read/write

transactions

• Model sparse memory

• ACE–lite port• Checks protocol correctness;

• Collects coverage

• ACE-lite

Corelink CCI-400

S4 S3

42

• Major challenges and solutions

– Early SW Bring-up & HW/SW Integration– Hybrid for early OS & SW bring-up

– SW-driven use case verification– Abstract level test creations for horizontal and vertical reuse is the key

– Power profiling and analysis of real world traffic– Dynamic power analysis by capturing hardware activities from use-cases/software runs on

emulator and feed it to Synthesizer

– HW/SW debug– Debgger with HW/SW views

– JTAG SW Debugger support for Software

– Rapid IP Integration– Automation is the key

– SoC performance characterization, analysis, & verification– Automation in testbench creation

– Analysis tools

– Advance protocol checking– Advance VIPs for ACE/CHI are useful for protocol compliance

Summary

hw/sw co-verification challenges and solutions · 3. 0 p h y 2 pcie gen 2,3 phy e t h e r-n e t h...

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