hv440 application note hv440 high voltage ring...

1

HV440 High Voltage Ring Generatorby Jimes Lei, Applications Engineering Manager

IntroductionThe Supertex HV440 is used for implementing a pulse widthmodulated high voltage ring generator for telecommunicationapplications. The HV440 can operate in both closed-loop oropen-loop. A closed-loop design is more complex but providesbetter load regulation and lower THD compared to an open-loopdesign.

In this application note, a closed-loop design is discussed. Theoutput ring voltage is 62VRMS at 20Hz with load capabilities of 5RENs and 20 RENs.

The telephone must see a minimum of 40VRMS, otherwise ringingis not guaranteed. Ring generators are typically sinusoidal.Common ring frequencies are 20Hz and 25Hz. Telephone loadsare rated in RENs (ring equivalent number). One North AmericanREN is equivalent to 6930Ω in series with 8.0µF. For a giventelephone line, the ring generator must be able to drive 5 RENs.

The output MOSFETs integrated in the HV440 can drive up to 5North American RENs. For applications requiring loads greaterthan 5 RENs, the HV440 can also drive external SupertexMOSFETs, TP2522N8 and TN2524N8 for loads of up to 20RENs. Complete schematics for a 5 REN and a 20 REN ringgenerator with their bill of materials can be found at the end of thisapplication note.

General Circuit DescriptionThe implementation of the ring generator circuit is very similar tothat of a class D amplifier. Referring to Figure 1, a logic voltage

high frequency pulse width modulated sine wave signal isgenerated by the sine wave reference, ramp generator, and erroramp. The PWM signal is the input signal for the HV440. TheHV440 will amplify the 0 to 5V signals to a negative high voltage(VNN1) and a positive high voltage (VPP1). The LC filter will convertthe high voltage PWM signal from the HV440 to a high voltagesinusoidal waveform which is used as the ring output. A feedbackpath is connected to the ring generator output and is comparedto the sine wave reference. Any differences between the sinewave reference and the ring generator output are corrected byadjusting the pulse widths controlled by the error amplifier. Thevarious blocks shown in Figure 1 are discussed separately inmore detail in the following sections.

Sine Wave ReferenceA low voltage reference sine wave signal is required to generatethe output ringer signal. A wien-bridge oscillator was chosen togenerate the reference sine wave as shown in Figure 2. TheWien-Bridge Oscillator was selected for its simplicity. Otherways of generating the reference sine wave are by using sinewave generator integrated circuits such as an Exar XR-2206, aMicro Linear ML2035, or a Philips PCD3311C.

However, the referenced signal is not limited to sinusoidalwaveforms. Trapezoidal ringing waveform with crest factorsbetween 1.2V to 1.6V are also acceptable. There are two mainadvantages to using trapezoidal waveforms over sinusoidalwaveforms. They are: a) It is easier to generate, b) With a givenpeak-to-peak voltage, higher RMS voltages can be obtained

Sine WaveReference

Ri Rf

RampGenerator

Error Ampand PWM HV440

Sine WaveRing Output

L

C

Figure 1: Conceptual Block Diagram

HV440Application Note

AN-H37

11/12/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liabilityindemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due toworkmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to theSupertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

2

when using crest factors of less than 1.414. The disadvantage ofusing trapezoidal ring generators is that sinusoidal ring generatorsare more widely accepted.

Three main parameters need to be considered when designingthe sine wave reference. They are as follows:

1) DC offset voltage,

2) Peak-to-peak amplitude, and

3) Ringing frequency.

1) DC Offset VoltageThe Wien-Bridge Oscillator operates on a single 5V supply, VDD.The sinusoidal signal generated by the Wien-Bridge Oscillatorneeds to be superimposed on a DC offset voltage set by R1, R2,R3, C2, and A1. The DC offset voltage level should be set in sucha way that it will not saturate and cause the sine wave signal tobe clipped.

Op amp A1 is a National LM2902 which has an output voltageswing of 0V to VDD-1.5V. For a VDD voltage of 5V ± 5%, the worstcase VDD voltage would be 5V-5% which is 4.75V. When sinkingcurrent, the voltage drop can be 0.5V. The voltage for the sinewave should therefore be in between 0.5V and 3.25V. A DCoffset of 2.0V was selected. A 2V peak-to-peak amplitude waschosen for the sine wave. The output of A2 will therefore swingfrom 1V to 3V. This leaves 0.5V margin for the low end of the sinewave and 0.25V margin for the high end of the sine wave.

R1, R2, and R3 divides the VDD voltage to 2.0V when VDD=5.0V.C2 is used as a DC coupling capacitor to filter any AC noise thatmay be on VDD. A1 is used as a unity gain buffer to generate a lowoutput impedance voltage reference. The DC offset voltage withthe values shown in Figure 2 is:

DC offsetR R

R R RV

K KK K K

V

V

DD=+

+ +

=Ω+ Ω

+ +

=

2 3

1 2 3

1 82 4 8710 1 82 4 87

5 0

2 0

x

x. .

. ..

.

Ω Ω Ω

R3 is used to generate a different DC voltage to set the output ringgenerator DC offset. The voltage generated by R3 is discussedin the error amplifier section.

R34.87K

R21.82K

R110.0K

VDD

C210nF

A1A2

R6

1.0K

R7

576Ω

R8

1.50K

D1

D2

C339nF

R4

205K

R5

205K C439nF

Output Sine Wave

Figure 2: Wien-Bridge Oscillator 2) Peak-to-Peak AmplitudeThe amplitude is determined by the two clamping diodes D1 andD2. Their forward voltage drop sets the initial conditions indetermining the amplitude. It should be kept in mind that in orderfor oscillation to occur in a Wien-Bridge circuit, the gain must beequal to or greater than 3. The gain is determined by R6, R7, andR8 in the following equation:

GainR R

R

KK

= ++

= ++

=

1

1576 1 50

1 00

3 076

7 8

6

Ω ΩΩ

..

.

D1 and D2 are in parallel with R8. When D1 or D2 are forwardbiased, they will be shunting R8, thereby lowering its effectiveDC resistance. The DC gain of 3.076 will start to decrease. If thegain becomes less than 3, oscillation will stop. The forwardvoltage drop, Vf, of the D1 and D2 will settle to a value such thatits DC resistance in parallel with R8 will give a DC gain of 3. Theoutput amplitude of A2 can be approximated with the followingequation:

VV K

K R RP Pf

− =( )

− +( )2

3

3 6 7x

Ω

Ω

The forward diode drop of D1 and D2 can be determined byevaluating its I-V curve. The curve is shown in Figure 3. The biascurrents for D1 and D2 should be set relatively high to minimizeany leakage current effects.

For a DC gain of 3, letting RD be the DC resistance of D1 and D2which are in paralllel with R8, RD can be determined by thefollowing calculation:

HV440 High Voltage Ring Generator

Figure 3: Forward bias current vs.Forward Diode Voltage

0 100 200 300 400 500 6000

10

20

30

40

50

VF (mV)

I F (

µA)

diode curve

RD=28.1KΩ

3

3 1

22

576 1 5 2 1 1 5

2 1 576 1 5

28 1

7

6

7 8 6 8

6 7 8

8

8= ++

=−− −

=( ) − ( )

− −

=

+R

Rsolving for R

RR R R R

R R R

K K K

K K

K

R R

R RD

D

D

D ,

. ..

.

Ω Ω Ω Ω

Ω Ω

Ω

x x x

x

Referring to the I-V curve on Figure 3, VF is 425mV for an RD of28.1KΩ. The sine wave reference amplitude is thereforetheoretically 1.8V peak-to-peak. The peak-to-peak voltage isexpected to be slightly greater than what the theoretical valuespredict due to the response time of the circuit. Oscillation will notstop instantaneously once its gain is less than 3. It will be slightlyless than 3. The actual value for the gain was measured to be2.94. The measured output voltage was 1.95V peak-to-peak.

3) Ringing FrequencyThe sinewave frequency is determined by R4, R5, C3, and C4.The sinewave frequency is set for 20Hz which is commonly usedin North America. Different countries will require differentfrequencies. For example, 25Hz is commonly used in Germany.By changing the values of R4 and R5, different frequencies canbe easily achieved. For 20Hz, 205KΩ is used for R4 and R5, and39nF is used for C3 and C4. The calculation for the frequency isshown below.

freqR R C C

K K nF nF

Hz

=

=

=

1

2

1

2 3 14 205 205 39 39

19 9

4 5 3 4π

x x x x x.

.

Ω Ω

Ramp GeneratorFigure 4 is the voltage ramp generator circuit consisting of R9,R10, R11, R12, R13, C5 and Comp1. The ramp frequency setsthe PWM frequency of the ring generator. The PWM frequencyfor the 5 REN circuit is different from the 20 REN circuit to avoidoutput inductor saturation.

The ramp generator is based on a simple R-C charge anddischarge circuit. The waveform does not need to be an ideallinear ramp because the overall circuit is closed loop. Any non-linearities on the ramp voltage will be taken into consideration bythe error amplifier. The ramp output voltage will swing from VLLto VUL. Its voltage and frequency can be approximated with thefollowing equations:

VR R R R

R R R R R R RV

VR R

R R R R RV

t R CVV

t R R CV VV V

V

UL DD

LL DD

DISLL

UL

CHGUL FINAL

LL FINAL

FINAL

=+ +( )

+( ) + + +( )

=+ +( )

= −

= − +( ) −−

10 9 11 12

9 11 12 10 9 11 12

10 11

10 11 9 10 11

13 5

12 13 5

x

x

ln

ln

== −( )+

+

=+

V VR

R RV

ft t

DD UL UL

CHG DIS

11

11 12

1

where,

VDD = 5V supply

VUL = Upper limit

VLL = Lower limit

tDIS = Discharge time

tCHG = Charge time

VFINAL = Final charge value

VDD = 5V supply

f = Ramp frequency

R910.0K

R105.11K

R113.32K

R1310.0K

C5

VDD

R121.00K

Comp 1

Ramp Output

Figure 4: Voltage Ramp Generator


4

Using the values shown in Figure 4:

For 5 REN circuit, C5=680pF For 20 REN circuit, C5=330pF

VUL = 3.14V VUL = 3.14V

VLL = 0.84V VLL = 0.84V

VFINAL = 4.57V VFINAL = 4.57V

tDIS = 8.97µs tDIS = 4.35µs

tCHG = 7.17µs tCHG = 3.48µs

f = 62kHz f = 128kHz

The voltage ramp generator will have a typical voltage swing of0.84V to 3.14V at a frequency of 62kHz for the 5 REN circuit and128kHz for the 20 REN circuit. The voltage swings are well withinthe operating input voltage range of comparators and outputvoltage swing of the op amps.

Error Amplifier / PWMPulse width modulated (PWM) signals need to be generated asthe input signals for the Supertex HV440. This is accomplishedby using op amp A3 and comparator comp 2 as shown in Figure5. A3 is configured as an error amplifier. It compares the desiredoutput ringing voltage with the reference sine wave generatedfrom op amp A2. The output of A3 is compared to the rampgenerator via comparator comp2. The output of comp2 is thePWM output operating at the same frequency as the rampgenerator frequency. The PWM output duty cycle can vary from0% to 100% controlled by the output of the error amplifier, A3. Asthe output of A3 increases, the duty cycle also increases.

R14 and R15 set the overall gain for the circuit. The DC offset forthe output ringer voltage is determined by setting the appropriatevoltage on C1 via resistor divider R1, R2, and R3. The circuit in

Figure 5 is set for a nominal output voltage of 62VRMS and a DCoffset of -48V. The following equations can be used to set theoutput RMS voltage and DC offset:

Reference Sine Wave 2.0VDC 0.69VRMS= +

=−

+ + +

+

=

DC offset VR

RV

RR R R

RR

OutputRR

DD

RMS

2 0 1

0 69

15

14

3

1 2 3

15

14

15

14

.

.

C6 and R16 sets the cutoff frequency for A3. If the cutofffrequency is too high, it will amplify noise whereas if it is too low,it will cause output distortion. The frequency should be muchgreater than the ringing frequency and much lower than thePWM frequency. C6 and R16 are set at 1.6kHz.

Supertex HV440The block diagram for the Supertex HV440 is shown in Figure 6.It operates from a positive high voltage supply, VPP1, a negativehigh voltage supply, VNN1, and a low voltage supply VDD. Maximumoperating differential voltage (VPP1-VNN1) is 220V. The VDDsupply is designed for 5V ± 5%. Circuit operation for the followingsections are described:

1) Logic block,

2) Linear regulators,

3) Current sense, and

4) Output MOSFET/gate driver.


Figure 5: Error Amplifier/PWM

A3

C610nF

R14

11.0K

R16

10.0K

R171.0K

R15

1.00M

From OutputRinging Voltage

From Op Amp A2Sine Wave Reference

PWM OutputFrom RampGenerator

5.0V

comp2

C110nF

R110.0K

R21.82K

R34.87K

VDD

5

1) Logic BlockThe HV440 can be used in 2 different modes: 1) Single input, or2) Dual input. In the single input mode, the NIN pin is used. A logichigh on Nin will turn on the P-channel MOSFET pulling the outputto VPP1. A logic low on NIN will turn on the output N-channelMOSFET pulling the output to VNN1. The HV440 has a built inmaximum deadband of 200ns to ensure no crossover conductionon the output. In this mode, the output is going to be VPP1 or VNN1.In the dual input mode, the output P-channel and N-channelMOSFETs can be controlled independently via inputs PIN andNIN. The logic truth table is shown on Figure 7. In this applicationnote, the single input mode is used.

Logic

HighVoltageLevel

TranslatorLinearReg.

CurrentSense and

Driver

HighVoltageLevel

Translator

LinearReg.

CurrentSense and

Driver

VDD

PIN

NIN

EN

Mode

Gnd

VDD

VPP1

VPsen

PGATE

VPP2

HVOUT

PGND

VNN2

NGATE

VNsen

VNN

Figure 6: HV440 Detail Block Diagram


stupnIcigoL stuptuO

N NI P NI edoM raBNE V ETAGP V ETAGN VH TUO

L L H L V 2PP V 1NN V 1PP

L H H L V 1PP V 1NN ZhgiH

*H *L H L V 2PP V 2NN *

H H H L V 1PP V 2NN V 1NN

L X L L V 1PP V 2NN V 1NN

H X L L V 2PP V 1NN V 1PP

X X X H V 1PP V 1NN ZhgiH

lliW.sTEFSOMlennahc-NdnalennahC-PhtobnosnruT*Vtnuhs 1PP Vot 1NN .

Figure 7: Logic Truth Table

6

2) Linear RegulatorsThe HV440 has two high voltage linear regulators which generatevoltages VPP2 and VNN2. VPP2 is typically 16V below VPP1. VNN2 istypically 10V above VNN1. VPP2 and VNN2 will track the highvoltage supplies VPP1 and VNN1. These are generated to provideproper gate-to-source turn on voltages for the internal andexternal MOSFETs. Discrete MOSFETs typically have gate-to-source voltage ratings of ±20V maximum. A low voltage capacitorof 0.1µF is recommended to provide the peak currents requiredduring the switching transition.

3) Current SenseThe current sense pins PSENSE and NSENSE are cycle by cyclecurrent sense. They are independent of each other. The voltagetrip point is set at a nominal voltage of 1.0V. Different senseresistor values can be selected to sesfiJhe maximum allowablepeak currents. This protects the device and the output MOSFETsfrom damage during a fault short circuit condition. The currentsense is reset on the rising edge of the next clock cycle.

4) Output MOSFETs and Gate DriversThe internal output MOSFETs in the HV440 can drive up to 5RENs. The diodes in series with the internal MOSFETs are toprevent current from flowing the opposite direction. For loadsgreater than 5 RENs, external MOSFETs can be used. The gatedriver, PGATE and NGATE, on the HV440 is designed to driveexternal Supertex MOSFETs TP2522N8 and TN2524N8 for loadrequirements of up to 20 RENs. When using external MOSFETs,the internal MOSFETs can be left unconnected by leaving HVOUTunconnected.

OutputThe output section for the 5 REN circuit is shown on Figure 8. A5 REN load has an impedance of 1400Ω at 20Hz. The averagepeak current going to the load can be approximated by 110V/1400Ω = 79mA. A large inductance value for L1 is desirable tokeep the PWM switching frequency low to minimize switchinglosses. The inductor current should be kept as low as possiblebut no less than 79mA. The inductor, L1, was selected based onthe largest standard value available with a 79mA rating or higherin a reasonably small package. L1 was selected to be a 10mH,120mA inductor.

The peak current for the inductor can be approximated with thefollowing equation:

IV V

L fPEAKPP NN=

−1 1

2 1x x

where, VPP1 = Positive high voltage supply

VNN1 = Negative high voltage supply

L1 = 10mH inductor

f = PWM frequency

R18 and R19 set the current limit going through L1. The nominalvoltage sense across the sense resistor is 1.0V. A 3.9Ω senseresistor was selected for a current limit of 256mA.

Capacitor C9 was selected such that the LC resonant frequencyis at least ten times greater than the ringing frequency and tentimes lower than the PWM frequency. A 0.22µF capacitor waschosen for C9 for a resonant frequency of 3.4kHz.


Figure 8: HV440 Output LC Filter for 5 REN

mode

PIN

Gnd

PGnd

VPP2

VPgate

HVOUT

VNgate

C70.1µF R18

3.9Ω

C114.7µF

D3BAS21

C90.22µF

10mH

L1Sine WaveRing Output

1

VPP1

16

14VPsen

13

15

11

12

10

VNsen

VNN2

C80.1µF

C13680pF C12

4.7µF

VNN1U3

9 R193.9Ω

D4BAS21

VDD

NIN

EN

8

6

4

7

5

3

2

To FeedbackResistors

5V Supply

From Outputof Comp 2

On/Off Control

7

Figure 9 is the output section for the 20 REN circuit. Thecomponents are selected in a similar manner as described in the5 REN circuit. Transistors TP2522N8 and TN2524N8 are usedfor Q1 and Q2 to accommodate for the higher REN loadrequirement. The internal transistors in the HV440 are not used.The HVout pin is therefore left unconnected.

Figure 9: HV440 Output LC Filter for 20 REN

mode

PIN

Gnd

PGnd

VPP2

VPgate

HVOUT

VNgate

C70.1µF R18

1.2Ω

C114.7µF

D3BAS21

C90.47µF

1.0mH

L1Sine WaveRing Output

1

VPP1

16

14VPsen

13

15

11

12

10

VNsen

VNN2

C80.1µF

C13680pF C12

4.7µF

VNN1U3

9 R191.2Ω

D4BAS21

VDD

NIN

EN

8

6

4

7

5

3

2

To FeedbackResistors

5V Supply

From Outputof Comp 2

On/Off Control Q1

Q2


8

Lab test ResultsThe ramp generator, sine wave reference, and output ring voltage are shown on Figures 10 and 11 for the 5 REN circuit.

The ramp generator, sine wave reference, and output ring voltage are shown on Figures 12 and 13 for the 20 REN circuit.

Figure 10: Ramp Output Figure 11: Ringer Output

Figure 12: Ramp Output Figure 13: Ringer Output


9

Fig

ure

14:

HV

440

5 R

EN

Rin

g G

ener

ato

r

C1

10nF

R8

4.87

K

R2

1.82

K

R1

10.0

K

5.0V

C2

10nF

1/4

U1

1/4

U1

1/4

U2

1/4

U1

R9

10.0

K

R10

5.11

K

R6

1.0K

R7

576Ω

R8

1.50

K

D1

D2

C3

39nF 2%

R4

205K

R5

205K

C4

39nF

2%

R11

3.32

K

R13

10.0

K

C5

680p

F5%

5V=

OF

F

0V=

ON

C10

2.2µ

F10

V

C6

10nF

R14

11.0

K

R16

10.0

K5%

R17

1.0K

5.0V

8

VD

D

6

NIN

7

EN

4 m

ode

5

PIN

3 G

nd

2 P

Gnd

Logi

cC

ontr

ol

R15

1.00

M

Driv

er1 VP

P1 VP

sen

VP

P2 16 14 15 13 11 12 10

VP

gate

HV

OU

T

VN

gate

Driv

erV

Nse

n

VN

N1

9

VN

N2

C8

0.1µ

FC

1368

0pF

C7

0.1µ

FR

183.

9Ω5%

C11

4.7µ

F10

0V

D3

BA

S21

D4

BA

S21

R19

3.9Ω

5%

C9

0.22µ

F25

0V

C12

4.7µ

F25

0V

10m

H

L1

Sin

e W

ave

Rin

g O

utpu

t

HV

440

U3

R12

1.00

K

1/4

U2

Un

less

no

ted

oth

erw

ise:

All

resi

stor

s 1/

8W, 1

%A

ll ca

paci

tors

50V

, 10%


10

HV440: 5 REN Ring Generator Bill of Materials

giseD noitpircseD eulaV loT gnitaR

1R rotsiserpihcmlifkcihT K0.01 Ω %1 W8/1



4R rotsiserpihcmlifkcihT K502 Ω %1 W8/1



7R rotsiserpihcmlifkcihT 675 Ω %1 W8/1








51R rotsiserpihcmlifkcihT M00.1 Ω %1 W8/1



81R rotsiserpihcmlifkcihT 9.3 Ω %5 W8/1


1C roticapacpihccimarecR7X Fn01 %01 V05


3C roticapacmliftnuomecafruS Fn93 %2 V05


5C roticapacpihccimarecOPN Fp086 %5 V05


7C roticapacpihccimarecR7X Fµ1.0 %01 V05


9C roticapacmlifretseylopdezillateM Fµ22.0 %01 V052

01C roticapacpihccitylortcelemulatnaT Fµ2.2 %02 V01

11C roticapaccitylortcelemunimulA Fµ7.4 %02 V001


31C roticapacpihccimarecR7X Fp086 %01 V05

1L rotcudnI Hm01 %51 Am021

2D-1D yrevocertsaf,yarraedoiD 99VAB — V07

3D yrevocertsaf,edoiD 12SAB — V052


1U CIreifilpmalanoitarepodauQ M2092ML — —

2U CIrotarapmocdeepshgihlauD M3092ML — —

3U CIrotareneGgniRegatloVhgiH GW044VH — —


11

Fig

ure

15:

HV

440

20 R

EN

Rin

g G

ener

ato

r

C1

10nF

R8

4.87

K

R2

1.82

K

R1

10.0

K

5.0V

C2

10nF

1/4

U1

1/4

U1

1/4

U2

1/4

U1

R9

10.0

K

R10

5.11

K

R6

1.0K

R7

576Ω

R8

1.50

K

D1

D2

C3

39nF 2%

R4

205K

R5

205K

C4

39nF

2%

R11

3.32

K

R13

10.0

K

C5

330p

F5%

5V=

OF

F

0V=

ON

C10

2.2µ

F

C6

10nF

R14

11.0

K

R16

10.0

K5%

R17

1.0K 5%

5.0V

8

VD

D

6

NIN

7

EN

4 m

ode

5

PIN

3 G

nd

2 P

Gnd

Logi

cC

ontr

ol

R15

1.00

M

Driv

er1 VP

P1 VP

sen

VP

P2 16 14 15 13 11 12 10

VP

gate

HV

OU

T

VN

gate

Driv

erV

Nse

n

VN

N1

9

VN

N2

C8

0.1µ

FC

1368

0pF

C7

0.1µ

FR

181.

2Ω5%

C11

4.7µ

F10

0V

D3

BA

S21

D4

BA

S21

R19

1.2Ω

5%

C9

0.47µ

F25

0V

C12

4.7µ

F25

0V

1.0m

H

L1

Sin

e W

ave

Rin

g O

utpu

t

HV

440

U3

Q1

TP

2522

N8

Q2

TN

2524

N8

R12

1.00

K

1/4

U2

Un

less

no

ted

oth

erw

ise:

All

resi

stor

s 1/

8W, 1

%A

ll ca

paci

tors

50V

, 10%


12

HV440: 20 REN Ring Generator Bill of Materials

giseD noitpircseD eulaV loT gnitaR







7R rotsiserpihcmlifkcihT 675 Ω %1 W8/1








51R rotsiserpihcmlifkcihT M00.1 Ω %1 W8/1









5C roticapacpihccimarecOPN Fp033 %5 V05




9C roticapacmlifretseylopdezillateM Fµ74.0 %01 V052

01C roticapacpihccitylortcelemulatnaT Fµ2.2 %02 V01



31C roticapacpihccimarecR7X Fp086 %01 V05

1L rotcudnI Hm0.1 %01 Am015

2D-1D yrevocertsaf,yarraedoiD 99VAB — V07



1Q TEFSOMlennahc-P 8N2252PT — V022

2Q TEFSOMlennahc-N 8N4252NT — V042

1U CIreifilpmalanoitarepodauQ M2092ML — —

2U CIrotarapmocdeepshgihlauD M3092ML — —

3U CIrotareneGgniRegatloVhgiH GW044VH — —


1235 Bordeaux Drive, Sunnyvale, CA 94089TEL: (408) 744-0100 • FAX: (408) 222-4895

www.supertex.com

11/12/01

©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.

hv440 application note hv440 high voltage ring...

Documents