humidity and temperature effects on pcb insertion loss · designs for enterprise cpu’s and...

DesignCon 2013

Humidity and Temperature Effects on PCB Insertion Loss

Jeff Loyer, Intel Corp. [email protected] Richard Kunze, Intel Corp. [email protected] Gary Brist, Intel Corp. [email protected]

DesignCon 2013 2 Humidity and Temperature Effects on PCB Insertion Loss

Abstract This paper represents the results of an effort to understand the net insertion loss impact of increased temperature and humidity on a large variety of PCB stackups and materials. Coupons from several different existing product PCB constructions were kept dry while identical coupons were subjected to high temperature/high relative humidity (35°C/45%RH) conditions for several weeks. Insertion loss and resistivity of those two sets were then measured at room temp and at ~68°C. From these measurements we discern separately the temperature and humidity effects on the conductors and PCB materials.

The impact of temperature and humidity have been found to be significant and must be understood to properly design a multi-gigabit system which will operate in non-ideal (hot, humid) conditions. While this topic has been covered before, our laboratory had some unique capabilities which allowed us to gather and analyze data not available previously: SET2DIL (Single-Ended TDR to Differential Insertion Loss) allows many measurements to be taken, enabling many samples and conditions; an environmental chamber was readily available; and coupons were available from many vendors representing many material and design types. While it is not a comprehensive compilation, it is more extensive than previously available.

The study focuses on the Data Center (server) environment, though results should extend to other environments with proper compensation. We also focus on stripline results for brevity since those were more straightforward.

Biographies Jeff Loyer is a Signal Integrity Lead w/ Intel Corporation and has led much of their efforts in finding solutions for PCB issues including the Fiberweave Effect, copper roughness, and measuring and controlling insertion loss. He has spoken on these topics at past DesignCon sessions.

Richard Kunze is currently a senior staff engineer and Technical Lead in the Enterprise System Engineering (ESE) organization within the Data Center Group (DCG), Intel Corporation, DuPont, Washington. His past experience in Intel includes leading the working group responsible for signal integrity of the PCIE bus interface in Intel Server systems, research and development of passive EM structures for high speed interconnects, and advancing the development of package power delivery modeling methodology and its application to package designs for Enterprise CPU’s and chipsets. Richard Kunze received his B.S. degree in physics from the University of Rochester, Rochester, NY, in 1973 and Ph.D. in physics from SUNYAB, Buffalo, NY in 1980.

Gary Brist is currently a Staff PCB and Packaging Technologist working within the Integrated Platforms Research group of Intel Corporation. He received a B.S. degree in Electrical Engineering from Montana State University (1990) and his M.S. degree in Electrical Engineering from Purdue (1992). He has authored over 25 patents and 20 publications on PCB and package design focusing on the impact of material selection and fabrication. Prior to joining Intel, Mr. Brist held various engineering and engineering management positions within the PCB fabrication industry.


Introduction Insertion loss has become a very significant factor in multi-gigabit channel performance. Transfer rates continue to increase while transistor sizes go down. This combination is very challenging to successfully transmitting information between devices – less energy available to transmit, and more absorbed by the channel. Reducing the amount of energy lost to the Printed Circuit Board (PCB) is becoming a primary factor in the viability of a design – insertion loss control can mean the difference between success and failure.

It has become routine to characterize the insertion loss of designs either immediately after they are first manufactured when they are typically extremely dry, or after being stored in typical laboratory conditions (~25°C, 40%RH). These conditions, however, are not the environment most high-speed traces will actually be operating in, and those environmental effects may be profound for multi-gigabit designs. It is therefore critical to understand exactly how the PCB insertion loss is affected by both temperature and humidity, since these will vary widely across operating environments. Not only is the PCB operating at an increased temperature, which causes an increase in conductor resistivity and dielectric loss tangent, but a PCB will also absorb moisture until it comes to equilibrium in the non-dry environment in which virtually all will operate, further affecting its insertion loss [1] [2] [3] [4] [5] [6]. This study was conducted to quantify more precisely how insertion loss will be changed under actual operating conditions. With this practical information, designers can specify, measure, and control insertion loss under known conditions and then extrapolate likely behaviors under actual operating condition.

Our laboratory had some unique capabilities in which to undertake this study – access to numerous impedance and differential insertion loss (SET2DIL) coupons from several designs and materials, an environmental chamber, SET2DIL equipment, and the ability to cross-section and measure the geometries of the coupon traces. This allowed us to measure the practical implications of the effects of temperature and humidity on PCB characteristics; the precise mechanisms are not presented, though some relevant background is given.

This paper outlines the steps taken to gain a practical understanding of the effects of temperature and humidity on insertion loss, and the relationships that were found. In short, the insertion loss and resistivity of “dry” and “wet” samples from several designs were measured at both “cool” and “hot” temperatures and the results compiled.

This study was limited to 85 differential pairs, which represent the vast majority of Intel’s multi-GHz designs. The focus is on stripline results since those were more straightforward; microstrip results are not given due to space constraints.

Study Overview Bringing “wet” samples to worst-case equilibrium

SET2DIL coupons from a variety of designs were gathered (13 total designs, 2 coupons from each design). For each design, one set of coupons (“dry”) continued to be stored in our laboratory environment (~22°C, 40%RH). The other set of coupons (“wet”) was placed in an environmental chamber (see Figure 1) set to 35°C, 45%RH. Those conditions were chosen to mimic ASHRAE Class A2 conditions [7], see Figure 2, which represent worst-case conditions for many servers.


Figure 1: Environmental Chamber, External and Internal Views

Figure 2: ASHRAE Conditions

The coupons in the chamber were given 43 days to equilibrate. During that period, their insertion loss was periodically measured to see if they had equilibrated, see Figure 3. In Figure 3, sample ID and time (not to scale) are on the X axis, while insertion loss change, relative to the first reading (dB/inch @ 4GHz) is on the Y axis. Some things to note:


The samples started at different initial conditions relative to the final equilibrium point as prior temperature/humidity testing had been performed on some of these samples, so not all the trends are in the same direction. Some started drier than the equilibrated condition and thus the trend was for insertion loss to increase over time; others had the opposite trend.

o Note: all samples had previously been subjected to a high temperature/high humidity (85°C/80%RH) environment for 10 days prior to this experiment – some had clearly absorbed a large amount of moisture from that exposure, others had not, depending on diffusivity rates.

Note especially samples 10, 11, and 14. The trend towards lower insertion loss is striking. These are clearly losing moisture and have not equilibrated, thus their results are assumed to be pessimistic. Interestingly, these are relatively low loss materials which, even in this moist condition, performed better than the higher loss materials, some of which (3, 5, 7, for instance) can be assumed to still be absorbing more moisture!

In some cases the insertion loss was varying chaotically, caused by measurement noise or local moisture gradients within the PCBs.

These are all very small samples, conditioned for 43 days – clearly the time required to infuse or diffuse moisture into/out of the inner layers of PCB’s is very, very long.


Figure 3: Insertion loss change vs. sample and time in chamber

Measuring “dry” and “wet” samples at “cool” and “hot” temperatures

After the wet coupons had been conditioned, they were sealed in individual plastic bags, and brought into a nearby laboratory, where suitable equipment was assembled (see Figure 4):

1) TDR/SET2DIL equipment to measure differential insertion loss 2) Ohmmeter with adapter to measure the resistance of the SET2DIL coupons. 3) Hot plate to control coupons’ temperature to 68°C.


Figure 4: Measurement Equipment Setup

Figure 5: Resistance Adapter and Resistance Measurement

The insertion loss and resistance of SET2DIL traces were then measured on the “dry” and “wet” coupons at “cool” (ambient laboratory) and “hot” (68°C) temperatures. This data allowed us to discern:

1) Humidity effects – comparing “dry/cool” to “wet/cool” 2) Temperature effects on dry materials: “dry/cool” vs. “dry/hot”


3) Temperature effects on wet materials: “wet/cool” vs. “wet/hot” 4) Combined temperature and humidity effects: “dry/cool” vs. “wet/hot”

Insertion Loss Humidity and Temperature Effects Findings Figure 6 compares the insertion loss (dB/inch @ 4GHz) of the various samples’ stripline traces under the four previously defined conditions: dry/cool, dry/hot, wet/cool, and wet/hot. Note that they are ordered from left to right based on insertion loss at dry/cool. Some things are particularly interesting:

The difference between the dry/cool → dry/hot and wet/cool → wet/hot is approximately the same in most cases, as will be shown explicitly later. This indicates the absorbed moisture didn’t change the insertion loss temperature coefficient greatly, which we found surprising.

Raising the temperature usually increases the loss significantly more than increasing the moisture (dry/cool → dry/hot vs. dry/cool → wet/cool).

There is a striking difference between the temperature/humidity effects on lower loss materials in this study (dry/cool loss is <0.7dB/inch @ 4GHz, ending with the sample 09, blue) and the higher loss materials (beginning with the sample 06, green). We attribute this to fundamental differences in the chemistry of the low vs. high loss materials, and believe it is something that can be taken advantage of – low loss materials will also have less susceptibility to increased temperature and humidity.

o Remember that there is reason to believe some of the low loss materials were still more moist, and some of the higher loss materials were less moist, than their final equilibrium point (Figure 3). The difference between low and high loss materials may be even greater!

There was also an anomaly in one of the cases (14, in orange).

Figure 6: Insertion Loss Effects (dB/inch) from Temperature and Humidity, Stripline

Figure 7 represents the same data as Figure 6, but from a different perspective. On the X axis is insertion loss at nominal (dry & cool), while the Y axis is now temperature coefficient in dB/inch/°C @ 4GHz for both the dry and wet samples. Some other interesting details are made clear:

The delineation between low and high loss materials is striking. Low loss materials not only begin with lower loss, but are affected by temperature much less than high loss materials.


The difference between dry and wet samples is not great. o The wet samples have more insertion loss than the dry samples when cool, but usually not

dramatically so. o Dry and wet samples usually have similar temperature coefficients.

Our industry probably needs to be aware of the effects of temperature on dielectric loss tangent. Since the effect on insertion loss due to resistivity increase as a function of temperature rise can be assumed to be constant, the difference in total insertion loss change can be attributed to an increase in the loss tangent of the various materials. This property has been studied to some degree [1] [2] [3] [4] [5] [6] [8], but much more work is called for, since there are clear differences between materials.

Figure 7: Insertion Loss Effects (dB/inch/°C) from Temperature and Humidity, Stripline

Figure 8 summarizes the net effect of combining both worst-case temperature and humidity effects. It implies two coefficients are appropriate when extrapolating nominal (cool/dry) insertion loss results to worst-case (hot/wet) conditions:

Low-loss (<0.65dB/inch @ 4GHZ) stripline: 0.0015dB/inch/°C @ 4GHz

High-loss stripline: 0.004dB/inch/°C @ 4GHz


Figure 8: Worst-Case Environmental Insertion Loss Coefficient - Stripline

There was also an anomaly in one of the cases (S14, mtl_g, in red). If these coefficients are applied for various values of “nominal” loss, they result in a net increase of approximately 20-30%. The next section, however, will discuss why this is not a valid estimation of loss due to temperature and humidity when applied to a “real-world” scenario.

“Worst Case” Assumptions Validity 35°C/45%RH as environmental chamber setting

Referring to Figure 2, there are at least two points which might be chosen to represent worst-case ASHRAE Class 2 conditions: 25°C/90%RH or 35°C/45%RH. 35°C/45%RH were chosen, since the elevated temperature would increase the diffusivity, reducing the time for the samples to equilibrate. But, there is concern that this still does not mimic the environment a PCB is likely to operate in. Referring to Figure 9, the ASHRAE conditions set limits for the data center climate and subsequently the air that will be entering the individual server’s enclosure.


Figure 9: PCB Conditions in Data Center

Once inside the server chassis, however, one can expect to find an elevated temperature due to the hot, power-consuming parts within. In this study, an internal temperature of 55°C (131°F) is assumed. Note that, although the temperature increases significantly and thus the relative humidity can be expected to decrease, the absolute humidity (i.e., “moisture content” or “humidity ratio”) must remain constant since water is neither being added nor removed from the server. Therefore, the relative humidity can be calculated for the environment inside the server as ~15%RH (see the table in Figure 9). Our assumption is that the PCB will absorb approximately the same moisture at the ASHRAE class 2 corners of 35°C/45%RH and 25°C/80%RH, or 55°C/15%RH (inside the server’s enclosure), since they have the same absolute humidity.

For a PCB which doesn’t have power-consuming parts, this assumption can be shown to be valid. For that case, the final saturated moisture content of a PCB would be expected to conform to the formula [9]:

It would take a very long time for a reasonably sized PCB to equilibrate to this condition [8] [10] [9] [11], but given that server PCB’s are expected to operate for years, it’s reasonable to assume this saturated condition would

, , , Where:

of water

Equation 1: Saturated Moisture Content


eventually be experienced. Calculating Cs/S, assuming S, the solubility of the PCB, is constant for various temperatures while keeping absolute humidity constant, shows the Cs/S value to be fairly constant, increasing slightly with temperature, but not dramatically so (Table 1, Figure 10).

Table 1: Cs/S vs. Temperature w/ constant absolute humidity

Figure 10: Cs/S vs. Temperature w/ constant absolute humidity

Table 2 shows the properties of various PCB environments and their respective relative saturated moisture content, Cs/S. Note that they are the same for the 2 Class 2 corners, and only a little higher for our assumed environment inside the server. Here RH is adjusted to 17.75% to keep absolute humidity constant. Thus, our


assumption that the ASHRAE corner is a valid representation of worst-case humidity appears valid. There is yet another aspect to be taken into account, however, as explained in the next section.

Table 2: Saturated Moisture vs. W/C Conditions

Effect of hot PCB in a humid environment

The calculations above comprehend an unpowered PCB placed in various environments represented by the top two scenarios in Figure 11; what is needed is to understand the saturated moisture content of a PCB with active components heating the PCB material environments as shown in the bottom scenario in Figure 11. Unfortunately, the authors could find no published studies giving direct insight into this condition.

Figure 11: PCB in various environments

Intuition makes us think that the PCB with hot components would be dryer, since typically objects are heated to dry them, but the problem is more complicated than that experience. Those objects are heated in a relatively dry environment, which increases the diffusivity of the object, allowing them to dry faster. But, there are scenarios where heat is used to more rapidly infuse moisture into an object [12]; it was not clear which case our scenario represented. Applying Equation 1 to this scenario, we might take our temperature T to be that of a hot PCB, ~80°C, and our absolute humidity to remain constant at 17g/m3. Going through the same calculation of saturated

Condition temp F temp C RHDensity (g/m^3) Cs/S

W/C Class 2, corner 1 95 35 45.00% 17.75 25.2W/C Class 2, corner 2 77 25 80.00% 18.39 25.3W/C inside server Class 2 131 55 17.14% 17.75 26.9


moisture content for this scenario indicated that indeed, the hot PCB would absorb more moisture than a static one, since Cs/S has increased significantly (see Table 3). This implied our findings might actually be optimistic! We needed to sanity-check our reasoning.

Table 3: Saturated Moisture of Static and Hot PCB in W/C Environment

In order to mimic and better understand the effect of “passive” vs. “active” PCBs, a rudimentary experiment was performed. The insertion loss of several coupons at ambient laboratory conditions was measured – these represent baseline results. Those PCBs were then placed on a hot plate set to 80°C in the laboratory (~22°C, 72°F, and 50%RH) for 3 days and their insertion loss was measured immediately after allowing them to cool to room temperature, to mimic moisture absorption of an “active” PCB in a laboratory environment. Those same coupons were then placed on the hot plate in an environmental chamber at worst-case conditions (55°C, 131°F, and 20%RH). To mimic moisture absorption of an “active” PCB in a worst-case environment the coupons were kept there for 4 days and again their insertion loss was measured immediately after the coupons had cooled to room temperature. The results are represented in Figure 12.

Figure 12: Static Ambient (“bl”) vs. Active PCB in Ambient (“d3”) and Worst-Case (“ec”) Conditions

While we can’t draw any absolute conclusions because of the limits of the study, there were some very telling results:

1) The PCBs clearly dried due when placed on a hot plate in the laboratory’s ambient environment. This matches our intuition – things are usually dried out by heating them.


2) The PCBs then absorbed moisture on a hot plate in the environmental chamber. Even though the relative humidity had decreased, there was more absolute humidity, and this was the predictor of relative moisture gain/loss.

3) The hot PCB’s did not demonstrate more insertion loss than the baseline, which approximately represented the condition product will be measured at. This indicates significant performance guard bands may not be needed to accommodate humidity effects (though we don’t know if our samples equilibrated).

This is not the final word – much work still remains to conduct a study which covers the effect of temperature and humidity on active PCBs comprehensively, but there is reason to believe an actual PCB won’t demonstrate an enormous infusion of moisture with corresponding degradation of performance. There is also clearly an environmental scenario which requires sophisticated modeling to properly comprehend (similar to work done in [12]). Equation 1 only applies for the static PCB situation; a heated PCB introduces a critical factor which invalidates that equation – a temperature/RH gradient surrounding the PCB (see Figure 13).

We have not yet conclusively determined how much moisture will be in an active PCB in ASHRAE class 2 (or class 3 or 4, which many servers now operate under) compared to that which we typically measure namely, dry, fresh from manufacturing. We have, however, increased our understanding of the fundamental issues at-hand dramatically which will greatly improve our methodology for later insertion loss experiments.

Figure 13: Hot PCB in Worst-Case Environment

Proposed Worst-Case Humidity, Temperature Compensation From a practical standpoint, the data from this study show that humidity and temperature are two independent phenomena that can be compensated for accordingly. For the temperature effects, Figure 7 indicates the following coefficients are appropriate to guardband for temperature effects:

0.001dB/inch/°C for low loss materials, stripline 0.003dB/inch/°C for high loss materials, stripline

Extrapolating these to account for the change from 25°C to 80°C (total change of 55°C): (55°C * 0.001dB/inch/°C)/(0.4dB/inch) ~ 15% for low loss materials, stripline (55°C * 0.003dB/inch/°C)/(0.8dB/inch) ~ 20% for high loss materials, stripline

A major caveat is that this assumes the entire trace is at the worst-case 80°C temperature, which is precluded for the most troublesome traces, i.e., those having long length. Thus, a guardband of approximately 10% seems


appropriate for temperature effects, though that begs clarification from studies on the actual temperature of traces on the various topology segments of a design. At this point, the data indicates humidity won’t be a significant factor, though that also awaits future study.

Resistance Temperature Coefficient Findings Microstrip Resistance Temperature Coefficient is not that of Copper!

We expected to find the resistance temperature coefficient to match that of copper, ~0.4%/°C [13] [14], but microstrip was markedly less, about 0.2%/°C. This was consistent across all the samples and on the two microstrip traces measured per samples (see Table 4, note the Temp Coefficients of the “top” and “bottom” traces are ~0.2%/°C for both the foreign and domestic vendors’ samples). We have not been able to explain this precisely, other than to note the base material, or the material that the microstrip traces are plated with, are not pure copper, a finding consistent with previous work [15] [16]. Note that, though Table 4 only shows the results for the control “dry” samples, the results were the same for the “wet” samples, that is, moisture had no effect on conductivity, as expected.

Table 4: Resistance Temperature Coefficients


Stripline Resistance Temperature Coefficient for is different for Foreign and Domestic Vendors!

Referring again to Table 4, note that the foreign vendors’ average temperature coefficient for the 2 stripline traces measured are ~0.35%/°C, which is fairly close to that of copper. The domestic vendors’ average temperature coefficient, however, are ~0.6%/°C, significantly higher than that of copper. It appears their “copper” has a significantly higher temperature coefficient than pure copper. Again, we have not been able to explain this, other than to suspect that the domestic stripline traces are not pure copper.

These measurements results appear credible and thus offer values that can be used in simulations with a high degree of confidence that they represent actual PCB properties.

Conductor Resistivity Findings PCB Traces Aren’t Pure Copper

While it was not the purpose of this particular study, the resistivity of our coupons was also calculated (see “Accurate Impedance and Insertion Loss Modeling of PCB Traces” of this same 2013 DesignCon), and found it was significantly different than that of pure copper (1.7ohm-cm [13] [14]), as would be expected given our temperature coefficient findings (Table 5).

Table 5: Microstrip (Left) and Stripline (Right) Conductivity

Temperature & Humidity Effects on Impedance While the details are not reported here, impedance was also measured on cool/dry and hot/wet samples and found not to change measurably.


Conclusions While we weren’t able to exactly quantify the insertion loss effects in a “real” server environment (hot PCB in warm server chassis), we did learn several very interesting, important, and relevant things:

Temperature and humidity effects can be dealt with independently – higher moisture content doesn’t significantly affect the temperature loss coefficient.

Low loss materials are affected significantly less by temperature than higher loss materials – this might be something we can leverage to control loss under non-ideal conditions.

o Low loss dielectrics not only begin with lower loss values when measured dry and cool, their loss will increase significantly less than high loss materials, increasing their value for insertion loss control.

We don’t expect PCBs in actual systems to absorb enormous amounts of moisture

Moisture takes an enormously long time to penetrate into stripline layers. While not able to precisely quantify environmental effects, we were able to bound the maximum temperature and humidity effects – the actual impact of temperature and humidity are probably significantly less than the 20-30% increase we observed for our study of static PCB’s in an ASHRAE Class 2 worst-case condition.

This study has increased our understanding of the effects of temperature and humidity enormously, and given us valuable insights into how to better study the effects for future efforts. Those will be necessary to determine a realistic guardband to properly accommodate the environmental effects on our PCBs.


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