hs3 routing guide - stanford universitycva.stanford.edu/.../2001/ee273_2001_handouts/amp_hs3.pdf ·...

I N T E R C O N N E C T A P P L I C A T I O N N O T E

Z-PACK HS3 Connector Routing

Report # 20GC004-1November 15, 2000 v1.0

Z-PACK HS3 6 Row 60 Position and 30 Position Connectors

Copyright 2000 Tyco Electronics Corporation, Harrisburg, PAAll Rights Reserved

Communications Circuits & Design Report #20GC004-1: AMP Z-PACK HS3 Connector Routing

The information contained herein and the models used in this analysis are applicable solely to the specified AMP connector as dated by thedocument. All information should be verified that it is representative of the current implementation of the connector. Alternative connectors may

be footprint-compatible, but their electrical performance may vary significantly, due to construction or material characteristics. Usage of theinformation, models, or analysis for any other connector or previous implementation is improper, and Tyco disclaims any and all liability or

potential liability with respect to such usage.

Table of ContentsItem Page #

I. INTRODUCTION......................................................................................................... 1

II. CONNECTOR OVERVIEW - Z-PACK HS3 ............................................................ 2

III. CONNECTOR FOOTPRINT ...................................................................................... 5A. Dimensions................................................................................................................ 5B. Fabrication Technology............................................................................................. 6

1. Pad Size............................................................................................................... 62. Antipad Size ........................................................................................................ 63. Non-functional Pads............................................................................................ 8

IV. ROUTING...................................................................................................................... 9A. Routing Channels ...................................................................................................... 9B. Trace Widths ............................................................................................................. 10C. Quad Track Routing .................................................................................................. 10D. Connector Footprint Breakout................................................................................... 11

1. Z-PACK HS3 6 Row Breakout ........................................................................... 112. Z-PACK HS3 10 Row Breakout ......................................................................... 12

V. ELECTRICAL PERFORMANCE.............................................................................. 13A. Antipad Adjacency.................................................................................................... 13B. Differential Pair Coupling......................................................................................... 15C. Skew & Propagation Delay....................................................................................... 15

VI. SUMMARY.................................................................................................................... 19

VII. RELATED DOCUMENTS .......................................................................................... 21

VIII. CONTACT INFORMATION ...................................................................................... 21A. Tyco Electronics........................................................................................................ 21B. Communications Circuits & Design ......................................................................... 22


tyco / ElectronicsCommunications Circuits & Design

PAGE 1 Nov. 15, 2000

Z-PACK HS3 Connector Routing

I. Introduction

As engineers design systems that attempt to push serial speeds across backplaneenvironments in the gigabit per second range, the selection of the systems electricalconnector becomes more significant. Electrical, mechanical, and manufacturing aspectsof the connector must be considered simultaneously. At the board level these aspectscombine with common board design practices to influence the design of the connector-to-board interface and how the board itself will be routed. The manner in which theconnector is designed into the system can significantly impact the systems intendedperformance.

Tyco Electronics has been actively researching these areas in an effort to help customersuse the Z-PACK HS3 connector in gigabit serial systems. The combination ofinterconnect research and intimate knowledge of the connector is presented to provideinsight into the capability of an Z-PACK HS3-based system design. Furthermore, thisdocument provides specific design recommendations that will address layout, electricalperformance, and manufacturability tradeoffs of the connector at the board level.

Figure 1: AMP Z-PACK HS3 connector operating in a 10 Gbps serial systemenvironment



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II. Connector Overview - Z-PACK HS3

Figure 2: Z-PACK HS3 10 Row (100 position) and 6 Row (60 position) Connectors

The AMP Z-PACK HS3 connector shown in Figure 2 has been developed for high-speedsignal applications and is targeted for systems with high signal density or noise-sensitivesignals. These applications work well with the Z-PACK HS3 due to ground shields thatare placed between pin columns. The ground shields nearly eliminate noise betweenconnector columns, allowing the use of higher signal densities while maintaining signalimpedances of 50 Ω single-ended and 100 Ω differential.

Two different pin count versions of the Z-PACK HS3 connector are available for both 10row and 6 row connectors. These two versions are a 10 column version (100 or 60position) and a 5 column version (50 or 30 position). The 5 column version is availablewith an optional multi-purpose alignment region for coding keys and a guide pin. Also,the Z-PACK HS3 is available in right-, center, and left-handed versions. The differencebetween these versions is the orientation of the guide pin and coding key regions. Allmodules use press-fit pin technology and employ dual beam receptacles.

Part numbers for each connector module are provided in Figure 3 and Figure 4. Furtherproduct information can be found in AMP catalog #1307515 and the Z-PACK HS3specific subset, catalog #1307397.



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Figure 3: 10 Row Product Family

120795 120793 120791 120790 120792 120794



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Figure 4: 6 Row Product Family

120789 120787 120786 120788



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III. Connector Footprint

A. DimensionsFull mechanical dimensioning and tolerances are available for all versions of the Z-PACK HS3 connector. See section VII for details. The dimensions critical to routing ofthe Z-PACK HS3 connector are related to the hole pattern, or footprint, of theconnector as shown in Figure 5. All dimensions within the footprint are identical for boththe backplane (header) and daughter card (receptacle) components. Both signal andground pins have identical hole sizes. Figure 5 and Table 1 below are provided toquickly identify critical hole dimensions for the circuit board. Manufacturing dependantdimensions are discussed later in this document.

Figure 5: Footprint Dimensions (10 row 10 column module)

Hole Dimension Diametermm (in.)

Drill Hole Size 0.70 ± 0.025(0.0276 ± 0.001)

Finished Hole Size 0.60 ± 0.05(0.024 ± 0.002)

Copper Thickness of Hole 0.0375 ± 0.0125(0.0015 ± 0.0005)

Table 1: Connector Hole Dimensions



PAGE 6 Nov. 15, 2000

B. Fabrication TechnologyOther important dimensions for board layout are determined by the capabilities of thecircuit board fabricator. Current high-tech PCB industry fabrication technology (i.e.capability) requires minimum pad sizes ranging from D+10 mils through D+18 mils,where D is the diameter of the drilled hole size (1 mil is 0.0254 mm (0.001")). For theZ-PACK HS3 connector this results in minimum pad sizes ranging from 0.96 mm(0.038") to 1.16 mm (0.046"). These resultant pads are the minimum pad sizes requiredto maintain 0.05 mm (0.002") of annular ring for a given PCB manufacturers capability.Annular ring is an industry standard measure of the clearance between the pad edge andworst case drill edge after manufacturing. Because the Z-PACK HS3 is typically used inhigh speed or dense applications where routing issues are most significant, all paddimensions in this document will assume a D+12 mil pad size, or 1.02 mm (0.040") pad,unless otherwise specified. The pad diameter may be optimized for specific projectneeds, and should be evaluated on a project and vendor basis. Designing with a D+10mil technology PCB could mean reduced yields or breakout, potentially adding cost tothe PCB or violating industry specification compliance.

Note: A minimum pad to trace clearance of 0.13 mm (0.005") will also be assumed forcalculating routing dimensions.

1. Pad Size

Based upon the D+12 mil fabrication technology assumption, a 1.02 mm (0.040")diameter pad should be used with all Z-PACK HS3 connector pins. For very high-techPCBs (D+10 mil) the pad is 0.97 mm (0.038"). In some cases the reducedmanufacturability of a D+10 mil technology PCB is required to reduce pad sizes,although potentially reduced yields or breakout may add cost to the PCB. Wherepossible the largest appropriate pad size should be used to provide the PCB manufacturerwith the greatest flexibility, thereby reducing overall system costs.

Thermal reliefs are not required on ground or power pins, because the Z-PACK HS3connector uses a press-fit technology. A direct connection to reference and power planeswill offer the lowest inductance connection to the circuit board.

2. Antipad Size

Antipads, or plane clearances (Figure 6), are required to separate signal holes fromreference voltages to avoid shorting. Choosing the proper size of these clearances iscritical in determining several other design parameters: signal integrity, EMI, voltagebreakdown, and manufacturability. The antipad for the Z-PACK HS3 is limited to aminimum of 1.27 mm (0.050") due to manufacturability and a maximum of 1.60 mm(0.063") by signal integrity. A minimum antipad should be at least 0.25 mm (0.010") indiameter larger than it associated pad.



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Determining the proper antipad size within the 1.27 mm (0.050") to 1.60 mm (0.063")range depends upon system design goals.

Antipad sizes are minimized:• To reduce noise by closely shielding adjacent pins with reference planes• To reduce EMI by minimizing aperture sizes in reference planes• To maintain a strong reference to ground for single-ended signals and ground

referenced differential signals

Antipad sizes are maximized:• To maximize voltage breakdown spacing between the pin and the reference plane• To increase manufacturability by reducing the chance of shorting.• To reduce reflections in a high speed gigabit serial system by reducing the capacitive

effect of the plated through-hole.

A comparison of the system performance of the1.60 mm (0.063") antipad to a smaller 1.32 mm(0.052") antipad, shown in Figure 7, demonstrateshow increasing the antipad size can increaseoverall system performance due to minimizedsystem reflections. The diagrams in Figure 7show an 18" point-to-point link with two AMP Z-PACK HS3 connectors operating at 5 Gbps, asdescribed in the DesignCon 2000 Presentationreferenced in section VII.

Figure 6: Trace, Via, and Antipad in Plane

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1.32 mm (0.052")Antipad diameter

166 mV Eye Opening25 % Jitter

1.60 mm (0.063")Antipad diameter

302 mV Eye Opening19 % Jitter

Figure 7: Antipad Performance Comparison

3. Non-functional PadsThe removal of non-functional internal pads will improve signal integrity andmanufacturability of the PCB. However, some assembly facilities prefer that pads areleft in order to maintain hole integrity through various soldering processes. For electricalreasons it is recommended to remove unused pads on internal layers.

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IV. Routing

Because the Z-PACK HS3 connector can be used for both single-ended and differentialsignals, the routing of both signal types will be examined. Whether routing into orthrough the Z-PACK HS3 pinfield, the general guidelines are the same.

A. Routing Channels

Between each column of signal pins are two routing channels for traces. When routingedge-coupled differential signals through or into the pinfield, traces should besymmetrical around ground pins, not signal pins. Both recommended and non-recommended routing styles are shown in Figure 8. When routing differential signalsaround the ground pins, the traces should be kept as close to the ground pins asmanufacturing will allow, in order to reduce noise if differential spacing permits. Single-ended and broadside-coupled differential signals use the same routing channels as edge-coupled differential signals but should be centered between signal and ground pins tomaximize trace-to-trace isolation and reduce trace crosstalk. The Z-PACK HS3connector also has vertical routing channels that can be utilized in the same fashion as thehorizontal channels.

RecommendedDifferential Routing

Non-RecommendedDifferential Routing

Figure 8: Routing Methods



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B. Trace Widths

The narrowest area of the connector footprint is the diagonal routing between a signal pinand a ground pin. This diagonal region is labeled as Bin Figure 9 and is applicable to both the header andreceptacle parts. At location B, there is a 0.56 mm(0.022") space between 1.02 mm (0.040") pads. Thisallows for a maximum of a 0.30 mm (0.012") wide trace(A) to be routed in the diagonal region, assuming that atrace to pad spacing of 0.13 mm (0.005") is required. Ifthe trace is routed off-angle (not 45o), then an additional0.0254 mm (.001") in trace width or spacing can begained beyond 0.30 mm (0.012").

Figure 9: Footprint Dimensions

C. Quad Track Routing

Typically two traces are routed between signal columns in the Z-PACK HS3 connectordue to the 0.56 mm (0.022") dimension between a signal and ground pin in the footprint.If manufacturing constraints (either D+12 mil or pad-to-trace spacing) are relaxed by.076 mm (.003") then four narrow traces can be routed between signal columns wherepreviously two traces fit. Antipad sizes must also be minimized to maintain groundcoverage for the additional traces. Quad track routing (4 traces or 2 differential pairbetween signal columns) should only be used for low speed, high density designs that canaccommodate the additional trace crosstalk and attenuation. System level noise analysisshould be performed when the Z-PACK HS3 connector is used in this fashion todetermine the performance effects. Additionally, this would reduce the number of layersrequired to route out of the connector by half. Both routing methods are shown below inFigure 10.

Dual Track Routing

Quad Track Routing

Figure 10: Example of Dual and Quad Track Routing of the Z-PACK HS3 Footprint

GND

Signal Signal

Signal Signal



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D. Connector Footprint Breakout

1. Z-PACK HS3 6 Row BreakoutIf routing out of both sides of the connector is possible, then only 1 signal layer isrequired for the 6 row Z-PACK HS3 connector breakout on a motherboard (orbackplane). Otherwise, if only one routing direction is used, the daughter card breakoutexample can be used which requires a minimum of 3 signal layers (with some freeremaining channels) to route out of a fully populated 6 row Z-PACK HS3 connector. Forconfigurations where there are remaining routing channels on a layer, only half of the lastrouting layer is needed by the breakout pattern. Examples of typical breakout patterns forthe Z-PACK HS3 6 row connector pinfields are shown in Figure 11 Figure 13. SectionVII lists available CAD tool-specific layout examples for the Z-PACK HS3 connector.

Backplane Daughtercard

Figure 11: Backplane Single-EndedBreakout Pattern (1 Layer)

Figure 12: Backplane DifferentialBreakout Pattern (1 Layer) Figure 13: Daughtercard Differential

Breakout Pattern (3 Layers)

Circuits & Design Report #20GC004-1: AMP Z-PACK HS3 Connector Routing,


PAGE 12 Nov. 15, 2000

2. Z-PACK HS3 10 Row BreakoutOn a daughter card, the 10 row version of the Z-PACK HS3 requires 5 signal layers(also with some free remaining channels), while the motherboard (or backplane) requiresa minimum of 2 signal layers to route out. Examples of typical breakout patterns for theZ-PACK HS3 10 row connector pinfields are shown in Figure 14 Figure 16.

Backplane Daughtercard

Figure 14 : Backplane Single-EndedBreakout Pattern (2 Layers)

Figure 15: Backplane DifferentialBreakout Pattern (2 Layers) Figure 16: Daughtercard Differential

Breakout Pattern (5 Layers)

Circuits & Design Report #20GC004-1: AMP Z-PACK HS3 Connector Routing


PAGE 13 Nov. 15, 2000

V. Electrical Performance

Electrical performance reports which contain validated crosstalk data for the connector,are available for the AMP Z-PACK HS3 connector. Additional test and simulation datashowing throughput capabilities of the Z-PACK HS3 connector is also available. Bothtypes of reports are available at www.amp.com/simulation. The electrical performanceimpact of routing traces through the Z-PACK HS3 footprint is covered in the sectionsbelow.

A. Antipad Adjacency

In some cases where wide traces are routed through the connector footprint the referenceplane clearance (antipad) will partially overlap areas of the routed trace. However, theimpact on trace impedance and noise generation is minor due to the short electrical lengthof the overlap. Traces routed in the Z-PACK HS3 footprint maintain full reference planecoverage except where routing over the antipad is required. Figure 17 shows the effectsof routing wide traces over large antipads in the Z-PACK HS3 footprint. The frequencyresponse of a standard stripline trace not routed through pinfields is compared with anidentical trace routed through 12 footprints. The difference between the two responsecurves is negligible.

• 457 mm (18") System• Z-PACK HS3 Connectors• 0.30 mm (0.012") Traces

Figure 17: Measured Performance of Routing Over AntipadsThis routing effect as viewed in the time domain manifests as an impedancediscontinuity. Figure 18 and Figure 19 show that the impedance variation due to tracejogging and routing over antipads is only 3 Ω as measured by an unfiltered TDR. The

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http://www.amp.com/simulation



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figures show that the trace impedance variation due to manufacturing is comparable tothe antipad discontinuity. Figure 18 shows the 0.30 mm (0.012") wide trace routed for adistance of 305 mm (12") across a two-daughtercard system. Figure 19 represents thesame trace routed for 305 mm (12") through 12 Z-PACK HS3 pinfields. Both figures arecentered around a 50 Ω impedance offset.

Figure 18: Routing Impedance (Trace Only)

Figure 19: Routing Impedance (Through Pinfields)

12" Trace Through Pinfields

12" Trace



PAGE 15 Nov. 15, 2000

As a result, reducing the overlap of the trace and antipad minimizes discontinuities on thesignal. When connecting traces to signal pins, the entire trace must route over the antipadfor a short distance. To minimize the antipad discontinuity entire traces should be routedover antipads for as short a distance as possible. Additionally, entire traces should notcross other antipads or ground clearances, but maintain a continuous adjacent-layerground path in the Z-PACK HS3 footprint.

B. Differential Pair Coupling

For edge-coupled differential signals, trace jogging is necessary around the ground pinsof the connector footprint. These differential signals which must separate, will stillmaintain a consistent differential impedance in that region of the connector. Figure 20and Figure 22 show TDR plots of the differential impedance of both loosely spaced (<5%trace-to-trace coupling) and closely spaced (>20% trace-to-trace coupling) differentialpairs routed across 305 mm (12") of backplane. Figure 21 and Figure 23 show the sametwo trace geometries routed through 12 Z-PACK HS3 pinfields. The differentialimpedance scale of all four figures is 80mρ / division (approximately 8 Ω / division).The four figures show that the impedance varies only ~ 4 Ω from the nominal100 Ω (well within standard board manufacturing constraints of 10%) as measured by anunfiltered TDR. By designing the differential pairs that are primarily coupled to ground,Z-PACK HS3 footprint differential routing is able to closely maintain a100 Ω differential trace impedance.

C. Skew & Propagation Delay

As a right-angle connector, each row of the Z-PACK HS3 has a different electrical pathlength. Typical values are provided below in the single line model data of AMPconnectors. Figure 24 and Figure 25 are current single line model data sheets for theAMP Z-PACK HS3 connector. All electrical and mechanical information should beverified that it is current and applicable (www.amp.com/simulation). Although it ispossible to assign differential signals in-row to reduce skew, this is not recommendedbecause the noise-shielding effectiveness of the in-column ground blades is greatlyreduced.




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Figure 20: Loosely Coupled Signal Pair

Figure 21: Loosely Coupled Signal PairRouted Through Pinfields

Figure 22: Tightly Coupled Signal Pair

Figure 23: Tightly Coupled Signal PairRouted Through Pinfields



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Figure 24: AMP Z-PACK HS3 6 Row Single Line Data



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Figure 25: AMP Z-PACK HS3 10 Row Single Line Data



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VI. SummaryTable 2 is provided to summarize the recommendations presented in this document.

Item ValueConnector Dimensions:Z-PACK HS3 Signal Pin Column Pitch 2.5 mm (0.098")

Z-PACK HS3 Signal Pin Row Pitch 1.5 mm & 2.0 mm(0.059") & (0.079")

Number of Connector Rows 6 and 10Number of Connector Columns 5 and 10Footprint Dimensions:Suggested Pad Size ≥1.02 mm (0.040")

Suggested Antipad Size Range 1.27 mm 1.60 mm(0.050") (0.063")

Maximum Trace Width (Plug & Receptacle) 0.30 mm (0.012")Nominal Finished Hole Size 0.60 mm (0.024")Nominal Drill Hole Size 0.70 mm (0.0276")

Copper Thickness in Hole 0.0375 mm ± 0.0125 mm(0.0015" ± 0.0005")

Layer Requirements:Layers Required to Fully Route out of a 6 Row Z-PACK HS3 on a Backplane 1Layers Required to Fully Route out of a 10 Row Z-PACK HS3 on a Backplane 2Layers Required to Fully Route out of a 6 Row Z-PACK HS3 on a Daughtercard 3Layers Required to Fully Route out of a 10 Row Z-PACK HS3 on a Daughtercard 5Pad Size Required to Quad Track Route 0.005"/ 0.005" Traces/Spaces 0.94 mm (0.037")Electrical Propagation Data:6 Row Z-PACK HS3 Typical Electrical Propagation of A Row Pin 81 ps6 Row Z-PACK HS3 Typical Electrical Propagation of B Row Pin 97 ps6 Row Z-PACK HS3 Typical Electrical Propagation of C Row Pin 112 ps6 Row Z-PACK HS3 Typical Electrical Propagation of D Row Pin 129 ps6 Row Z-PACK HS3 Typical Electrical Propagation of E Row Pin 144 ps6 Row Z-PACK HS3 Typical Electrical Propagation of F Row Pin 163 ps10 Row Z-PACK HS3 Typical Electrical Propagation of A Row Pin 81 ps10 Row Z-PACK HS3 Typical Electrical Propagation of B Row Pin 96 ps10 Row Z-PACK HS3 Typical Electrical Propagation of C Row Pin 112 ps10 Row Z-PACK HS3 Typical Electrical Propagation of D Row Pin 127 ps10 Row Z-PACK HS3 Typical Electrical Propagation of E Row Pin 143 ps10 Row Z-PACK HS3 Typical Electrical Propagation of F Row Pin 160 ps10 Row Z-PACK HS3 Typical Electrical Propagation of G Row Pin 175 ps10 Row Z-PACK HS3 Typical Electrical Propagation of H Row Pin 192 ps10 Row Z-PACK HS3 Typical Electrical Propagation of J Row Pin 208 ps10 Row Z-PACK HS3 Typical Electrical Propagation of K Row Pin 227 ps

Table 2: Data Summary



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Table 3 through Table 6 provide representative padstack recommendations based upontypical system goals. The padstack recommendations are only suggested values, that mayor may not be applicable to any given system and should be evaluated before use.

Item ValueSuggested Pad Size 1.02 mm (0.040")Suggested Antipad Size 1.60 mm (0.063")

Table 3: High Speed Padstack Recommendations


Table 4: Low Noise Padstack Recommendations


Table 5: Nominal Padstack Recommendations


Table 6: High Volume Production (Conservative) Padstack Recommendations



PAGE 21 Nov. 15, 2000

VII. Related Documents

• A representative Cadence Allegro and Mentor Falcon part model is available basedupon the design parameters specified in this reference document.

• Electrical models of the Z-PACK HS3 connector are available atwww.amp.com/simulation.

• Reference designs and conference papers are available at www.amp.com/simulation.• Mechanical detailed drawings of the AMP Z-PACK HS3 connector are available at

www.amp.com.

VIII. Contact Information

A. Tyco ElectronicsTyco Electronics Corporation is the world's leader in electrical, electronic and fiber-opticconnectors and interconnection systems. Its facilities are located in over 50 countriesserving customers in the automotive, computer, communications, consumer electronics,industrial and power industries. Tyco Electronics, headquartered in Harrisburg,Pennsylvania, USA, is the largest passive electronics components supplier in the world,providing advanced technology products from its AMP, Elcon, Elo Touchsystems, HTS,M/A-COM, Madison Cable, OEG, Potter & Brumfield, Raychem, Schrack and Simelbrands.

AMP, Z-PACK and TYCO are trademarks. Other products, logos, and Company namesmentioned herein may be trademarks of their respective owners.

For more information about TYCO Products, call us today or visit us on the web.

Product Information Center 800-522-6752717-986-7777

Internet http://www.tycoelectronics.com



http://www.amp.com/

http://www.amp.com/



PAGE 22 Nov. 15, 2000

B. Communications Circuits & Design

Communications Circuits & Design (CC&D) is part of the Global CommunicationsBusiness Unit of Tyco Electronics, which focuses on the rapidly growing telecom andnetworking markets. CC&D offers the industry interconnection expertise from conceptto production, and helps customers to validate their designs at the concept stage. CC&Dis providing a leadership role for the industry in the area of signal integrity by workingwith Tyco Electronics customers, industry standard working groups, and semiconductorvendors.

Offering interconnection expertise from concept to production, CC&D can help validateyour design and package it for manufacturing. At the front end, our end-to-end computersimulation and analysis of your system will evaluate the most critical parameters of yourdesign. Our advanced analysis and modeling techniques can help determine the optimaldevice drivers, board design and stackup, and board layout for your design. Byidentifying problems such as reflections, ground bounce, crosstalk, jitter, propagationdelay, and timing, CC&D can help you reduce costs and verify the performance of yourdesign.

CC&D has been instrumental in developing and verifying many of the worlds mostpopular bus standards. Here is a brief sampling.

CompactPCI: Our recommendations helped make CompactPCI the rock-solid,industrial-strength bus that combines high performance with flexibility.

CompactPCI Hot Swap: We provided the critical simulations that allowedmission-critical hot swapping to be a reality in CompactPCI.

CT: CC&D performed the simulations for the H.110 computer telephonyextensions to CompactPCI.

PXI: Our analysis of PXI resulted in several improvements for increased signalintegrity.

CPCI/CT/ATM Backplane: This is a CC&D-designed system that combinesCompactPCI, CT, and Cellbus into a high-performance system that meets thegrowing needs of communications convergence.

To find out more about our design services, contact us today.

Communications Circuits & Design 717-986-7824Internet http://www.amp.com/simulationElectrical simulation [email protected] models [email protected]


mailto:[email protected]

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