hs-2420rh_fast sample and hol

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1

®

FN3554.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2003. All Rights ReservedAll other trademarks mentioned are the proper ty of their respective owners.

HS-2420RH

Radiation Hardened Fast Sample and Hold

The HS-2420RH is a radiation hardened monolithic circuit

consisting of a high performance operational amplifier withits output in series with an ultra-low leakage analog switchand MOSFET input unity gain amplifier.

With an external hold capacitor connected to the switch output,a versatile, high performance sample-and-hold or track-and-hold circuit is formed. When the switch is closed, the devicebehaves as an operation amplifier, and any of the standard opamp feedback networks may be connected around the deviceto control gain, frequency response, etc. When the switch isopened the output will remain at its last level.

Performance as a sample-and-hold compares very favorablywith other monolithic, hybrid, modular, and discrete circuits.

Accuracy to better than 0.01% is achievable over thetemperature range. Fast acquisition is coupled with superiordroop characteristics, even at high temperatures. High slewrate, wide bandwidth, and low acquisition time produceexcellent dynamic characteristics. The ability to operate atgains greater than 1 frequently eliminates the need forexternal scaling amplifiers.

The device may also be used as a versatile operationalamplifier with a gated output for applications such as analogswitches, peak holding circuits, etc.

Specifications for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

Detailed Electrical Specifications for these devices are

contained in SMD 5962-95669. A “hot-link” is provided

on our website for downloading.

Pinout 14 LEAD METAL-SEALED SIDE-BRAZED CERAMIC DIP

MIL-STD-1835, CDIP2-T14

TOP VIEW

Features

• Electrically Screened to SMD # 5962-95669

• QML Qualified per MIL-PRF-38535 Requirements• Maximum Acquisition Time

- 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs- 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . . . . . . 6µs

• Maximum Drift Current . . . . . . . . . . . . . . . . . . . . . . . 10nA(Maximum Over Temperature)

• TTL Compatible Control Input

• Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . ≥ 80dB

• Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)

• No Latch-Up

Applications

• Data Acquisition Systems

• D to A Deglitcher

• Auto Zero Systems

• Peak Detector

• Gated Op Amp

Functional Diagram

IN-

IN+

OFFSET ADJUST

OFFSET ADJUST

V-

NC

OUTPUT

SAMPLE/HOLD

GND

NC

HOLD CAPACITOR

NC

V+

NC

CONTROL1

2

3

4

5

6

7

14

13

12

11

10

9

8

Ordering Information

ORDERING NUMBER

INTERNAL

MKT. NUMBER

TEMP. RANGE

(oC)

5962R9566901VCC HS1B-2420RH-Q -55 to 125

-+

OFFSETADJUST

V+

-+

7OUTPUT

11

HOLDCAPACITOR

- INPUT

+ INPUT

SAMPLE/

HOLDCONTROL

V-GND

14

2

1

HS-2420RH

3 4 5

513

Data Sheet February 2003



2

Test Circuits

FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION)

NOTE: Compute Hold Mode Feedthrough Attenuation from theFormula:

Where VOUT HOLD = Peak-Peak Value of Output Sinewave duringthe Hold Mode.

FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION

NOTE: GBWP is the Frequency of VINPUT at which:

FIGURE 3. GAIN BANDWIDTH PRODUCT

DUT

-

+

A

S/H-VCC+VCC

CH =1000pF50Ω

2

2 1

1

S2

S12

1S6

12

S7

S71

2

50Ω

VAC

AOUT

EOUT

50Ω

1MΩ

4

3

2

1S8

3

2S3 1

+VCC

GND

50pF 2kΩ

1

S5

OPEN 3

2S4

1

100kΩ

VDC

10kΩ

ILOAD

NULLAMP

X1X-1

BUFFER

100kΩ

ALL RESISTORS = ±1%ALL CAPACITORS = ±10%

+-

+-

CH =

VOUT

50pF2kΩ

+15V -15V

1000pF

DUT

VIN

OUT

A0

ENIN2

IN1

IN3

IN4

IN5

IN6

IN7

IN8

A2

A1

SINEWAVEINPUT

SAMPLE/HOLDCONTROL INPUT

+5V

+-

FeedthroughAttenuation 20 logVOUT HOLDVIN HOLD

--------------------------------

=

CH =

VOUT

50pF2kΩ

+15V -15V

1000pF

DUT

S/H50Ω

+-

20 logVOU T

VINPUT---------------------

3d B – =

HS-2420RH



3

FIGURE 4. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER)

FIGURE 5.

Test Circuits (Continued)

INCREMENT t2BY 50ns

(50ns LONGER DELAY)

SEND SAMPLECOMMAND

SET t2 TO 7µs

INITIALLY

DIGITIZE V1AT t1 (≈10µs)

DIGITIZE V2AT t2

DECREMENTt2 BY 50ns

CALCULATE V1

- V2IS ∆V ≥ 0.01%?

NO

YES

COURSE tACQ

MEASUREMENT LOOP

DECREMENTt2 BY 50ns

DIGITIZE V1AT t1 (≈10µs)

DIGITIZE V2AT t2

CALCULATE V1 - V2IS ∆V ≥ 0.01%?

RECORDtACQ

NOYES

FINE tACQ

MEASUREMENT LOOP

NOTE: See Test Diagram, Timing Diagram

COMPUTERCONTROLLER

V1 DIGITIZER

V2 DIGITIZER

V1

V2

t2VARIABLE

DELAY

t2 DELAY

CONTROL

t1≈10µs

1000pF

2kΩ

t1

-+-

+

S/HCONTROL

HS-2420RH

+10V

0V

0V

-10V

OR

50pF

DELAY

HS-2420RH



4

Timing Waveforms

FIGURE 6. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE)

FIGURE 7A. FIGURE 7B.

FIGURE 7. OVERSHOOT, RISE AND FALL TIME WAVEFORMS

FIGURE 8A. FIGURE 8B.

FIGURE 8. SLEW RATE WAVEFORMS

10V

2V0V

0V

VIN(POS tACQ CASE)

S/H CONTROL

DUT OUTPUT(POS tACQ CASE) 0V

10V

t1 ≈ 10µs(t1 DIGITIZER COMMAND)

(t2 DIGITIZER COMMAND)

t1

t2

t2

0.01% OR 0.1%ENVELOPE

+V

0V -V

0V

INPUT

+OS, tR -OS, tF

VPEAK

90%

10% 90%

10%

VPEAK

VFINAL

tR tF

VFINAL

-V

+V

-V

+V

+SL -SL

INPUT

+V +V

75%

25%

25%

75%

-V -V

∆t ∆t

HS-2420RH



5

Typical Performance Curves VSUPPLY = ±15VDC, TA = 25oC, CH = 1000pF, Unless Otherwise Specified

FIGURE 9. TYPICAL SAMPLE AND HOLD PERFORMANCE

vs HOLDING CAPACITOR

FIGURE 10. BROADBAND NOISE CHARACTERISTICS

FIGURE 11. DRIFT CURRENT vs TEMPERATURE FIGURE 12. OPEN LOOP FREQUENCY RESPONSE

FIGURE 13. HOLD MODE FEEDTHROUGH ATTENUATION

CH = 1000pF

FIGURE 14. OPEN LOOP PHASE RESPONSE

1000

100

10

1.0

0.1

0.0110pF 100pF 1000pF 0.01mF 0.1mF 1.0mF

DRIFT DURING HOLD AT25oC mV/s

MIN SAMPLE TIMEFOR 0.1% ACCURACY

10V SWINGS (ms)

UNITY GAIN PHASEMARGIN (DEG)

HOLD STEPOFFSET ERROR(mV)

SLEW RATE/CHARGE RATE

V/(ms)

UNITY GAINBANDWIDTH

(MHz)

CH VALUE

1000

100

10

1

m V R

M S

10 100 1K 10K 100K 1M

BANDWIDTH

LOWER 3dB FREQUENCY = 10Hz

OUTPUT NOISE“HOLD” MODE

EQUIV. INPUT NOISE“SAMPLE” MODE - 100KSOURCE RESISTANCE

EQUIV. INPUT NOISE“SAMPLE” MODE - 0KSOURCE RESISTANCE

1000

100

10

1

I D ( p A )

-50 -25 0 25 50 75 100 125

TEMPERATURE (oC)

100

80

60

40

20

0

-20 O P E N L O O P V O L T A G E G A I N ( d B )

10 100 1K 10K 100K 1M 10M 100M

FREQUENCY (Hz)

CH = 100pF

CH = 1000pF

CH = 1.0µF

CH = 0.1µF

CH = 0.01µF

-30

-40

-50

-60

-70

-80

-90

A T T E N U A T I O N ( d B )

100 1K 10K 100K 1M 10M

±10V SINUSOIDAL INPUT FREQUENCY (Hz)

0

20

40

60

80

100

120

140

160

180

200

220

240 O P E N L O O P P H A S E A N G L E ( D E G R E E S )

10 100 1K 10K 100K 1M 10M 100M

FREQUENCY (Hz)

CH = 1.0µF

CH = 0.1µF

CH =1000pF

CH ≤ 100pF

CH = 0.01µF

HS-2420RH



6

Burn-In Circuit HS-2420RH CERDIP

NOTES:

R1 = 100kΩ ±5% (per socket)C1 = C2 = 0.1µF (one per row) or 0.01µF (one per socket)D1 = D2 = 1N4002 or equivalent (per board)

Irradiation Circuit

NOTES:

V1 = +15VV2 = -15VR = 100kΩ

1

2

3

4

5

6

7

14

13

12

11

10

9

8

C2 D2

D1 C1

-15V

+15V

R1

-IN

+IN

OFFADJ

-V

NC

OUT

OFFADJ

S/HCTL

GND

NC

HOLDCAP

NC

+V

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

V1

R

V2

GND GND

FIGURE 15. HOLD STEP vs INPUT VOLTAGE FIGURE 16. BASIC SAMPLE-AND-HOLD (TOP VIEW)

FIGURE 17. INVERTING CONFIGURATION FIGURE 18. NONINVERTING CONFIGURATION

+10

+5

-5

-10

-15

-20

-25

-30

-35

-10 -5 +5 +10

DC INPUT VOLTAGE (V)

HOLD STEP VOLTAGE (V)

CH = 0.1µF

CH = 10,000pF

CH = 1000pF

CH = 100pF

+IN V-

100kΩOFFSET TRIM

(±25mV RANGE)

OUT-IN

V+CH

S/HCONTROL

-+ -

+

HS-2420RH

-IN

+IN

OUT

S/HCONTROL

INPUTRI

OUTPUT

0.002RF

RF

S/H CONTROLINPUT

HS-2420RH

GAIN ~-RF

RI

+IN

-IN

OUT

S/HCONTROL

INPUT

RI

OUTPUT

0.002RI

RF

S/H CONTROLINPUT

HS-2420RH

GAIN ~ I +-RF

RI

HS-2420RH



7

HS-2420RH

Offset and Gain Adjustment

Offset Adjustment

The offset voltage of the HS-2420RH may be adjusted usinga 100kΩ trim pot, as shown in Figure 15. The recommendedadjustment procedure is:

1. Apply 0V to the sample-and-hold input, and a square

wave to the S/H control.2. Adjust the trim pot for 0V output in the hold mode.

Gain Adjustment

The linear variation in pedestal voltage with sample-and-holdinput voltage causes a -0.06% gain error (CH = 1000pF). Insome applications (D/A deglitcher, A/D converter) the gainerror can be adjusted elsewhere in the system, while in otherapplications it must be adjusted at the sample-and-hold. Thetwo circuits shown below demonstrate how to adjust gainerror at the sample-and-hold.

The recommended procedure for adjusting gain error is:

1. Perform offset adjustment.2. Apply the nominal input voltage that should produce a

+10V output.

3. Adjust the trim pot for +10V output in the hold mode.

4. Apply the nominal input voltage that should produce a -10Voutput.

5. Measure the output hold voltage (V-10 NOMINAL). Adjustthe trim pot for an output hold voltage of:

V-10 NOMINAL( ) 10V – ( )+

2------------------------------------------------------------------------



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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Die Characteristics

DIE DIMENSIONS:

97 mils x 61 mils x 19 mils

METALLIZATION:

Type: AlThickness: 16kÅ ± 2kÅ

GLASSIVATION:

Type: SiloxThickness: 14kÅ ± 2kÅ

WORST CASE CURRENT DENSITY:

2.0 x 105A/cm2

TRANSISTOR COUNT:

78

PROCESS:

Bipolar-Di

Metallization Mask Layout HS-2420RH

HS-2420RH

hs-2420rh_fast sample and hol

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