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How to turn an ADC into a DAC:A 110dB THD, 18mW DAC using

sampling of the output and feedback to reduce distortion

Axel Thomsen, Design ManagerSilicon Laboratories Inc. Austin, TX

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Why this talk?A good example how architectural design avoids hard circuit design

A good illustration of the power of feedback

An example of understanding new challenges in a new architecture

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This work was done byAxel Thomsen, Dan B. Kasha, Lei Wang and Wai L. Lee,atIndustrial Products Division, Cirrus Logic Inc. Austin, TX

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OutlineIntroduction

Traditional Architecture

Feedback ArchitectureIntegrator 1Output Sampling Issues Loop StabilityOther Circuits

Experimental Results

Conclusion

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Introduction: Motivation and Goalschannel test of a highly integrated data-acquisition channel

low distortion, low power: 110dB THD, 18mW, 114dB SNR in 400Hzsinusoidal signal sourceminimal number of external componentsnoise-shaped single bit bitstream provided at 256kHz, digitally interpolated to 1024kHzjitter tolerance

minimize number of critical building blocks with architectural solution to reduce circuit design complexityleverage knowledge of designing low distortion ADCs

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Traditional Architecture

all blocks and interfaces must exceed noise and distortion requirements !

DAC + filter reconstructionand Qnoise filter buffer

VoutD*Vref

switched capacitor continuous time

Vout

time

distortion from signal dependent settling waveforms

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ADC Integrator 1 Implementation

+ -

+-

1

1

Cint

2

11

1

11

1

2

2

22

22

2

D

D

DD

Cin

Cref+

-Vref

Cref Cin

Cint

Caaf

antialias filterwith external C

Raaf Vin-

D*Vref-

H(z)Vin D

ADC data feedback ADC signal input

+

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Feedback Architecture Concept

D*Vref-

H(z)Vin D

ADC:prior art showsgood linearity, only 1 critical block

sampling

H(s)Vout

D*Vref

discrete time continuous time

-H(z)

Vout’

DAC: only 1 critical block,distortion sources attenuated inside loop.But loop is not purelydiscrete time!

sampling

settling distortion

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Integrator 1 Implementation

+ -

+-

1

1

Cint

Vout2

11

1

11

1

2

2

22

22

2

D

D

DD

Cfb

Cref+

-

+

-Vref

Cref Cfb

Cint

Caa

Raa

ADC data feedback becomes DAC data input

ADC signal input becomes DAC signal feedback

antialias filterwith external C

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Integrator 1 opamp

Vout- Vout+Vin+ Vin-

cmfb cmfb

+ +--

Folded cascode opamp with gain boosting and power managementReference: Kasha, ESSCIRC ‘98

Vb Vb

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A fundamental distortion source

Vout

time

Verror

time

signal dependent errorwhen observed in continuous time

perfectly settled value, does not reflect settlingdistortion - need for ‘smoothing’

error is a sequence of impulses

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Spectrum of Signal Dependent Settling Waveforms

fs 2*fs n*fs (n+1)*fs

VERROR(ω)

frequency

Distortion images near fs similar in size to in-band harmonicsContinuous time application sees only in-band harmonicsSampling will alias the distortion images into bandLoop gain will attenuate aliased distortion, not continuous timedistortionAnti-alias filter is needed

aliasingAAF

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Antialias Filtering2 filter stages with 50kHz cutoff achieve >40dB attenuation at fs to allow -80dB THD from glitchesdoubles as reconstruction filter in the DACSingle stage OTA, non-inverting, into capacitive load

Vout

antialias filter D*Vref

sampling

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Circuits: Quantization noise filter

VoutD*Vref

sampling

1st order Qnoise attenuation

switched cap outputobserved in continuous time

2 stage Butterworth filter

filtering of quantization noise needed. Noise rises 4th order at 400 Hz

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Need high loop gain for distortion attenuation, but cannot afford large UGBW because of quantization noise attenuation

Circuit blocks for loop gain

VoutD*Vref

sampling

A resonator formed by two integrators in feedback - extra loop gain

A cascade of 3 integrators provides high gain at low frequencies without requiring high UGBW

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Stability: multipath feedforwardcompensation

Architecture is similar to delta-sigma modulator loop3 integrators cause 270 degrees of phase lag Feed-forward paths create LHP zeros At UGBW phase lag is reduced to less than 180o

Conditionally stable system

VoutD*Vref

feedforward paths

References: Nyquist (1930), Eschauzier (1996 (KAP)), Thomsen (1998(VLSI Circ))

Block F [Hz]I1 2200I2 1000I3 700Fres 160LPF 6000

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-150-100-50

050

100150

1 10 100 1000 10000 100000 1000000

-270

-180

-90

0

1 10 100 1000 10000 100000 1000000

Transfer Function of the switched cap section

-18dB/oct

-18dB/oct

30o PM

2 LHP zeros

gain [dB] vs. frequency [Hz]

phase Vs frequency [Hz]

w/o resonancewith resonance

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Output CircuitsOutput buffer

preceding loop gain relaxes requirements Target THD < -70dB into 1K Ohmlow power class AB implementation: 1.5mWUGBW: 1MHz 6B gain reduces swing of internal nodes

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Output Circuits 2Output can be taken from buffer or from resampling network –both should have the same linearityResampling

Sampling best done from large charge reservoir (only external C)passive AAF cuts high frequency noise from output stage before sampling

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Complete DAC Architecture

Vout'

Integrator Qnoise filter antialias filter AAF 1 buffer

AAF2

D*Vrefx2

sampling

Vout

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Results: In-band spectrumAmplitude [dB] vs frequency [Hz]

-160

-120

-80

-40

0

0 100 200 300 400

THD = 110dBSNR = 114dB in 400Hz

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Results: Out of band noise

total noise less than 2.5mVrms

signal output at -40dBfs

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Results: Measured step response

0dBfs: demonstrates robustness of complex system

-20dBfs: large overshoot due to low phase margin

-8

-6

-4

-2

0

2

4

6

8

0 0.005 0.01 0.015 0.02

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0 0.005 0.01 0.015 0.02

differential voltage [V] vs. time [s]

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Results: Measured performancetechnology 0.6 µm DPTM CMOSarea 3.6 mm2

power 18 mW at 5VTHD 110 dB into 1kΩSNR in 400Hz 114 dBfstotal output noise <-50dBdifferential output swing 5 Vppinput sampling frequency 1024 kHzmax signal bandwidth 100 Hz

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Integrator1Integrator1

output output bufferbuffer

I2I2

I3I3

Qnoise Qnoise filterfilter

AAF AAF filterfilter

Chip photo

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ConclusionPresented a low distortion, low power DAC in 0.6µm CMOS process

A DAC architecture with only 1 critical circuit building block leveraged of ADC design knowledge

Analysis of a fundamental distortion source at the discrete time to continuous time interface

Presented design and stability analysis of a conditionally stable loop