Ch.3 - Exercises Solutions

Q.1Calculate the baseband noise power of a second order modulator with OSR=256 and feedback levels ±1V.

Solution:The noise power is:

10 log( π4

15OSR5 )=−112.2dBW

Q.2Calculate the signal to quantization noise ratio of a second order modulator with input amplitude -3 dBFS (full-scale), OSR=256 and feedback levels ±1V.

Solution:

SQNR=10 log (0.25 )+112.2=118.2dB

Q.3A second order modulator is to achieve a 16-bit resolution and operate at a sampling frequency of 10 MHz and ±1V feedback levels. Calculate the maximum baseband frequency that can be obtained.

Solution:

16-bit resolution = 6.02 x 16 =96.32 dB -> SNR=10 log ( 15OSR5

2 π4) therefore OSR=152. This

implies a baseband of 10 MHz/(2 x 152) = 35.4 KHz.

Q.4Calculate the amplifier gain required to reduce the dead zone width of a second order sigma-delta modulator with feedback levels ±1V to below 100 μV .

Solution:Dead zone = 1.5/A2 = 100e-6 so A=122.5

Q.5Analyze the Boser-Wooley modulator of Fig.3.15 in paragraph 3.7.2. Determine expressions for the noise transfer function NTF(z) and signal transfer function STF(z).

Solution:

Analyzing the Boser-Wooley model yields:

V=Y +E

W=( a1 z−1

1−z−1 ) (U−V )−Vb

Y= (Y +W ) soY=W a2 z

−1

1−z−1

V=E+W a2 z

−1

1−z−1

V=E+( a1 z−1

1−z−1 )( a2 z−1

1−z−1 )(U−V )−Vba2 z

−1

1−z−1

V (1−z−1 )2=E (1−z−1 )2+a1a2 z−2U−a1a2 z

−2V−Vba2 z−1(1−z−1)

V [(1−z−1 )2+a2bz−1 (1−z−1)+a1a2 z−2 ]=E (1−z−1)2+a1a2 z−2U

Therefore:

STF ( z )=a1a2 z

−2

(1−z−1 )2+a2b z−1 (1−z−1 )+a1a2 z

−2

NTF ( z )= (1−z−1 )2

(1−z−1 )2+a2b z−1 (1−z−1 )+a1a2 z

−2

Q.6Analyze the modulator shown in Fig.3.17.

Fig. 3.17 Error-Feedback MOD2 Block Diagram

Determine expressions for the noise transfer function NTF(z) and signal transfer function STF(z).

Solution:

E=V−Y

Y=U +z−1 ( z−1−b ) E

V=U+ z−1 ( z−1−b ) E+E

V=U+ (1−b z−1+z−2 ) E

STF ( z )=1∧NTF ( z )=(1−b z−1+z−2)

Q.7Determine the optimum value of the coefficient b in Fig.3.17 for second order noise shaping. Assuming b is mismatched by 1%, perform a Simulink® simulation to determine the maximum SQNR obtainable from the modulator at OSR=64 and full scale ±1. Compare this to the value obtainable without mismatch. Discuss your results.

Solution:If b=2 the NTF ( z )=(1−z−1)2

1% of b=2 implies b=1.98

Roughly 72 dB peak SQNR is reduced to 50 dB (see the folder - 0_Exercises->Q7_mod2_ErrorFeedback - for the model).

The Error-Feedback architecture is very sensitive to mismatch in the coefficient b. Therefore it is typically not used in analog realisations but is a common architecture in digital DACs/PLLs.

Q.8What effects does finite integrator opamp gain have on the performance of a Sigma-Delta ADC? Are second order modulators sensitive to this non-ideality?

Solution:Modulators lose the ability to achieve infinite precision with DC signals due to the limited gain of the integrators. Therefore, dead zones appears which increase the noise and distortion in the modulator. MOD2 is still affected by finite integrator gain, however, compared to MOD1 is much more tolerant thanks to the higher loop gain (i.e. 1.5/A2).

Q.9Briefly explain the issue of integrator saturation in a MOD2. How can be avoided?

Solution:

In a real MOD2, the large amplitude of the output signal of the integrators (i.e. especially of the second integrator forming the loop filter) may lead to amplifier saturation, due to the limited headroom set by the power supplies. If clipping occurs, large distortion is introduced, as proven by the results obtained. Therefore, due to the very low tolerance of MOD2 to the even slightest integrator overload, it is apparent that such issue should be carefully considered during the design, either by reducing the input range of the modulator or by scaling the internal signals of the modulator appropriately.

Q.10Discuss the advantages and disadvantages of adding dither to Sigma-Delta modulators.

Solution:Using dither would aid the recovery of dead zones by preventing the modulator from locking into limit cycles. It would result that the modulator will behave much more like the ideal case of infinite integrator gain. However, the use of dither would reduce the maximum stable input range of the modulator as well as increase the noise level, which consequently would reduce the peak SQNR achievable.

Q.11For a second order low-pass Sigma-Delta modulator, briefly explain the requirements for the integrators forming the loop filter.

Solution:The first integrator has the most stringent requirements because it always contains both the input signal and the feedback error, therefore, it has to exhibit good settling, slew rate, etc. behaviors. The second integrator has the problem of the possible rapid growth of its output state, which may lead to clipping and distortions. Therefore, it results wise to limit the input of MOD2 to |u|<0.8∨0.9 so that the state of the second integrator is not unduly large. However, even though such an input limit will keep the modulator state reasonable for DC and slowly-varying inputs, it is still possible for the modulator state to become much larger than intended. Therefore, it is important to include means for detecting overly large states and for placing the modulator in a "good" state. This would ensure stability since second order modulators recover from a state where the integrators are saturated as soon as the input is restored to a lower amplitude.

Q.12Create a Simulink® model of the second order Silva-Steensgaard modulator and simulate the SQNR for a sinewave input of 12 KHz at -3 dBFS. Use the default settings of the - load_par - routine. Further plot a graph of the SQNR for different amplitudes of the input sinewave.

Solution:Open the - sweep_testbench - model, right click on the - Modulator - block and change the -Model Reference Parameter - to - Q12_mod2_SilvaSteensgaard - which can be found in the folder - 0_Exercises->ch3. Type - simu.select=2 - into the Matlab Command Window and run the simulation. Type - mod_SNDR - into the Matlab Command Window and record the SQNR, which should be approximately 71 dB. Therefore confirming the operation expected for a

MOD2 modulator. To plot a graph of the SQNR for different amplitudes of the input sinewave use the - sweep_sinamp - routine. Note to type - target_mod='MODEL_NAME'; - into the Matlab Command Window before running the sweep simulation.

Q.13Briefly explain the advantages and disadvantages of using a second order modulator instead of the simple MOD1.

Solution:Compared to MOD1, the reader should have noticed that MOD2 behaves much more closely to an ideal modulator than MOD1 [3, 10]:

Tonal limit cycles are still seen for DC inputs, but the strong signal-band tonal behavior seen with MOD1 is less apparent.

Related to the above, the modulator output spectrum for sinewave inputs (and with no quantizer dither) generally follows the shape of the NTF better, lacking the many strong tones superimposed on the NTF that are usually seen with MOD1.

Considerably higher SQNR can be achieved at a given OSR by MOD2.

Since there are two integrators providing DC gain before the quantizer, dead zone behavior when using real integrators with finite DC gain is much improved over MOD1.

Care must be taken to avoid integrators clipping in real modulators, especially when high SQNR is to be achieved.

Consequently, unlike MOD1 which is plagued by non-ideal behaviors, basic MOD2 and its variants, such as those examined in section 3.7, are commonly seen in practice.

Despite the relatively better performance of MOD2 seen in this chapter, achieving an extremely high SQNR (e.g. >> 100 dB) may still require unacceptably high OSRs [3, 10]. Recall that, for a given signal bandwidth of interest (e.g. a 24 kHz audio band), increasing the OSR increases the speed that any analog circuits in the modulator must operate on (e.g. for an OSR of 64 an audio modulator will operate at f s = 24x2x64 = 3072 kHz). If the OSR requirement becomes too high to achieve the target SQNR, then the modulator design may become unacceptable in other regards, such as:

Excessively high power consumption to achieve very fast integrator settling in analog modulators, or small adder's delays in digital modulators.

Excessively high power consumption to achieve very small quantizer's delays.

Often a sufficiently fast clock may not be available in the system and so a dedicated modulator clock must then be generated, e.g. by adding a PLL with its associated circuits costs and power requirements (i.e. the modulator's clock requirements can be further complicated by the fact that the modulator data must then synchronize to

the rest of the system, ideally without the further complication of needing sample rate conversion if the modulator and system clocks do not have simple ratios such as 1:2, 1:1.5, etc.).

In extreme cases, the circuit speeds required to achieve the necessary OSR may even exceed the various speed limits of the medium in which the modulator is to be realized (e.g. available MOS transistor fT and/or channel transit times in ICs).

In very high SQNR applications (e.g. > 100 dB), a higher-order modulator such as MOD3 operating at moderate OSR can thus be a better solution than MOD2 operating at very high OSR. However, increasing the modulator order above two introduces other problems, such as possible loop instability due to each integrator adding further loop phase, which degrades phase margins.