hotcarriereffectshot carrier effectsbandi.chungbuk.ac.kr/~ysk/devnot11.pdf · 2011-04-09 ·...
TRANSCRIPT
Hot Carrier EffectsHot Carrier Effects
충북대학교 전자정보대학 김영석
2 12 32012.3
1
Evolution of MOSFET technologyITRS predictions in 2009
2005, λ=90nm2011, λ=40nm, vdd=0.9V, tox,eff=1nm
2017 λ 162017, λ=16nm
2전자정보대학 김영석
Moor’s LawIC complexity roughly doubles every 2 years” Gordon Moore, 1965
Higher Density
But, Hot Carrier Effects
3전자정보대학 김영석
ScalingDennard (IBM) in 1974
Constant Electric Field Scaling
4전자정보대학 김영석
ScalingThreshold Voltage VTH
V
CQ
VVVox
depFFBoxsiFBTH
+
−++=Δ+Δ+=
)2(2
2
εφε
φφφ
VqNCQ
tCWqNQ
qNVW
SBFsubsidep
ox
oxoxdepsubdep
sub
SBFsidep
+=
−
==−+
=
/)2)((2
,,)2(2
φε
εφε
kV
tkkVqkN
VV
tC
TH
oxox
SBFsubsisiFBTH
oxoxox
=+
+Δ+≈/
)/2)((2:scalingafter
/
'
εφε
φ
ε
Drain Current
D l
kIkVkV
kLkWkCI D
THGSoxnD =−≈ 2' )//(//)(
21 μ
WLCCVC GSGS 2Delay
kkIkVkC
WLCCI
D
GSGS
oxGSD
GSGS
ττ
τ
==
≈=
/)/)(/(
3,
'
Power Consumption
' )/)(/( PkVkIP DD ==
5
2)/)(/(k
kVkIP DD
전자정보대학 김영석
MOSFET ReviewCross-section
Depletion
0 < VGS < VTH
S bth h ld tSubthreshold current
Inversion
VGS >= VTHVGS > VTH
6전자정보대학 김영석
MOSFET: ID @ InversionLinear Region
ID ~ VDS
Voltage controlled resistor (VGS)
Pi h ffPinch-off
VDS=VDSAT
Saturation RegionSaturation Region
VDS => Leff slowly
Vchannel=VDSAT=const
Pinch-off section absorbs (VDS-VDSAT), high-field region, electron velocity saturationvelocity saturation
Hot Carrier Injection
Large lateral electric field
Population of high-energy electrons
7전자정보대학 김영석
Scaling => 채널길이 감소Lateral E-field (drain) 증가 (>100kV/cm)=> Hot-Carrier 발생 (E>1.5eV)
Impact Ionization(I/I) or Avalanche Breakdown
Isub 증가 => 기판전압증가, Snapback 발생
I 증가 > O id T / VT 증가Ig 증가 => Oxide Trap/ VT 증가
Hot Carrier Effects(HCI)
8전자정보대학 김영석
Substrate Currents Mechanism
Electron Energy > 1.5eV
=> Impact Ionization
> El t H l i ti=> Electron-Hole pair generation
전자는 드레인 or 게이트로 이동
정공은 기판으로 이동 (Isub)정공은 기판으로 이동 (Isub)
Isub can be used to predict the device lifetime
9전자정보대학 김영석
Substrate Currents Difference between Electrons and Holes: pn μμ ⋅≈ 3
Electron-Hole pair generation by Electrons: Energy>1.5eV
Electron-Hole pair generation by Holes: Energy>2.4eV
p
10전자정보대학 김영석
Substrate Currents(Isub) 문제점Breakdown 발생: 정공 기판으로 이동 => 기판 전압 상승 => 소스-기판 순방향바이어스 => 소스에서 전자들이 기판으로 방출 (기생 npn BJT동작) => More I/I => Snapback Breakdown
CMOS Latch-Up 유발CMOS Latch Up 유발
Back Bias Generator 전압을 올림
드레인-기판 공핍영역에서 정공에 의한 Secondary Impact-Ionization 발생
A monitor to correate device degradation with lifetime
Device Degradation/Isub are driven by a common source: Emax
11전자정보대학 김영석
Hot-Carrier Injection into Gate Oxide 게이트 산화막으로 주입된 대부분의 전자들은 게이트 전극으로 이동 ( 약 fA - pA).
이중 1/1E6 정도의 전자들은 게이트 산화막에 trap됨
Negative Charge => VT 증가 => 전류감소
12전자정보대학 김영석
Nature of Gate Oxide DamageHCI increases with shrinking
L , xj , tox , Nsub => E(lateral), E(vertical) (significant)
HCI
2 D O id h t i I t f t ti2 Damages: Oxide charge trapping, Interface trap generation
Very localized
gm , VTH , IDgm , VTH , ID
2 Voltage Regions
VDS ~ 2VGS: Sat. region, Ech large, I/I, Max substrate current, Interface trap generation (no Oxide charge trapping)
VDS ~ VGS: Linear region, Ech small, no I/I, Hot electron injection into oxide, Oxide charge trapping (Less Interface trapinto oxide, Oxide charge trapping (Less Interface trap generation)
13전자정보대학 김영석
MOSFET Degradation 3단계(1) Impact Ionization
E>1.5eV
Substrate Current 증가
(2) O id b i 넘기(2) Oxide barrier 넘기
E>3.2eV
Lucky electron modelLucky electron model
Gate Current 증가
(3) Oxide Interface Trap 생성
E>3.7eV
gm 감소(VTH 증가)
14
(1) Impact IonizationChannel hot electron(CHE) injection
Impact Ionization(I/I) injection
(or Drain avalanche hot carrier(DAHC) injection)
15전자정보대학 김영석
Impact Ionization by Hot-ElectronsElectrons are accelerated by the E-field
Get sufficient energy to break the covalent bond
Impact-Ionization=Avalanche Breakdown
I b li bl d i t it f th t f h tIsub: a reliable and convenient monitor of the amount of hot-carrier degradation
16전자정보대학 김영석
Impact Ionization by Hot-Electrons
Isub ~ IDS * Pi
Pi = the probability of an electron travelling a sufficient distance to gain the kinetic energy or more without suffering a collision
E/Φ λiΦ
eVeP
i
Eqi
mi
5.1~energy ionizationimpact : where
/
Φ= Φ− λ
Substrate current
mi EqDSsub eICI λ/
1Φ−= DSsub 1
17전자정보대학 김영석
Fowler-Nordheim (FN) TunnelingPrimarily by Eox
Localized at the source (maximum Eox at the Source)
⎟⎟⎞
⎜⎜⎛ −
= CEJ βexp2
Nonsignificant (But Significant for very thin oxide)
⎟⎟⎠
⎜⎜⎝
=ox
oxT ECEJ exp
Nonsignificant (But Significant for very thin oxide)
18전자정보대학 김영석
Direct TunnelingDirect Tunneling occurs in thin oxide at low voltages
For tox<3nm, Direct Tunneling Current>Thermal generation Current
No Inversion layer in MOS-C
2 5 i th Li it?2.5nm is the Limit?
Also Shown are Interface-Trap Assisted Leakage Paths
19전자정보대학 김영석
(2) Ig: Lucky Electron ModelP1(A to B): Channel Electrons gain kinetic energy from the lateral channel electric field
P2(B): The Momentum of the hot electron must be redirected toward the interface by a Quasi-Elastic Collisiontoward the interface by a Quasi Elastic Collision
No energy-robbing collision
Retain the kinetic energy
Ped(B to C): Travel without suffering further collisions
Poc(C): Oxide scattering factor
20전자정보대학 김영석
Lucky Electron ModelLucky Electron Model
eVeIIII
i
chsubchGi
5.1~energy thresholdionization:/~/ /
Φ
ΦΦ−
V2.3~energybarrier injection :Φ
21전자정보대학 김영석
(3) Oxide DegradationOxide Degradation
Oxide Charge Trapping
Interface Charge Trapping => 치명적
Ch f D i h t i ti d t id dChange of Device characteristics due to oxide damage
gm decrease
VTH increaseVTH increase
Oxide trapped charge / Interface trapped charge : Important role in the device degradation due to HCI
22전자정보대학 김영석
Si/SiO2 Interface Charges① Mobile Ions
윈인: Na+, K+ ions
성질: 이동성이 좋음. 특히 BT(Bias-Temperature) Stressing시 Na+ 이온이 산화막에서 이동하여 VFB가 변화함이온이 산화막에서 이동하여 VFB가 변화함.
제거방법:
i) Phosphorus(PSG등) Stabilization => Na+가 PSG층으로 이동하여 Trap됨.p 등 가 층으로 이동하여 p됨
ii) Chlorine Neutralization => Na+가 Cl(HCl,Cl2)과 결합하여 NaCl 형성
=>Neutral
② Fixed Charge
윈인: 산화과정시 생기는 Excess Ionic Silicon으로 추정됨.
성질: Positive Si/SiO2 interface에 위치 Metal성질: Positive, Si/SiO2 interface에 위치,
(111)Wafer는 (100)보다 3:1정도로 QF 많음.
제거방법: Ar, N2 Annealing으로 2E11cm-2 정도로
Metal
Trapped Charge+++ K+, Na+
Mobile Ions
제거방법 으로 정도로
줄일 수 있음.SiO2----
Interface Traps
X X X X
Fixed Charge+ + + +
23
Si
전자정보대학 김영석
Si/SiO2 Interface Charges③ Interface Traps(Surface States)
윈인: Si/SiO2 Interface에서 Dangling Bond에 의해 Forbidden Band에생기는 Energy State
성질: Donorlike/Acceptor Trap 두종류 있음성질: Donorlike/Acceptor Trap 두종류 있음,
Si/SiO2 interface에 위치, VG의 함수
제거방법: PostMetallization or Hodrogen Ambient Annealing => 제거방법 g g
Hydrogen이 Dangling Bond와 결합하여 QIT 제거.
(DIT= 1010 states/cm2-eV)
④ Radiation Effects: x-rays, Energetic Electrons, Protons,Heavy Ionized Particles에 의해 QF/QIT 증가시킴
Metal
제일큼영향/
)(
ox
SIT
ox
MM
ox
FMSFB
CQC
QC
QCQV
Φ
−−−Φ=φγ
SiO2
Trapped Charge+++----
K+, Na+Mobile Ions
제일큼영향 /, oxFMS CQΦ
Si
Interface Traps
X X X X
Fixed Charge+ + + +
24전자정보대학 김영석
Fixed oxide chargeSi-SiO2 atomic model
Si dangling bond
Oxygen dangling bond
B th d li b d l t /h l TRAPBoth dangling bond : electron/hole TRAP
SiN : nitrogen dangling bond
25전자정보대학 김영석
Threshold Voltage Shift
0@FGpp VVQCVV + 0@
FGTHiTH
DSoxpp
FG
oxpp
ppCGFG
QVV
VVCC
QCC
VV
−=
==+
++
=
)22(2 0 FFSBTHdep
FFBTHi
oxppTHiTH
VVCQ
VV
CCVV
φφγφ −++=−+=
+
)(0 FFSBTHox
FFBTHi Cφφγφ
26전자정보대학 김영석
CharacterizationVFG 영향
A region: Electrons(Ich) 증가 => I/I 증가
B region: Emax 감소 => I/I 감소
VD 영향VD 영향
VD 증가 => Emax 증가 => I/I 증가
Leff 영향Leff 영향
Leff 감소 Emax 증가 => I/I 증가
27전자정보대학 김영석
CharacterizationISUB vs VD
VTH vs time
Lifetime vs ISUB
28전자정보대학 김영석
Device DegradationHCI
=> VTH 감소, 전류 IDS 감소, gm 감소
=> Circuit Speed 감소
> Ci it F il=> Circuit Failure
29전자정보대학 김영석
Device LifetimeIn General, Device Lifetime is defined by
%3
10
=Δ
=Δ
D
T
II
mVV
%3=Δ m
D
gg
I
mg
30전자정보대학 김영석
Techniques to Reduce HCIReduce Maximum Electric Field (Emax)
Reduce VDD
Gate Oxide Engineering for higher reliability (e.g., oxynitrides)
St t t t th t th f EStructure to separate the current path from Emax
31전자정보대학 김영석
LDD(Lightly Doped Drain)Hot Carrier Effect 방지를 위한 소자 구조
LDD(Lightly Doped Drain)
32전자정보대학 김영석
SummarySubstrate Current by Impact Ionization
G t C t b L k El t
(1) /1
mi EqDSUB eICI λϕ−=
Gate Current by Lucky Electrons
(2) /2
mb EqDG eICI λϕ−=
(1)+(2)
(3))( / ibSUBG II ϕϕ∝ (3) )( ib
D
SUB
D
G
IIϕϕ∝
oxide barrier toenergy :2.3IonizationImpact create energy to :3.1
eVeV
b
i
==
ϕϕ
33전자정보대학 김영석
SummaryDevice Lifetime by Interface Traps (IG, ISUB)
eIWC Eq
D
mit /5
(4)(1)
(4) =τ λϕ
II
IW SUB iit / (5) )(
(4)(1)
∝
+
−τ ϕϕ
WII
II
SUB
D
DD
9.2
9.1
∝∴τSUB
TI t ftt73 V
34
TrapsInterfacecreateenergy to :7.3 eVit =ϕ
전자정보대학 김영석
SummaryLifetime: Ex
AI
mWAIAI
SUB
SUBD
/103
60,10,10
129.2
64 ===
−
−− μ
years
mAWID
SUB
31sec101
/103
9
129.1
=×≈∴
×≈
τ
μ
Note that Li-Ion battery: 2 years, 400회
35전자정보대학 김영석
ReferencesHot Carrier Design Considerations for MOS Devices and Circuits, C. T. Wang, Van Nostrand Reinhold, 1992
Hot-Carrier Reliability of MOS VLSI Circuits, Y. Leblebici and S. M. Kang, Kluwer Academic Publishers, 1993Kang, Kluwer Academic Publishers, 1993
36전자정보대학 김영석